CORDIC accelerator system and method for scaling factor compensation

Abstract

The invention provides a CORDIC accelerator system and method for scaling factor compensation, and the system comprises an angle preprocessing module, an angle decoder module and a four-stage pipeline calculation module, and the angle preprocessing module maps an input angle Zin to a first angle interval, generating a corresponding reference angle selection signal, an initial angle and symbol information at the same time; the angle decoder module is connected with the output end of the angle preprocessing module and converts a reference angle selection signal into an initial horizontal coordinate and an initial vertical coordinate; and the four-stage assembly line calculation module is connected with the output end of the angle decoder module and the output end of the angle preprocessing module, performs four-stage iterative calculation based on 2 power series approximation according to the initial horizontal coordinate, the initial vertical coordinate, the initial angle and the symbol information, and outputs a final horizontal coordinate and a final vertical coordinate. According to the system and the application method thereof, the hardware resource consumption is reduced, and the calculation speed is greatly improved.

Description

CORDIC accelerator system and method for scaling factor compensation Technical Field

[0001] This invention belongs to the field of integrated circuit design, and specifically relates to a CORDIC accelerator system and method for scaling factor compensation. Background Technology

[0002] The coordinate rotation digital computer (CORDIC) algorithm was first proposed by Volder in 1959. Its core advantage lies in transforming complex calculations involving trigonometric functions, hyperbolic functions, and coordinate transformations into simple shift and addition / subtraction operations, eliminating the need for complex hardware units such as multipliers and dividers. Therefore, it is widely used in integrated circuit design, becoming a core computing module in embedded systems and signal processing chips. The basic iterative formula of CORDIC is: (1) (2) Rotation matrix: (3) Rotation angle: (4) In the existing technology, the hardware implementation of the CORDIC algorithm is mainly based on a serial iterative architecture. Its core hardware components include: X / Y / Z registers (which store the X coordinate, Y coordinate and residual angle of the current iteration, respectively), shifters, an arithmetic logic unit (ALU, which implements addition and subtraction operations), an angle comparison and selection module, and a scaling factor compensation multiplier. Its specific working process is as follows: 1. Initialization: Input angle Map the coordinates to the convergence interval of the CORDIC algorithm, and initialize the X register as the initial x-coordinate, the Y register as the initial y-coordinate, and the Z register as the initial angle after mapping. Simultaneously, n sets of fixed micro-rotation angles are pre-stored. (generally ).

[0003] 2. Serial iteration: according to From 0 to Execute in sequence The hardware operation process for each iteration is as follows: a) Direction determination: The angle comparison module determines the sign of the current residual angle in the Z register and determines the rotation direction control signal. ( = 1 indicates counterclockwise rotation. = -1 indicates clockwise rotation); b) Shift operation: The shifter, based on the current iteration number i, shifts X... i and Y i Perform right shift by i bits (corresponding to multiplying by 2) respectively -i ,adaptation hour , c) Addition and subtraction operations: ALU based on The symbol, execution , Operations (" " " Depend on Decide, Use "-" or "+" when taking time. (d) Residual angle update: ALU synchronous execution. 3. Scaling factor compensation: After writing the updated residual angle back to the Z register. After the iteration, the residual angle in the Z register is less than the preset threshold (meeting the accuracy requirements), but the outputs of the X and Y registers need to be multiplied by the scaling factor. (Because of each iteration) (Introducing scaling effects), therefore X needs to be executed via a multiplier. final =X n ×K、Y final =Y n The compensation operation of ×K ultimately yields the cosine value (X) corresponding to the input angle. final ) and sine value (Y final ).

[0004] The latency of the above serial iterative hardware architecture is "iteration count × single-step latency", specifically analyzed as follows: 1. Single-step latency (tstep): refers to the total latency of the hardware critical path during a single iteration. Since each module needs to complete its operation sequentially in serial iteration, the critical path includes: the sign determination latency (tcomp) of the angle comparison module, the shift operation latency of the shifter (tshift, positively correlated with the data bit width), the addition and subtraction operation latency of the ALU (talu, positively correlated with the bit width and carry chain length), and the write-back latency of the register (treg). Therefore, the single-step latency tstep = tcomp + tshift + talu + treg, and its value is determined by the hardware process, data bit width, and module design, and is usually a fixed value.

[0005] 2. Total Delay (ttotal): Since serial iteration requires that the (i+1)th iteration can only start after the i-th iteration has completely finished (i.e., the iteration process has no parallelism), the total delay is the product of the number of iterations n and the single-step delay tstep, i.e., ttotal = n × tstep. For example, if 10 is required... -5 For computational precision of orders of magnitude, traditional serial architectures typically require 16-20 iterations. If the single-step delay is 1ns, the total delay can reach as high as 16-20ns.

[0006] However, the traditional CORDIC algorithm and the above-mentioned serial iterative hardware architecture have the following drawbacks in practical applications: (1) The convergence speed is slow, and it is necessary to increase the number of iterations to improve the computational accuracy. The delay and area will also increase with the increase of the number of iterations, which is not suitable for scenarios with high real-time requirements. As shown in the above delay analysis, the total delay increases with the number of iterations. Linear growth. To improve computational accuracy, the number of iterations must be increased. This leads to a sharp increase in total latency, and the hardware area also increases due to the expansion of iterative control logic and register sets.

[0007] (2) There is a scaling factor compensation problem. In the iterative process of the traditional CORDIC algorithm, each rotation introduces a scaling factor compensation problem. The scaling factor necessitates compensation of the final calculation result. This requires the design of an additional multiplication compensation circuit, which not only increases hardware resource consumption but also introduces additional computational latency, reducing system operating efficiency.

[0008] (3) The residual angle processing is coarse and the iteration efficiency is low: the micro-rotation angle of the traditional serial architecture is poor. To maintain a fixed step size, the only way to increase the number of iterations is to... To reduce the residual angle, it is not possible to deal with small residual angles (such as Z in the later stages of iteration). i A fine approximation is performed using values ​​< 0.01 rad. This results in a large number of redundant iterations being required to achieve the target accuracy, further exacerbating the contradiction between "iteration count - latency - area".

[0009] To reduce the number of iterations and lower latency, some methods employ search algorithms such as Angle Recoding (AR), Modified Vector Rotation (MVR), and Extended Basic Angle Set (EEAS) to reduce the number of micro-rotations required for a given rotation angle. However, reducing the number of micro-rotations necessitates variable scaling factor multiplication, thus outweighing the advantages gained from the reduced number of micro-rotations. Some methods minimize the time overhead of the scaling factor by merging iterations and scaling operations in hybrid-scale rotations and parallel scale factor compensation. However, while reducing the number of iterations, they do not refine the residual angles, resulting in limited overall performance improvement, larger computational errors, and lower accuracy.

[0010] Some methods utilize the concepts of uniform scaling and user-friendly angles to optimize the latency of the CORDIC algorithm. This requires left-shift operations to achieve micro-rotations, but these operations increase the internal bit width to maintain the required accuracy. Some methods propose scaling factor-free compensation approaches that approximate the rotation matrix using Taylor series expansions of sine and cosine. However, the factorial terms in the Taylor series cannot be precisely expressed as quadratic powers, making them hardware-incompatible. Furthermore, the solutions proposed in these methods directly approximate the factorial term 3! as 2.2 Furthermore, only the first two terms of the expansion were used, resulting in significant errors in the calculation results and reduced accuracy. Additionally, for iterations with small residual angles, multiplication was directly employed, impacting the critical path latency and leading to higher hardware resource overhead.

[0011] The above methods either lead to an increase in area and power consumption, or reduce accuracy and increase the error of the calculation results. Summary of the Invention

[0012] This invention addresses the aforementioned problems by proposing a CORDIC accelerator system and method for scaling factor compensation. The concept involves simplifying the hardware through mathematical transformation, converting the factorial terms of the sine and cosine Taylor expansions in traditional algorithms into combinations of power series of 2, and employing a four-stage iterative calculation of different power series. The remaining angle after the third stage is processed using shift-addition operations, thereby saving hardware resources and reducing latency.

[0013] In a first aspect, this invention proposes a CORDIC accelerator system for scaling factor compensation, comprising an angle preprocessing module, an angle decoder module, and a four-stage pipelined computation module. The angle preprocessing module processes the input angle Z... in Mapped to The first angle interval is used to simultaneously generate the corresponding reference angle selection signals sel1 and sel0, the initial angle Z0, and the sign information sign-bit (Z0) (i.e., the highest bit of the input angle); the decoder is connected to the output of the angle preprocessing module to convert sel1 and sel0 into the initial horizontal coordinate. and initial ordinate The four-stage pipeline calculation module connects the output of the decoder and the output of the angle preprocessing module, based on the initial x-coordinate. Initial ordinate The initial angle Z0 and sign-bit (Z0) symbol information are used to perform iterative calculations based on a power-series approximation in four stages: Stage-1, Stage-2, Stage-3, and Stage-4, to output the final x-coordinate X. res and the final ordinate Y res .

[0014] More specifically, Stage-1, Stage-2, and Stage-3 each contain X i Iterative calculation circuit, Y i Iterative calculation circuit, comparator, and iterative residual angle Z iThe calculation circuit includes a comparator input for Stage-2 and Stage-3 connected to an iterative output angle absolute value calculation unit. This unit calculates the remaining angle Z output in the previous stage. i-1 The absolute value of Z; the comparator will... i-1 The absolute value of X is compared with a preset threshold, and X is controlled based on the comparison result. i Iterative computation circuit and Y i The iterative calculation circuit iterates over the coordinates output from the previous stage; iterates over the remaining angle Z. i The calculation circuit updates the remaining angle Z based on the comparison result. i And input it into the next stage.

[0015] More specifically, the X i Iterative calculation circuit, Y i The iterative calculation circuits all include cos shifters and sin shifters implemented based on power series of 2, which are used to realize rotation calculations without scaling factors.

[0016] More specifically, Stage-4 consists of an angle fine-tuning step size selection circuit, an X4 calculation circuit, and a Y4 calculation circuit, wherein the angle fine-tuning step size selection circuit calculates the remaining angle output by Stage-3. The values ​​are converted to absolute values ​​to select the fine-tuning step size k. The X4 and Y4 calculation circuits iteratively calculate the x-coordinate X3 and y-coordinate Y3 of Stage-3 based on the fine-tuning step size k, respectively, and perform sign correction on the results, outputting the final x-coordinate X. res and the final ordinate Y res .

[0017] More specifically, the refinement step size k is an integer from 0 to 32.

[0018] Secondly, the present invention proposes a calculation method for the above-mentioned system, comprising the following steps: S1. Angle preprocessing step, wherein any input angle Z is processed... in =θ, θ∈(-π,π), map θ to the first angle interval (0, π / 4), and generate reference angle selection signals sel1 and sel0 and sign information sign-bit(Z0); S2. Initial value loading step, based on the reference angle selection signals, select the initial coordinates corresponding to the quadrant to which the input angle θ belongs ( , S3. Four-stage pipeline rotation steps, using four stages: Stage-1, Stage-2, Stage-3, and Stage-4, to adjust the initial coordinates ( , The iterative rotation calculation is performed on the angle values ​​within the first angle interval, wherein: Stage-1, Stage-2, and Stage-3 perform micro-rotations without scaling factors based on a power series approximation of 2, wherein the trigonometric function values ​​corresponding to the angle increment required for each micro-rotation are approximated by a Taylor series expansion containing finite terms, and the factorial coefficients in the Taylor series expansion are converted into a power series summation form of 2; Stage-4 performs a residual angle refinement rotation, the purpose of which is to optimize the multiplication operation in the micro-rotation into a shift and addition operation; S4. Result output step, according to the sign information, the coordinate values ​​output by the residual angle refinement rotation of Stage-4 are sign-corrected to obtain the final iterative coordinates (X). res Y res ).

[0019] Preferably, in step S3: Stage-1 performs a rotation angle of 2. -1 The Stage-2 selects a rotation angle of 2 based on the absolute value of the remaining angle. -2 or 2 -3 The micro-rotation, and by sharing the rotation angle of 2 -2 With 2 -3 The common subexpression in the power series approximation of 2 is used to reduce hardware consumption; Stage-3 selects to perform a rotation angle of 2 based on the absolute value of the remaining angle. -4 or 2 -5 The micro-rotation.

[0020] Preferably, whether Stage-1, Stage-2 and Stage-3 perform rotation depends on whether the remaining angle output in the previous stage meets the preset rotation conditions. The rotation conditions are set based on the rotation angle threshold of the corresponding stage to ensure that micro-rotations of different rotation angles within the same stage are executed mutually exclusively.

[0021] Preferably, the residual angle refinement rotation performed by Stage-4 specifically involves: refining the residual angle output by Stage-3. The absolute value is expressed in vector form. = 2048 + j·k, where k is an integer from 0 to 32; according to formula Z d = | | × ² Calculate the intermediate value Z d And extract Z d The lower 6 bits of the binary value are used to determine the value of k; based on the value of k, the final iterative coordinate (X) is calculated through shift and addition operations. res Y res ).

[0022] Thirdly, the present invention proposes an electronic device for a CORDIC accelerator system with scaling factor compensation.

[0023] The innovations of this invention include: 1. Scaling factor compensation: Existing accelerators have additional multiplication compensation circuits, which not only increase hardware resources (multipliers occupy large areas and consume high power), but also introduce computational delays. Some use Taylor series expansion, but the approximation error of the factorial terms is relatively large (e.g., 3!≈2²). This invention simplifies the hardware through mathematical transformation, converting the factorial terms (1 / 3!, 1 / 4!, 1 / 5!) of the sine and cosine Taylor expansion into a power series combination of 2 (e.g., 1 / 3!≈2). -1 - 2 -2 (1+2 -2 +2 -4 (+...)), fully adaptable to hardware shift-addition operations, with dedicated cos / sin shifters designed for each stage, eliminating the need for additional compensation circuit hardware overhead.

[0024] 2. Regarding the number of iterations: Traditional accelerators require a large number of iterations (requiring repeated use of the same hardware units), leading to increased area. While some optimization schemes (such as AR and MVR) reduce the number of iterations, they require additional variable scaling factor multipliers, offsetting the area advantage. This invention adopts a 4-stage pipeline (Stage-1 to Stage-4), with clearly defined functions for each stage. Compared to existing serial iterative hardware, the latency is reduced from "number of iterations × single-step latency" to "number of pipeline stages × single-step latency," improving real-time performance. The rotation angle is combined into the same stage through shared sub-circuits, avoiding redundant design of shifters and adders and reducing hardware redundancy. The hardware implementation of shared common expressions (such as the cos / sin shifter in Stage-2 switching the rotation angle via a two-to-one MUX) eliminates the need for separate circuit design for each iteration, significantly reducing area.

[0025] 3. Regarding residual angle processing: Existing solutions for small angles (residual angles) either use multipliers, leading to increased latency; or use left shift operations, resulting in internal bit width expansion (requiring additional hardware to maintain accuracy); or are approximately coarse, leading to large errors. The Stage-4 of this invention iteratively multiplies the residual angle (d×k×2). -11 × / This is transformed into a shift-add operation, implemented using a k value (0~32, represented by powers of 2), eliminating the need for a multiplier; it is achieved by right-shifting by 2 bits (| |×2 -2The k value is obtained directly, requiring only a shift register in the hardware, without the need for complex calculation units. Furthermore, the lower 6 bits of the k value are directly mapped to the shift weight, simplifying control. The X4 / Y4 calculation circuit (as shown in Figures 7c and 7d) adopts a "MUX + shift register + adder" structure, based on Z... d The position (Z) d [0]~Z d [5]) Select the shift result, the adder merges all valid terms, the hardware structure is compact, and the bit width is controlled within 2. -13 Within (to avoid bit width expansion).

[0026] The beneficial effects of the present invention include: 1. Eliminating scaling factor compensation overhead, reducing hardware resource consumption and latency.

[0027] 2. The number of iterations is reduced and a pipelined architecture is adopted, which greatly improves the computing speed.

[0028] 3. Residual angle refinement ensures high accuracy while reducing iterations.

[0029] 4. Hardware structure optimization, balancing complexity and practicality. By merging iteration stages, sharing sub-circuits, and using shift addition instead of multiplication, performance is improved while controlling hardware complexity: the four-stage pipelined computing module has a high degree of modularity, with each stage circuit implemented based on power-law shift and addition, without complex arithmetic units, making it easy to integrate and place and route hardware. Attached Figure Description

[0030] Figure 1 is a structural diagram of the CORDIC accelerator system for scaling factor compensation according to the present invention.

[0031] Figure 2 is a structural diagram of the angle preprocessing module of the present invention.

[0032] Figure 3 is a structural diagram of the four-stage pipeline calculation module of the present invention.

[0033] Figure 4a is a circuit diagram of Stage-1 of the present invention.

[0034] Figure 4b is a schematic diagram of the X1 iterative calculation circuit of Stage-1 of the present invention.

[0035] Figure 4c is a schematic diagram of the Y1 iterative calculation circuit of Stage-1 of the present invention.

[0036] Figure 4d is a circuit diagram of the iterative residual angle calculation circuit of Stage-1 of the present invention.

[0037] Figure 5a is a circuit diagram of Stage-2 of the present invention.

[0038] Figure 5b is a schematic diagram of the X2 iterative calculation circuit of Stage-2 of the present invention.

[0039] Figure 5c is a schematic diagram of the Y2 iterative calculation circuit of Stage-2 of the present invention.

[0040] Figure 5d is a circuit diagram of the iterative residual angle calculation circuit of Stage-2 of the present invention.

[0041] Figure 5e is a circuit diagram of the absolute value calculation unit of Stage-2 of the present invention.

[0042] Figure 6a is a circuit diagram of Stage-3 of the present invention.

[0043] Figure 6b is a schematic diagram of the X3 iterative calculation circuit of Stage-3 of the present invention.

[0044] Figure 6c is a schematic diagram of the Y3 iterative calculation circuit of Stage-3 of the present invention.

[0045] Figure 6d is a circuit diagram of the iterative residual angle calculation circuit of Stage-3 of the present invention.

[0046] Figure 6e is a circuit diagram of the absolute value calculation unit of Stage-3 of the present invention.

[0047] Figure 7a is a circuit diagram of Stage-4 of the present invention.

[0048] Figure 7b is a schematic diagram of the fine step size selection circuit of Stage-4 of the present invention.

[0049] Figure 7c is a schematic diagram of the X4 iterative calculation circuit of Stage-4 of the present invention.

[0050] Figure 7d is a schematic diagram of the Y4 iterative calculation circuit of Stage-4 of the present invention. Detailed Implementation

[0051] The specific structure and operation of the present invention will be further described below with reference to the accompanying drawings.

[0052] The optimization method proposed in this invention mainly includes: (1) using a power series of 2 to approximate the sine and cosine rotation matrix to achieve the purpose of compensation without scaling factor. The algorithm optimization was carried out for the sine and cosine shifter. According to the algorithm optimization, the computational structure of the CORDIC accelerator is divided into a 4-stage pipeline structure; (2) optimizing the multiplication of small angle rotation iteration in stage 4 into a shift addition structure to achieve the purpose of refining the residual angle; (3) sharing common expressions to merge the rotation angle into the same pipeline stage to reduce the number of iterations.

[0053] For algorithm optimization without scaling factor compensation, the sine and cosine representations in the rotation matrix are approximated using Taylor series, as shown in the expression: (5) (6) First of all, it is about Preliminary approximation work has been done: =2 -i To balance error and hardware complexity, the hardware complexity of the terms after the fourth term in the expansion is relatively high and the error optimization effect is small. Therefore, the algorithm only selects the first three terms in the Taylor expansion.

[0054] In the Taylor expansion above, because of the factorial term, it is not possible to effectively represent the coordinate iteration using a power series of 2. Therefore, the factorial term is processed as follows: (7) For , can be used (8) is used to approximate the factorial term, therefore the coefficient of the factorial term is... This can be approximated as a power series of 2 using the above method: (9) The number of terms to be expanded can be selected according to the accuracy requirement level, i.e., the allowable error range. Similarly, for coefficients... and ,have (10) (11) will Substitution It can be obtained (12) The final sine and cosine expressions are: (13) (14) s and c are positive integers that vary with the number of iterations i and the input bit width.

[0055] Similarly, to balance hardware circuit complexity and error, the input angle is a 16-bit word length, consisting of 1 bit sign + 2 bits integer + 13 bits decimal. Therefore, the truncated power-2 term must be controlled within 2. -13 Within.

[0056] For the optimization of the residual angle, after 3 iterations, the residual angle is less than 0.015625 rad (0.895°). 0.015625 can be represented as a vector P = 2048 + j32(32 / 2048). Therefore, for any angle with a residual angle less than 0.015625 rad, the above vector form P can be used. k The iteration is performed using 2048 + jk (k = 0~32). 2048 can be represented well in hardware, and the iteration expression is: (15) (16) The optimization made in this invention is to transform the multiplication operation in equations (15) and (16) into a shift-addition operation. Therefore, based on the remaining angle size... ,like If ∈[m, m+1], then k=m (m=0~32). m can be represented by powers of 2, and thus the coefficient k can be represented by powers of 2, thereby replacing the multiplication operation in the expression.

[0057] Rotation error = |Approximate value - Actual value|. According to Table 1, the rotation error can be controlled within 10. -5 and below the order of magnitude.

[0058] Based on the above calculation principle, the CORDIC accelerator system for scaling factor compensation constructed in this embodiment is shown in Figure 1. It includes an angle preprocessing module, an angle decoder module, and a four-stage pipelined computation module. The angle preprocessing module processes the input angle Z... in Mapped to The first angle interval is determined, and corresponding reference angle selection signals sel1 and sel0, initial angle Z0, and sign-bit (Z0) information are generated simultaneously. The decoder is connected to the output of the angle preprocessing module, converting sel1 and sel0 into initial x-coordinate X0 and initial y-coordinate Y0. The four-stage pipelined calculation module is connected to the output of the decoder and the output of the angle preprocessing module, and performs iterative calculations in four stages (Stage-1, Stage-2, Stage-3, and Stage-4) based on the initial x-coordinate X0, initial y-coordinate Y0, initial angle Z0, and sign-bit (Z0) sign information, outputting the final x-coordinate X0. res and the final ordinate Y res .

[0059] Table 1. Power series approximations of sine and cosine 2 under different iteration angles and their rotation errors.

[0060] In Table 1, 'i' represents the order of rotation angle, corresponding to a rotation angle of 2. -i rad.

[0061] Based on the power series approximation terms of 2 in Table 1, in the 4-stage pipeline structure, the iteration at i=1 involves a large number of shift and addition terms. Therefore, Stage-1 only performs a rotation angle of 2. -1 The iteration. A common expression exists in the sinusoidal approximation of i=2 / i=3. Therefore, the iterations for i=2 / i=3 are merged into Stage-2. The number of approximation terms for i=4 / i=5 is relatively small, so they are merged into Stage-3. Stage-4, as the stage for refining the residual angle, optimizes the multiplication into a refined shift and addition structure.

[0062] Table 2 Initial values ​​for different input angle ranges

[0063] Table 2 lists the initial values ​​corresponding to different angle ranges. Based on the even symmetry of the cosine function and the odd symmetry of the sinine function, if the input angle is negative, simply change the Y-axis of the final iteration result. res Simply invert the value; if the input angle range is within ( , If the result is between X and X, then you only need to calculate the result X. res Simply invert it.

[0064] Table 3. Rotation angles and conditions corresponding to each stage of the four-stage pipeline calculation unit.

[0065] Table 3 lists the rotation angles and rotation conditions for each Stage. Since i=2, 3 and i=4, 5 were merged separately, i=2, 3 and i=4, 5 are mutually exclusive and cannot be executed simultaneously in the same Stage. Therefore, rotation conditions are distinguished by angle thresholds to ensure that only one iteration is triggered in the same Stage. Here, the median threshold of the rotation angles within the same Stage is used as the rotation condition. The remaining angle after calculation for Stage-3 is less than 0.015625 rad (i.e., the maximum remaining angle, represented in vector form as P = 2048 + j32). The rotation angle for Stage-4 is a refined rotation based on the ratio of the remaining angle of Stage-3 to the maximum remaining angle (i.e., the k value).

[0066] The specific structure of the angle preprocessing module is shown in Figure 2. First, the angle Z is input. in With the sign-bit (Z) signal in After passing through XOR logic, the output of the XOR gate is ANDed with the sign-bit (Z). in The absolute value of the angle |Z is output through the adder. in The logic of the XOR gate and adder is to convert the input angle into its absolute value form. If the input angle is positive, the output is the angle itself; if the input angle is negative, it is processed in two's complement form and then passed to the next level of logic. Afterwards, a range judgment is performed on the absolute value to ensure that the output angle Z0 is controlled within the range (0, ...). Within the range: 1. If the comparator comparison result T3 < |Zin | <T4(T3= T4= The output of the two-choice MUX is Z0 = T4 -|Z in If I3 = 1, I2 = 0, I1 = 0, I0 = 0, output sel1 = 1, sel0 = 1; otherwise, MUX outputs |Z. in | Proceed to the next level interval for judgment; 2. If the comparator comparison result T2 < |Z in | <T3(T2= T3= The output of the two-choice MUX is Z0 = T3 - |Z in If I3 = 0, I2 = 1, I1 = 0, I0 = 0, output sel1 = 1, sel0 = 0; otherwise, MUX outputs |Z. in | Proceed to the next level interval for judgment; 3. If the comparator comparison result T1 < |Z in | <T2(T1= T2= ), the output of the two-choose-one MUX is Z0=|Z in If |-T1, I3 = 0, I2 = 0, I1 = 1, I0 = 0, output sel1 = 0, sel0 = 1; otherwise, MUX outputs |Z. in | Proceed to the next level interval for judgment; 4. If the comparator comparison result is 0 < |Z in | <T1(T1= ), the output of the two-choose-one MUX is Z0=|Z in |, I3 = 0, I2 = 0, I1 = 0, I0 = 1, output sel1 = 0, sel0 = 0; the comparison results of the four comparators are connected to the inputs I3, I2, I1, and I0 of the 4-to-2 encoder, respectively. The 4-to-2 encoder outputs selection signals S1 and S0 to the decoder based on the inputs. The decoder outputs the corresponding X0 and Y0 according to Table 2. The processed angle Z0 and the sign information sign-bit (Z0) are given to the input of the 4-stage pipeline module.

[0067] Figure 3 illustrates the internal structure of the four-stage pipelined computation module. The outputs Z0 and sign-bit(Z0) from the angle preprocessing module, as well as the outputs X0 and Y0 from the decoder module, serve as inputs to the four-stage pipelined computation module. After passing through the four-stage pipelined computation module, the final output result X is obtained. res Y resFigure 4a shows the overall circuit structure of Stage-1 in the pipeline structure. Input Z0 outputs a control signal S through a comparator, which is then fed to the X1 and Y1 iterative calculation circuits and the iterative remaining angle Z1 calculation circuit. The comparator compares Z0 with 0.25 rad; if Z0 > 0.25 rad, S = 0; otherwise, S = 1. Inputs X0 and Y0 are connected to the X1 and Y1 iterative calculation circuits, which output X1 and Y1 respectively. Input Z0 is connected to the iterative remaining angle Z1 calculation circuit, which outputs Z1. The circuit structures shown in Figures 4b and 4c are based on the basic iterative formula of the CORDIC algorithm. and The result is as follows. For the output logic of X1, the input X0 passes through a cosine shifter, and the input Y0 passes through a sin shifter. The outputs of both are then connected to a 2-to-1 multiplexer after passing through two adders. The control signal of this 2-to-1 multiplexer is the sign-bit (Z0). If the input angle is positive, then d... i =1 (counterclockwise rotation), if the input angle is negative, then d i = -1 (clockwise rotation). The output of the 2-to-1 MUX and X0 are used as the inputs of the next stage 2-to-1 MUX. The output of X1 is selected based on whether the rotation condition Z0 > 0.25 rad is met. If Z0 > 0.25 rad (i.e., S = 0), then the angle iteration of i = 1 is executed; otherwise, Stage-1 is skipped, and the output of X1 remains X0. Similarly, for the output logic of Y1, the output of Y0 after the cos shifter is added to (or subtracted from) the output of X0 after the sin shifter to obtain the result of Y1. If the rotation condition is not met, the output of Y1 remains Y0. Stage-1 has two shifters, which are used for the power-of-2 approximation optimization of the cosine and sin functions, respectively. The circuit structure of the shift register and adder is obtained according to the number of approximation terms of i = 1 in Table 1. The outputs of the two shifters correspond to the basic iterative formulas in the following ways. and The remaining angle Z1 output by Stage-1 is determined based on the sign of Z0 and the rotation condition. If the rotation condition is met and the sign is positive, then Z1 = Z0 - 0.5 rad; if the sign is negative, then Z1 = Z0 + 0.5 rad; otherwise, Z1 = Z0, as shown in Figure 4d.

[0068] Figure 5a shows Stage-2 in the pipeline structure. Input Z i-1 |Z| is obtained by iteratively outputting the absolute value of the angle calculation unit. i-1 |, the absolute value|Z i-1 The S control signal is output from comparator 1 and given to X. i Y i Iterative calculation circuit and iterative residual angle Zi Calculate the circuit, if |Z i-1 |>2 -4 If the value is less than or equal to rad, then S = 0; otherwise, S = 1. |Z i-1 The SEL control signal is output from comparator 0 and given to X. i Y i Iterative calculation circuit and iterative residual angle Z i The value of sel in the circuit calculation is determined by the rotation conditions in Table 3. If |Z i-1 |>(2 -2 +2 -3 If the value is 0, then sel = 0; otherwise, sel = 1. Input X. i-1 Y i-1 With X i Y i The iterative calculation circuit is connected to calculate the output X. i Y i Input Z i-1 With the remaining angle Z of the iteration i The circuit connection is calculated, and Z1 is obtained. According to the approximation terms shown in Table 1, there is a common term among the sin approximation terms listed for i = 2 and i = 3. Therefore, i = 2 and i = 3 are combined in Stage-2 to reduce hardware consumption by sharing sub-circuits. The circuit structures shown in Figures 5b and 5c are also derived from the basic iterative formula. Before outputting X2 and Y2, it is also necessary to determine whether the rotation condition |Z is satisfied. i-1 |> 2 -4 The value of S is rad (i.e., the value of S). If the condition (S = 0) is met, X2 and Y2 output the result of the shifted addition logic; otherwise, Stage-2 is skipped, and X2 and Y2 remain X1 and Y1. The cos and sin shifters are obtained based on the approximate number of terms i = 2 / 3 in Table 1. Since the rotation angle is 2... -2 With 2 -3 The merging operation has been optimized by adding a 2-to-1 MUX before the shifter output. The selection signal sel of the MUX is transmitted through |Z. i-1 The value of | is used to determine the rotation angle, which is selected as 2 based on the rotation conditions in Table 3. -2 / 2 -3 The iteration. Figure 5(d) shows the circuit for calculating the remaining angle after Stage-2 iteration. The principle is the same as Stage-1, and it also checks whether the rotation condition is met. If |Z i-1 |> 2 -4If the angle is less than or equal to rad, then perform angle iteration for i = 2 or 3 (the rotation condition for i = 2 or i = 3 is determined according to Table 3); otherwise, skip Stage-2. The circuit shown in Figure 5e performs an absolute value operation on the remaining angle output from Stage-1 to prevent the remaining angle from being negative after the Stage-1 iteration.

[0069] Figure 6a shows Stage-3 in the pipeline structure. The overall circuit connection of Stage-3 is similar to that of Stage-2. Stage-3's X... i Y i The cosine and sinine shifters in the iterative calculation circuit are obtained based on the approximate number of terms i = 4 or 5 in Table 1. This is because, similarly, for a rotation angle of 2... -4 With 2 -5 The merging operation has been optimized by adding a 2-to-1 MUX before the shifter output. The selection signal sel of the MUX is transmitted through |Z. i-1 The value of | is used to determine the rotation angle, which is selected as 2 based on the rotation conditions in Table 3. -4 or 2 -5 The iteration continues. The remaining circuit logic is consistent with Stage-2.

[0070] Figure 7a shows Stage-4 in the pipeline structure. Figure 7a shows the overall circuit structure of Stage-4. The output is obtained through a fine-tuned angle step selection circuit. , The lower 6 bits are connected to the X4 and Y4 iterative calculation circuits. X3 and Y3 are connected to the X4 and Y4 iterative calculation circuits respectively, and the final outputs X4 and Y4 are calculated.

[0071] Figure 7b is a schematic diagram of the fine-tuned angle step size k selection circuit for Stage-4. After iteration through Stage-3, the remaining angle is less than or equal to 0.015625 rad. Expressing 0.015625 as a vector, we get P = 2048 + j32. Therefore, this invention proposes to express the absolute value of the remaining angle Z3 after Stage-3 iteration as P3 = 2048 + jk (k = 0, 1, 2..., 32), where 2048 (2...)... 11 This is convenient for hardware implementation. The value of k is generated through the circuit shown in Figure 7b. During the calculation, all angles are represented using 16-bit fixed-point numbers (1 bit sign + 2 bits integer + 13 bits decimal). The 16-bit fixed-point number is obtained by multiplying the actual input angle (all angles in the four-stage pipeline calculation module have been converted to positive angles) by 2. 13 The value of k is obtained by converting the input angle to binary form. Therefore, when calculating the value of k, the input angle is first... Convert to | |,| Multiply by 2 -13 Then multiply by 2048 (2 11 )get , The lower 6 bits correspond to the decimal number of k, thus yielding the simple right-shifted two-bit circuit structure shown in Figure 7b. The calculation process for the value of k is as follows: (17) (18) Combining equation (18), the iterative expressions (15) and (16) are rewritten as follows: (19) (20) obtained (twenty one) (22) Substituting the k-value into the expression eliminates the influence of the extended bit width of the left shift register. The calculation circuit structures for X4 and Y4, built sequentially, are shown in Figures 7c and 7d, respectively. In the circuit structure shown in Figure 7c, the input Y3 is input into six shift registers, and the outputs of the shift registers are input into six 2-to-1 MUX selectors. The MUX selectors are configured according to their weights. The value [m] (m=0, 1, 2...5) is used to determine whether to output the shifted result or output 0, i.e., no shift. The outputs of the 6 MUX selectors are added together by an adder and then input into a right shift register. The sign of d is determined based on the sign information sign-bit(Z3) of the input angle Z3 in Stage-4. If the input angle is positive, then d... i = 1 (counterclockwise rotation), if the input angle is negative, then d i = -1 (clockwise rotation), the output of the last stage MUX is X4, which is the final X. res The result is shown in Figure 7d. The circuit structure is similar to that in Figure 7c, but considering the case of negative angle input, based on the even symmetry property of the cosine function and the odd symmetry property of the sine function, the following settings are made: if the input angle is negative, then Y4 is inverted to obtain the final Y. res The result, after shifting, adding, and the MUX selector, is XORed with the sign-bit (Z3). The output of the XOR operation is then added to the sign-bit (Z3) to obtain the final Y4 output. If the input angle is positive, the XOR addition is skipped, and the Y4 result is output directly. If the input angle is positive and the angle range is within (…), the output is Y4. , If the value is within 1000, then XOR it with the sel1 signal (the sel1 signal is the output signal sel1 of the angle preprocessing module). The output of the XOR logic is then added to the sel1 signal to obtain the final X4 output.

Claims

1. A CORDIC accelerator system for scaling factor compensation, characterized in that: It includes an angle preprocessing module, an angle decoder module, and a four-stage pipelined calculation module. The angle preprocessing module processes the input angle Z... in Mapped to The first angle interval is determined, and corresponding reference angle selection signals sel1 and sel0, initial angle Z0, and sign-bit (Z0) are generated simultaneously. The decoder is connected to the output of the angle preprocessing module and converts sel1 and sel0 into initial horizontal coordinates. and initial ordinate ； The four-stage pipeline calculation module connects the output of the decoder and the output of the angle preprocessing module, based on the initial x-coordinate. Initial ordinate The initial angle Z0 and sign-bit (Z0) symbol information are used to perform iterative calculations based on a power-series approximation in four stages: Stage-1, Stage-2, Stage-3, and Stage-4, to output the final x-coordinate X. res and the final ordinate Y res .

2. A CORDIC accelerator system for scaling factor compensation according to claim 1, characterized in that: Stage-1, Stage-2, and Stage-3 each contain X i Iterative calculation circuit, Y i Iterative calculation circuit, comparator, and iterative residual angle Z i The calculation circuit includes a comparator input for Stage-2 and Stage-3 connected to an iterative output angle absolute value calculation unit. This unit calculates the remaining angle Z output in the previous stage. i-1 The absolute value of Z; the comparator will... i-1 The absolute value of X is compared with a preset threshold, and X is controlled based on the comparison result. i Iterative computation circuit and Y i The iterative calculation circuit iterates over the coordinates output from the previous stage; iterates over the remaining angle Z. i The calculation circuit updates the remaining angle Z based on the comparison result. i And input it into the next stage.

3. A CORDIC accelerator system for scaling factor compensation according to claim 1, characterized in that: The X i Iterative calculation circuit, Y i The iterative calculation circuits all include cos shifters and sin shifters implemented based on power series of 2.

4. A CORDIC accelerator system for scaling factor compensation according to claim 1, characterized in that: Stage-4 consists of an angle fine-tuning step size selection circuit, an X4 calculation circuit, and a Y4 calculation circuit. The angle fine-tuning step size selection circuit calculates the remaining angle output from Stage-3. The values ​​are converted to absolute values ​​to select the fine-tuning step size k. The X4 and Y4 calculation circuits iteratively calculate the x-coordinate X3 and y-coordinate Y3 of Stage-3 based on the fine-tuning step size k, respectively, and perform sign correction on the results, outputting the final x-coordinate X. res and the final ordinate Y res .

5. A CORDIC accelerator system for scaling factor compensation according to claim 1, characterized in that: The refinement step size k is an integer from 0 to 32.

6. A calculation method for a CORDIC accelerator system with scaling factor compensation according to claim 1, comprising the following steps: S1. Angle preprocessing step: This involves processing any input angle Z... in =θ, θ∈(-π,π), map θ to the first angle interval of (0, π / 4), and generate reference angle selection signals sel1 and sel0 and symbol information sign-bit(Z0); S2. Initial value loading step: Based on the reference angle selection signal, select the initial coordinates corresponding to the quadrant to which the input angle θ belongs. ， S3. Four-stage pipeline rotation steps, using four stages: Stage-1, Stage-2, Stage-3, and Stage-4, to adjust the initial coordinates ( ， The iterative rotation calculation is performed on the angle values ​​within the first angle interval, wherein: Stage-1, Stage-2, and Stage-3 perform micro-rotations without scaling factors based on a power series approximation of 2, wherein the trigonometric function values ​​corresponding to the angle increment required for each micro-rotation are approximated by a Taylor series expansion containing finite terms, and the factorial coefficients in the Taylor series expansion are converted into a power series summation form of 2; Stage-4 performs a refined rotation of the residual angle; S4. Result output step: according to the sign information, the coordinate values ​​output by the refined rotation calculation of the residual angle in Stage-4 are sign-corrected to obtain the final iterative coordinates (X). res Y res ).

7. The calculation method for a CORDIC accelerator system with scaling factor compensation according to claim 6, characterized in that, In step S3: Stage-1 performs a rotation angle of 2. -1 The Stage-2 selects a rotation angle of 2 based on the absolute value of the remaining angle. -2 or 2 -3 The micro-rotation, and by sharing the rotation angle of 2 -2 With 2 -3 The common subexpression in the power series approximation of 2 is used to reduce hardware consumption; Stage-3 selects to perform a rotation angle of 2 based on the absolute value of the remaining angle. -4 or 2 -5 The micro-rotation.

8. The calculation method for a CORDIC accelerator system with scaling factor compensation according to claim 6, characterized in that: Whether Stage-1, Stage-2 and Stage-3 perform rotation depends on whether the remaining angle output from the previous stage meets the preset rotation conditions. The rotation conditions are set based on the rotation angle threshold of the corresponding stage to ensure that micro-rotations of different rotation angles within the same stage are executed mutually exclusively.

9. The calculation method for a CORDIC accelerator system with scaling factor compensation according to claim 6, characterized in that, The residual angle refinement rotation performed by Stage-4 specifically involves: refining the residual angle output by Stage-3. The absolute value is expressed in vector form. = 2048 + j·k, where k is an integer from 0 to 32; according to formula Z d = | | × 2 -2 Calculate the intermediate value Z d And extract Z d The lower 6 bits of the binary value are used to determine the value of k; based on the value of k, the final iterative coordinate (X) is calculated through shift and addition operations. res Y res ).

10. An electronic device that carries the system of claims 1-5.

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