Packaging system of multi-chip integrated module based on silicon carbide device

Abstract

The invention relates to the technical field of semiconductor packaging and intelligent chips, and particularly discloses a silicon carbide device-based multi-chip integrated module packaging system, which comprises a design simulation platform, a stress buffering and interconnection integration unit and a packaging process monitoring and feedback unit. And designing a simulation platform to carry out electric-thermal-mechanical multi-physics field co-simulation and structure optimization. The stress buffer and interconnection integrated unit physically realizes an optimized structure through the adaptive stress buffer layer and the standardized three-dimensional interconnection frame. And the packaging process monitoring and feedback unit acquires process data in real time and performs adaptive compensation to form a design-manufacturing closed loop. The thermal mechanical stress can be actively managed, the interconnection process is unified, and intelligent control of the manufacturing process is realized, so that the module reliability and the manufacturing yield are improved, and the development period is shortened.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging and smart chip technology, specifically relating to a packaging system for a multi-chip integrated module based on silicon carbide devices. Background Technology

[0002] In the field of power electronics, power semiconductor devices are the core components for achieving efficient power conversion and control, and their performance directly determines the efficiency, power density, and reliability of the entire power electronic system. With the rapid development of industries such as new energy vehicles, rail transportation, and renewable energy power generation, unprecedented demands are being placed on the ability of power modules to operate at high temperatures, high frequencies, and high power densities.

[0003] Power devices based on silicon carbide (SiC), a wide-bandgap semiconductor material, are gradually replacing traditional silicon-based devices due to their superior characteristics such as high breakdown electric field, high thermal conductivity, and high electron saturation drift velocity, becoming key to realizing next-generation high-efficiency, compact power conversion systems. Integrating multiple SiC chips with auxiliary chips such as drivers and protection devices into a single module is an important technological direction for achieving system miniaturization and performance improvement.

[0004] The packaging of multi-chip integrated modules faces a series of integration challenges. The significant differences in the coefficients of thermal expansion between various material systems, such as silicon carbide chips, silicon-based driver chips, ceramic substrates, and metal interconnect layers, make them prone to thermomechanical stress under power cycling and temperature shocks, leading to interface delamination or solder layer fatigue failure. The complex integration of multiple processes makes it difficult to control the cumulative tolerances of chip mounting, wire bonding, and molding, directly impacting manufacturing yield and long-term reliability. Furthermore, the complex three-dimensional interconnect and heat dissipation structures used to meet high power density requirements have lengthy design and simulation verification cycles, and the lack of standardized integration solutions results in high costs and time risks from design to mass production. Summary of the Invention

[0005] The purpose of this invention is to provide a packaging system for a multi-chip integrated module based on silicon carbide devices, in order to solve the problems in the prior art such as thermomechanical stress failure caused by the mismatch of thermal expansion coefficients of multiple materials, difficulty in controlling the cumulative tolerance of multi-process integration, long design and verification cycle of complex three-dimensional interconnect and heat dissipation structure, and lack of standardized solutions.

[0006] This invention provides a packaging system for a multi-chip integrated module based on silicon carbide devices. This system, centered on layered collaborative design, active stress management, and digital integration of the process chain, constructs a closed-loop system from design simulation to physical packaging and online monitoring. The system includes a design simulation platform, a stress buffer and interconnect integration unit, and a packaging process monitoring and feedback unit.

[0007] The design simulation platform is used to perform co-simulation and optimization of the electrical, thermal, and mechanical multiphysics behavior of modules before physical packaging. The platform includes a materials database, a multiphysics coupling simulation engine, and a structural optimization module. The materials database pre-stores precise physical parameters of silicon carbide chips, silicon-based driver chips, various types of ceramic substrates, solders, metallization layers, molding compounds, and various substrate materials. These parameters include, but are not limited to, coefficients of thermal expansion, Young's modulus, Poisson's ratio, thermal conductivity, specific heat capacity, and resistivity. The multiphysics coupling simulation engine, based on the finite element method, simultaneously solves the electrical-thermal-mechanical coupling equations constructed from the parameters provided by the materials database to predict the temperature distribution, current density distribution, and resulting thermal stress and deformation fields within the module, from the chip junction temperature to the package shell, under preset power cycling conditions and temperature shock conditions. The structural optimization module receives the prediction results output by the multiphysics coupling simulation engine and iteratively optimizes the module's interconnect topology, chip layout, heat dissipation path, and key structural dimensions according to preset optimization objective functions and constraints. The objective function aims to minimize the maximum thermal stress and maximum junction temperature, while constraints ensure that electrical performance parameters and mechanical strength are not lower than the design thresholds.

[0008] The stress buffer and interconnect integration unit is used to physically realize the optimized structure output by the design simulation platform. Its core lies in introducing an active stress management mechanism and standardized interconnect interfaces. This unit includes an adaptive stress buffer layer, a standardized three-dimensional interconnect framework, and a gradient thermal management structure. The adaptive stress buffer layer is positioned between the silicon carbide power chip and the ceramic substrate. This buffer layer is composed of a metal matrix composite material and an embedded micro-spring array. The metal matrix composite material serves as the main body, and its coefficient of thermal expansion is designed to be between that of the silicon carbide chip and the ceramic substrate. The embedded micro-spring array is pre-embedded in the composite material in a specific spatial arrangement. The stiffness coefficient of the micro-springs is differentiated according to the power level and position of the chip above them. During temperature changes, the micro-springs actively absorb and redistribute interfacial shear stress through their own elastic deformation.

[0009] A standardized 3D interconnect framework provides a unified vertical interconnect and horizontal routing interface for all chips, including silicon carbide power chips and silicon-based driver chips. This framework employs a multi-layer redistribution structure, with vertical interconnects achieved between layers via microvia arrays. Each redistribution layer is etched with a standardized pad array and routing channels. Power chips connect to the standardized pads on the bottom layer of the framework via copper pillar bumps, while driver chips connect to corresponding pads on the upper layers of the framework via finer-pitch microbumps, thus unifying the diverse interconnect requirements of heterogeneous chips within a single interconnect framework.

[0010] The gradient thermal management structure consists of a microchannel liquid cooling unit integrated into the bottom of the ceramic substrate and a pin-fin heat sink on the upper surface of the package. The flow topology of the microchannel liquid cooling unit is customized based on the chip heat source distribution output from the design simulation platform to ensure targeted and enhanced cooling of the high heat density silicon carbide chip area. The pin-fin heat sink is combined with the upper surface of the package through a high thermal conductivity interface material to dissipate the heat generated by the driver chip and other components, as well as to assist in heat dissipation, forming a gradient heat dissipation path from the chip to the coolant and then to the ambient air.

[0011] The packaging process monitoring and feedback unit is used to collect key process parameters and intermediate product quality data in real time during the packaging manufacturing process and to establish a data loop with the design simulation platform. This unit is integrated into the packaging production line and includes a multi-sensor array, a data fusion processor, and a process parameter adaptive controller. The multi-sensor array is deployed at multiple key process stations, including chip mounting, wire bonding or bump formation, molding, and reflow soldering. Sensor types include high-precision infrared thermal imagers, laser displacement sensors, in-line optical inspection instruments, and ultrasonic scanning microscopes.

[0012] The data fusion processor receives raw data from a multi-sensor array in real time. For the chip placement station, the processing steps include extracting images of solder or adhesive layer spread and measuring the vertical height and planar angle offset of the chip after placement. For the interconnect formation station, the processing steps include measuring the consistency of bump height and diameter, or the arc height and pull force distribution of the bonding wire. For the molding station, the processing steps include monitoring the temperature and pressure distribution of the molding compound flow front.

[0013] The adaptive process parameter controller has a built-in mapping model between key process parameters and final product quality indicators. This model is generated by the design simulation platform through training on a large amount of virtual process simulation data. The controller compares the real-time feature parameters extracted by the data fusion processor with the standard values ​​in the mapping model. When a feature parameter deviates from the standard value by more than a preset tolerance range, the controller immediately calculates and outputs a compensation adjustment command to the actuator of the corresponding process station. Taking chip mounting as an example, if an out-of-tolerance angle deviation of a chip is detected, the controller will instruct the mounting head to perform attitude fine-tuning compensation at the same position in the next module.

[0014] Furthermore, the configuration method of the embedded micro-spring array in the adaptive stress buffer layer is as follows. First, based on the thermal stress cloud map analysis of a single silicon carbide chip at its maximum operating junction temperature using a design simulation platform, the four corner regions of the chip edge are identified as stress concentration areas. Next, micro-springs with a first stiffness coefficient are configured at the buffer layer positions corresponding to these four stress concentration areas. This first stiffness coefficient is calculated and set to absorb 70% to 80% of the predicted peak shear stress. Then, micro-springs with a second stiffness coefficient, which is smaller than the first stiffness coefficient, are configured in the non-corner regions of the chip edge to absorb the uniformly distributed background stress. Finally, micro-springs with a third stiffness coefficient or only metal matrix composite material are configured in the central region of the chip. The third stiffness coefficient is set to a minimum value or zero to ensure that this region has the highest vertical thermal conductivity, which is beneficial for downward heat conduction.

[0015] Furthermore, the multilayer redistribution layers of the standardized 3D interconnect framework are fabricated using silicon interposer or glass substrate processes. The bottom redistribution layer pad array of the framework has a pitch of 400 micrometers to be compatible with the copper pillar bump spacing of mainstream silicon carbide MOSFETs or diode chips. The top redistribution layer pad array of the framework has a pitch of 150 micrometers to be compatible with the microbump spacing of silicon-based driver and control chips. The diameter of the interlayer microvias is designed to be 50 micrometers, and the vias are filled with electroplated copper. The total thickness of the framework is controlled within 500 micrometers, and standardized mechanical alignment marks and electrical performance test pads are designed around its perimeter to facilitate automated mounting and in-circuit testing.

[0016] Furthermore, the optimization process of the flow channel topology for the microchannel liquid cooling unit in the gradient thermal management structure is as follows. The design simulation platform first divides the bottom region of the ceramic substrate into multiple thermal management units based on the layout and power consumption of the silicon carbide chip. Then, with the goal of maximizing the heat carried away by the coolant in each thermal management unit, and constrained by ensuring that the flow channel pressure drop does not exceed the system's allowable value, computational fluid dynamics simulation is used to iteratively optimize the flow channel width, depth, and tortuous shape of each unit. The resulting flow channel topology exhibits a non-uniform distribution characteristic. In the region directly beneath the chip with high heat flux density, the flow channels exhibit a denser serpentine or pin-rib array structure; in regions with lower heat flux density, the flow channels are simplified to straight-through or less branched shapes.

[0017] Furthermore, the mapping model used by the adaptive controller for process parameters in the packaging process monitoring and feedback unit is constructed as follows: A virtual process simulation module within the simulation platform is designed. By changing key process parameters such as mounting pressure, solder paste volume, bonding power and time, and molding compound preheating temperature, tens of thousands of process samples and their corresponding virtual intermediate product characteristics are generated in the virtual environment. Subsequently, a multiphysics coupling simulation engine is used to predict the electrothermal and mechanical performance and reliability indicators of the final package for each virtual sample. Finally, machine learning algorithms, such as deep neural networks, are used to train the model on massive amounts of process parameters, intermediate features, and final performance indicator data, establishing a nonlinear mapping model from real-time process characteristics to final quality prediction, and then to the required process parameter compensation.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention uses a design simulation platform to perform electro-thermal-mechanical multi-physics collaborative simulation and structural optimization. It accurately predicts and avoids thermomechanical stress risks during the virtual design stage, transforming the traditional serial iterative mode of design-prototyping-testing-failure-redesign into a simulation-based predictive optimization mode. This fundamentally shortens the development cycle of complex three-dimensional integrated modules and reduces trial and error costs.

[0019] 2. The stress buffer and interconnect integration unit proposed in this invention systematically solves the fundamental stress mismatch problem caused by heterogeneous integration of multiple materials by introducing an adaptive stress buffer layer with a gradient of thermal expansion coefficients and a standardized three-dimensional interconnect framework. The programmable micro-spring array in the adaptive buffer layer can actively absorb and redistribute localized concentrated stress, significantly improving the interface reliability of the module under power cycling and temperature shock. The standardized interconnect framework unifies the interconnection process of heterogeneous chips, greatly reducing process complexity and accumulated tolerances, and improving manufacturing yield and consistency.

[0020] 3. The packaging process monitoring and feedback unit constructed in this invention realizes the datafication and intelligentization of the manufacturing process. By collecting process data in real time and comparing it with a virtual simulation-based mapping model, the system can diagnose process deviations online and immediately perform adaptive compensation, moving quality control from final product inspection to every critical manufacturing stage. This closed-loop control mechanism ensures that the physical packaging results can be highly reproduced and optimized, greatly improving the repeatability and product reliability from design to mass production, and providing a systematic solution for the large-scale, high-quality manufacturing of silicon carbide multi-chip integrated modules. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the overall technical solution architecture of the present invention; Figure 2This is a schematic diagram of the core principle framework of the stress buffer and interconnection integrated unit in this invention; Figure 3 This is a flowchart outlining the main stages of the simulation platform design in this invention. Figure 4 This is a schematic diagram of the multi-level interaction relationship and data flow of the encapsulation process monitoring and feedback unit in this invention; Figure 5 This is a schematic diagram of the core principle framework of the gradient thermal management structure in this invention. Detailed Implementation

[0022] Example 1: This invention provides a packaging system for a multi-chip integrated module based on silicon carbide devices, the overall technical architecture of which is shown in the attached figure. Figure 1 To be continued Figure 5 As shown, this system, centered on hierarchical collaborative design, proactive stress management, and digital integration of the process chain, constructs a closed-loop system from design simulation to physical packaging and online monitoring. The system consists of three main functional units: a design simulation platform, a stress buffering and interconnection integration unit, and a packaging process monitoring and feedback unit. These three units achieve seamless information flow through standardized data interfaces, forming a full lifecycle control mechanism encompassing virtual optimization, physical implementation, process verification, and feedback correction.

[0023] First, the design simulation platform will be described in detail. Please refer to the appendix. Figure 3 This platform serves as the decision-making hub for the entire packaging system, enabling collaborative simulation and structural optimization of the module's electrical, thermal, and mechanical multiphysics behavior before physical manufacturing. The platform comprises three core subsystems: a materials database, a multiphysics coupling simulation engine, and a structural optimization module. The materials database pre-stores complete sets of physical parameters for silicon carbide power chips, silicon-based driver chips, alumina or aluminum nitride ceramic substrates, tin-silver-copper solders, copper or nickel metallization layers, epoxy molding compounds, and various high thermal conductivity substrate materials. Each material is labeled with its coefficient of thermal expansion, Young's modulus, Poisson's ratio, thermal conductivity, specific heat capacity, and resistivity. All parameters are derived from authoritative experimental measurements or datasheets from third-party certified material suppliers and are stored in segments according to temperature ranges, ensuring sufficient accuracy within the operating range of -55℃ to 200℃.

[0024] The multiphysics coupled simulation engine constructs a three-dimensional nonlinear transient model based on the finite element method, simultaneously solving a strongly coupled set of equations consisting of Maxwell's equations, Fourier's heat conduction equations, and Navier-Stokes equilibrium equations. Its governing equations can be expressed as:

[0025] in, For stress tensor, For the coefficient of thermal expansion tensor, For Young's modulus, For temperature field, For unit tensors, For density, For specific heat capacity, Thermal conductivity, It is the current density vector. For electrical conductivity, This represents the discrete term for mechanical power consumption. Under given boundary conditions (such as ambient temperature, current input, and constraint displacement), this system of equations calculates the module's global response under typical power cycling conditions (e.g., 100A pulse current for 10ms, with 90ms intervals) and JEDEC standard temperature shock tests (-55℃↔150℃, 5 cycles) using an iterative solver. The output results include a chip junction temperature distribution map, the thermal stress vector field inside the package, the cumulative shear strain curves at each interconnect interface, and the locations of current congestion hotspots on the critical path.

[0026] The structural optimization module receives the above simulation results as input and automatically iteratively adjusts them according to a preset multi-objective optimization function. The optimization objective function is defined as follows:

[0027] in, and This is a weighting coefficient, dynamically set according to the product reliability level, and typically ranges from 0.4 to 0.6. This indicates the maximum thermal stress value within the entire package. This represents the highest junction temperature among all chips. Constraints include: any interconnect width must not be less than 15 micrometers to ensure current carrying capacity; chip spacing must not be less than 200 micrometers to avoid arcing; the flexural deformation of the ceramic substrate must not exceed 5 micrometers to maintain flatness; and the predicted shear strength of all solder joints must be higher than 25 MPa. Optimization variables encompass over 200 degrees of freedom, including the relative layout coordinates of the silicon carbide chip and driver chip, the thickness of the adaptive stress buffer layer, the topology of the redistribution layer, and the geometric parameters of the microchannel flow path. The optimization process employs a gradient-based sequential quadratic programming algorithm combined with a global search strategy, completing at least 50 iterations within 8 hours. The final output is a set of three-dimensional structural parameters that satisfies all constraints and has the optimal overall performance, serving as the sole basis for subsequent physical manufacturing.

[0028] The stress buffer and interconnection integration unit will be described in detail below. Please refer to the appendix. Figure 2This unit is the key actuator that transforms the virtual structure output from the design simulation platform into a physical module. Its core lies in the introduction of an active stress management mechanism and a standardized interconnect interface. The unit consists of three parts: an adaptive stress buffer layer, a standardized three-dimensional interconnect framework, and a gradient thermal management structure. The three parts are vertically stacked in space, forming a complete electrical and thermal conduction path from the chip to the external pins.

[0029] An adaptive stress buffer layer is disposed between the back surface of the silicon carbide power chip and the upper surface of the ceramic substrate, with a thickness controlled within the range of 30 to 80 micrometers. The buffer layer is primarily composed of a copper-tungsten metal-based composite material, and its volume fraction is precisely controlled to achieve an overall coefficient of thermal expansion of 7.2 × 10⁻⁶. -6 / ℃, between silicon carbide (4.0×10 -6 / ℃) and alumina ceramics (6.8×10 -6 The composite material is positioned between 0.5°C and 0.6°C, thereby reducing the overall thermal mismatch. An embedded micro-spring array is pre-embedded within this composite material. This array consists of thousands of independent micro-spring units, each 25 micrometers high and 15 micrometers in diameter, made of electroformed nickel-cobalt alloy, exhibiting high elastic modulus and low creep characteristics.

[0030] The spatial arrangement of the microsprings is not uniform, but rather differentiated based on the stress concentration areas output by the design simulation platform. Specifically, for a single silicon carbide chip, its edge is divided into four corner regions and eight center regions. The microsprings corresponding to the four corner regions are assigned a first stiffness coefficient, set to generate a restoring force of 0.8 N per micrometer of displacement. This stiffness is sufficient to absorb 70% to 80% of the predicted peak shear stress. The microsprings corresponding to the eight center regions use a second stiffness coefficient of 0.3 N / micrometer to absorb background-level uniform stress. The chip center region does not have microsprings, retaining only a pure metal matrix composite material to maximize the vertical thermal conductivity of this region, with a measured value reaching 280 W / m·K. All microsprings are integrally formed during manufacturing using photolithography and electroforming processes. Their top ends are connected to the back of the chip via eutectic bonding, and their bottom ends are embedded in the composite matrix, forming a reliable mechanical anchor.

[0031] A standardized 3D interconnect framework sits atop an adaptive stress buffer layer, supporting and interconnecting all heterogeneous chips. Fabricated using a glass substrate process, the framework has a total thickness of 480 micrometers and consists of four redistribution layers. Each redistribution layer is 15 micrometers thick, made of sputtered copper, and covered with a 5-micrometer thick polyimide passivation layer. Vertical interconnection is achieved between layers via 50-micrometer diameter microvias. A 2-micrometer titanium / copper seed layer is deposited on the inner wall of each microvia, followed by electroplating to fill it with high-purity copper, resulting in a porosity of less than 0.1%. The bottom redistribution layer, facing the chip, is etched with a 400-micrometer pitch array of square pads, each 350 micrometers × 350 micrometers in size, for thermo-bonding to the copper pillar bumps (300 micrometers in diameter, 120 micrometers in height) on the bottom of the silicon carbide power chip.

[0032] The upper redistribution layer, facing the driver chip, is etched with a circular pad array with a pitch of 150 micrometers and a pad diameter of 120 micrometers. These pads are used for reflow soldering with the tin-silver microbumps (80 micrometers in diameter and 40 micrometers in height) of the silicon-based driver chip. The two middle redistribution layers are primarily used for signal routing and power distribution, with the wiring width dynamically adjusted between 20 and 100 micrometers according to current requirements. The entire frame is surrounded by cross-shaped mechanical alignment marks with an accuracy of ±1 micrometer. It also integrates a daisy-chain test structure and Kelvin four-wire test pads, facilitating visual alignment and in-line electrical performance verification by automated placement equipment.

[0033] The gradient thermal management structure consists of a bottom microchannel liquid cooling unit and a top pin-fin heatsink. Please refer to the appendix. Figure 5 The microchannel liquid cooling unit is directly integrated onto the lower surface of the ceramic substrate, with a channel depth of 200 micrometers and a width varying between 50 and 300 micrometers. The channel topology is customized based entirely on the chip heat source distribution output by the design simulation platform. The specific process is as follows: First, the bottom surface of the ceramic substrate is divided into several thermal management units, each corresponding to a silicon carbide chip or a group of high-power components. Then, with the goal of maximizing heat removal by the coolant within each unit, and constrained by the maximum allowable voltage drop of the system (typically not exceeding 150 kPa), the channel shape is optimized through computational fluid dynamics simulation. The resulting channel exhibits significant non-uniformity: in the region directly below a single silicon carbide MOSFET, a high-density serpentine layout is adopted, with a bend radius of 150 micrometers and an adjacent channel spacing of 100 micrometers; in diode or low-power regions, a through-type or Y-shaped branch structure is used, with the channel spacing increased to 400 micrometers.

[0034] The coolant is a mixture of deionized water and ethylene glycol (volume ratio 7:3), with the inlet temperature maintained at 25°C and the flow rate controlled at 0.5 L / min. The pin-fin heatsink is made of 6061 aluminum alloy through precision die casting, with a height of 8 mm, a pin diameter of 1.2 mm, and a spacing of 2.5 mm. Its bottom surface is bonded to the upper surface of the molding compound through a 50-micron-thick phase change interface material (melting point 55°C, thermal conductivity 8 W / m·K) to dissipate the heat generated by the driver chip (typically 5 W to 15 W) and assist the main heat dissipation path. This forms a dual-path gradient heat dissipation system: from silicon carbide chip junction region → buffer layer → ceramic substrate → coolant → ambient air, and from driver chip → molding compound → pin-fin heatsink → ambient air.

[0035] Finally, the packaging process monitoring and feedback unit is described in detail. Please refer to the appendix. Figure 4 This unit is integrated into a fully automated packaging production line and deployed at four key process stations: chip mounting, bump forming, molding, and reflow soldering. It enables real-time sensing and closed-loop control of the entire manufacturing process. The unit consists of three parts: a multi-sensor array, a data fusion processor, and a process parameter adaptive controller.

[0036] The multi-sensor array incorporates various high-precision sensing devices. At the chip placement station, a 5-micron resolution laser displacement sensor and a 1000fps high-speed infrared thermal imager are deployed. The former measures the Z-axis height deviation and planar tilt angle of the chip after placement, while the latter monitors the instantaneous temperature field during solder reflow. At the bump formation station, a depth-of-field composite optics detector and a micro-tension testing probe are configured. The former reconstructs the three-dimensional morphology of the bumps and calculates the consistency of height and diameter, while the latter randomly selects samples for tension testing to ensure the bump shear strength is not less than 40 MPa. At the molding station, an embedded pressure-temperature composite sensor array is installed to monitor the pressure (range 0 to 10 MPa) and temperature (range 160°C to 180°C) distribution at the flow front of the molding compound within the mold cavity in real time. At the reflow soldering station, an ultrasonic scanning microscope performs 100% non-destructive testing on the soldered modules to identify defects such as voids, cracks, or interface delamination.

[0037] The data fusion processor is an embedded multi-core ARM architecture computer running a real-time operating system. Its processing logic is divided by process station: For placement station data, the infrared image is first corrected for non-uniformity, and the area and centroid of the solder melting zone are extracted; simultaneously, laser displacement data is fused to calculate the height difference between the four corners of the chip; if it exceeds 3 micrometers, it is considered an out-of-tolerance angle deviation. For bump station data, each bump contour is identified using an image segmentation algorithm, and an ellipse model is fitted to obtain the major axis, minor axis, and eccentricity; if the diameter variation coefficient is greater than 5%, an early warning is triggered. For molding station data, a spatiotemporal trajectory model of the flow front is established; if the pressure gradient abruptly exceeds a threshold, it is considered uneven filling. All feature parameters are packaged into a standardized JSON format and uploaded in real-time to the process parameter adaptive controller via industrial Ethernet.

[0038] The adaptive process parameter controller incorporates a mapping model built from a deep neural network. The training data for this model comes from the virtual process simulation module of the design simulation platform. This module perturbs key process parameters (such as mounting pressure ±10%, solder paste volume ±15%, reflow peak temperature ±5℃, and molding compound preheating time ±20%) using the Monte Carlo method, generating 50,000 sets of virtual process samples. Each set of samples undergoes complete multiphysics simulation to obtain corresponding intermediate features (such as bump height and chip tilt angle) and final reliability indicators (such as thermal cycle life and shear strength). Subsequently, a three-layer fully connected neural network (128 nodes in the input layer, 256 nodes in the hidden layer, and 64 nodes in the output layer) is used for end-to-end training, with the loss function employing a weighted combination of mean squared error and classification cross-entropy. After training, the model can achieve rapid inference from real-time feature parameters to the required compensation amount. For example, when a silicon carbide chip is detected to have an X-axis tilt angle of 0.15 degrees after mounting (exceeding the 0.1-degree tolerance), the controller immediately queries the model and outputs a compensation command: increase the Z-axis travel of the mounting head at the same position in the next module by 2 micrometers and apply a pitch angle correction of -0.05 degrees. This command is sent to the mounting equipment servo system via the OPC UA protocol and is executed within 200 milliseconds, ensuring process stability.

[0039] In summary, this embodiment systematically solves the core challenges of silicon carbide multi-chip integrated modules in terms of thermomechanical reliability, process integration complexity, and manufacturing consistency by designing a multi-physics collaborative optimization simulation platform, implementing active stress management and standardized interconnection in stress buffering and interconnection integration units, and establishing real-time closed-loop control in packaging process monitoring and feedback units. The entire system achieves a high-fidelity reproduction from virtual design to physical manufacturing, providing a scalable and replicable technical paradigm for the industrialization of high-power-density power electronic modules.

[0040] Example 2: Building upon Example 1, this example provides an in-depth exploration of alternative implementation schemes for the material system and manufacturing process of the standardized three-dimensional interconnect framework. This scheme is suitable for applications with more stringent requirements for high-frequency performance and signal integrity, such as on-board chargers for electric vehicles or RF front-end modules for 5G base stations.

[0041] In this embodiment, the standardized three-dimensional interconnect framework no longer uses a glass substrate, but instead selects a high-resistivity silicon interposer as the substrate material. The silicon interposer has a resistivity greater than 3000 Ω·cm, a thickness of 400 micrometers, and a crystal orientation of [missing information]. <100> The manufacturing process is as follows: First, the silicon wafer undergoes double-sided thermal oxidation to grow a 2-micron thick silicon dioxide insulating layer; then, a 300-micron deep through-hole array is formed on the front side through deep reactive ion etching, with a through-hole diameter of 40 microns and a sidewall roughness RMS of less than 50 nanometers; next, a 500-nanometer tantalum nitride barrier layer and a 2-micron copper seed layer are sequentially deposited on the inner wall of the through-holes, and then the void-free copper pillars are filled by pulse reverse electroplating; then, a 5-micron copper layer is sputtered on the front and back sides respectively, and a two-layer redistribution structure is formed through a double damask process, with a line width / spacing of 10 microns / 10 microns; finally, a 10-micron thick benzocyclobutene polymer is covered on the top layer as a passivation layer, and the pads are exposed by opening windows.

[0042] The bottom pad array of this silicon interposer frame still has a pitch of 400 micrometers, but the pad surface is chemically plated with gold to a thickness of 0.5 micrometers to improve the reliability of thermo-bonding with the copper pillar bumps of the silicon carbide chip. The upper pad array has a pitch of 120 micrometers, compatible with more advanced 2.5D packaged driver chips. Due to the dielectric constant of silicon material (… =11.9) is much lower than glass ( (≈4.5) To suppress high-frequency signal crosstalk, this embodiment embeds a grounding shield wall between adjacent signal lines. The shield wall is formed by deep silicon etching, penetrating the entire redistribution layer, and is filled with conductive silver paste. It is connected to the underlying ground plane, effectively reducing crosstalk noise by more than 15dB.

[0043] In terms of interconnect formation technology, this embodiment employs hybrid bonding technology instead of traditional hot pressing or reflow soldering. Specifically, the silicon carbide chip and the bottom layer of the silicon interposer are directly bonded via copper-copper bonding, requiring no solder or bumps at the bonding interface. This process requires the surface roughness Ra of the copper on both sides to be less than 1 nanometer, and atomic-level diffusion bonding is achieved at 400°C and 30 MPa after plasma activation. The driver chip is connected to the upper-layer pads via microbumps, but the bump material is changed to a copper-tin intermetallic compound, with its reflow temperature controlled at 280°C to avoid thermal shock to the bonded silicon carbide chip. The hybrid bonding process reduces the interconnect resistance to below 0.1 milliohms and the parasitic inductance to below 10 picohenries, significantly outperforming traditional solutions.

[0044] Furthermore, this embodiment features a high-frequency adaptive modification to the micro-spring array of the adaptive stress buffer layer. The micro-spring material has been replaced with a high-conductivity copper-beryllium alloy, increasing its conductivity to 30% IACS while maintaining an elastic modulus above 120 GPa. A 200-nanometer-thick silver layer is applied to the surface of the micro-springs to reduce AC resistance caused by the high-frequency skin effect. In terms of layout, the micro-springs are not only arranged at the chip edges but also have micro-spring islands added in high-current-density regions inside the chip, forming localized stress relief points to prevent micro-vibration fatigue caused by electromagnetic forces.

[0045] The gradient thermal management structure has also been adjusted accordingly. Since the thermal conductivity of the silicon interposer (150 W / m·K) is higher than that of glass (1.2 W / m·K), the channel depth of the microchannel liquid cooling unit has been reduced to 150 micrometers to shorten the heat conduction path. Simultaneously, a microscale thermoelectric cooler array is integrated inside the silicon interposer. Each thermoelectric unit measures 200 micrometers × 200 micrometers and is fabricated from Bi2Te3-based materials using a thin-film deposition process. When a local hotspot temperature exceeds 125°C, the encapsulation process monitoring and feedback unit activates the corresponding thermoelectric cooler, applying a reverse current to achieve active cooling, which can reduce the local temperature by 8°C to 12°C.

[0046] In terms of packaging process monitoring, this embodiment adds a high-frequency S-parameter online testing module. Before molding, a 1GHz to 10GHz sweep frequency signal is applied to the test pads on the silicon interposer using a probe station to measure insertion loss and return loss in real time. The data fusion processor compares the measured S-parameters with the predicted values ​​from the design simulation platform. If the deviation exceeds ±0.5dB, it is determined to be an interconnect quality anomaly, and the process parameter adaptive controller is triggered to fine-tune the plasma activation power or bonding pressure of subsequent batches.

[0047] This embodiment combines technologies such as silicon adapter boards, hybrid bonding, high-frequency optimized microsprings, and integrated thermoelectric cooling. While maintaining the core architectural advantages of Embodiment 1, it significantly improves the high-frequency performance and local thermal management capabilities of the module, expanding the applicability of this invention in the fields of high-end communications and new energy vehicles.

Claims

1. A packaging system for a multi-chip integrated module based on silicon carbide devices, characterized in that, include: Design a simulation platform to perform co-simulation and optimization of the electrical, thermal, and mechanical multi-physics behavior of the module before physical packaging; The stress buffer and interconnection integration unit is used to physically realize the optimized structure output by the design simulation platform. Its core lies in the introduction of an active stress management mechanism and a standardized interconnection interface. The packaging process monitoring and feedback unit is used to collect key process parameters and intermediate product quality data in real time during the packaging manufacturing process, and to establish a data loop with the design simulation platform.

2. The packaging system for a multi-chip integrated module based on silicon carbide devices according to claim 1, characterized in that, The design simulation platform includes a materials database, a multiphysics coupling simulation engine, and a structural optimization module. The material database pre-stores physical parameters of silicon carbide chips, silicon-based driver chips, ceramic substrates, solders, metallization layers, molding compounds, and substrate materials. These physical parameters include the coefficient of thermal expansion, Young's modulus, Poisson's ratio, thermal conductivity, specific heat capacity, and resistivity. The multiphysics coupling simulation engine is based on the finite element method and simultaneously solves the electro-thermal-mechanical coupling equations constructed from the parameters provided by the material database to predict the temperature distribution, current density distribution, and the resulting thermal stress and deformation field inside the module under preset power cycling conditions and temperature shock conditions. The structural optimization module receives the prediction results output by the multiphysics coupling simulation engine and iteratively optimizes the interconnect topology, chip layout, heat dissipation path and key structural dimensions of the module according to the preset optimization objective function and constraints.

3. The packaging system for a multi-chip integrated module based on silicon carbide devices according to claim 2, characterized in that, The stress buffer and interconnection integration unit includes an adaptive stress buffer layer, a standardized three-dimensional interconnection framework, and a gradient thermal management structure. The adaptive stress buffer layer is disposed between the silicon carbide power chip and the ceramic substrate. The buffer layer is composed of a metal matrix composite material and an embedded micro-spring array. The thermal expansion coefficient of the metal matrix composite material is between that of the silicon carbide chip and the ceramic substrate. The embedded micro-spring array is embedded in the composite material in a specific spatial arrangement. The stiffness coefficient of the micro-spring is configured differently according to the power level and position of the chip above it. The standardized three-dimensional interconnect framework adopts a multi-layer redistribution layer structure, with vertical interconnection between layers achieved through a microvia array. Each redistribution layer is etched with a standardized pad array and routing channels. The power chip is connected to the standardized pads at the bottom of the framework through copper pillar bumps, and the driver chip is connected to the corresponding pads on the upper layer of the framework through microbumps. The gradient thermal management structure consists of a microchannel liquid cooling unit integrated on the bottom of the ceramic substrate and a pin-fin heat sink on the upper surface of the package. The flow channel topology of the microchannel liquid cooling unit is customized according to the chip heat source distribution output by the design simulation platform.

4. The packaging system for a multi-chip integrated module based on silicon carbide devices according to claim 3, characterized in that, The packaging process monitoring and feedback unit includes a multi-sensor array, a data fusion processor, and a process parameter adaptive controller. The multi-sensor array is deployed at several key process stations, including chip mounting, interconnect formation, molding, and reflow soldering. The sensor types include infrared thermal imagers, laser displacement sensors, online optical inspection instruments, and ultrasonic scanning microscopes. The data fusion processor receives raw data from the multi-sensor array in real time and extracts real-time feature parameters from each process station. The adaptive process parameter controller has a built-in mapping model between key process parameters and final product quality indicators. This mapping model is generated by the design simulation platform through virtual process simulation data. The controller compares the real-time feature parameters extracted by the data fusion processor with the standard values ​​in the mapping model. When the feature parameters deviate from the standard values ​​by more than the preset tolerance range, the controller immediately calculates and outputs compensation adjustment instructions to the actuators of the corresponding process stations.

5. The packaging system for a multi-chip integrated module based on silicon carbide devices according to claim 4, characterized in that, The configuration method of the embedded micro-spring array in the adaptive stress buffer layer is as follows: Based on the thermal stress cloud diagram analysis of a single silicon carbide chip at the maximum operating junction temperature using the design simulation platform, the four corner points on the chip edge were identified as stress concentration areas. Microsprings with a first stiffness coefficient are configured at the locations of the buffer layers corresponding to these four stress concentration zones. The first stiffness coefficient is set to be able to absorb 70% to 80% of the predicted peak shear stress. Microsprings with a second stiffness coefficient are configured in the non-corner areas of the chip edge, the second stiffness coefficient being smaller than the first stiffness coefficient; The chip's central region is configured with a microspring having a third stiffness coefficient, or only a metal-based composite material is retained, wherein the third stiffness coefficient is a minimum value or zero.

6. The packaging system for a multi-chip integrated module based on silicon carbide devices according to claim 5, characterized in that, The multilayer rewiring layer of the standardized three-dimensional interconnect framework is fabricated using silicon interposer or glass substrate processes. The bottom redistribution layer pad array of the framework is designed with a pitch of 400 micrometers to be compatible with the copper pillar bump spacing of silicon carbide chips. The upper redistribution layer pad array of the framework is designed with a pitch of 150 micrometers to be compatible with the microbump pitch of silicon-based driver chips. The diameter of the interlayer micro-vias is designed to be 50 micrometers, and the pores are filled with electroplated copper. The total thickness of the frame is controlled within 500 micrometers, and standardized mechanical alignment marks and electrical performance test pads are designed around it.

7. The packaging system for a multi-chip integrated module based on silicon carbide devices according to claim 6, characterized in that, The flow channel topology optimization process of the microchannel liquid cooling unit in the gradient thermal management structure is as follows: The design simulation platform first divides the bottom area of ​​the ceramic substrate into multiple thermal management units based on the layout and power consumption of the silicon carbide chip. With the goal of maximizing the heat carried away by the coolant in each thermal management unit and with the constraint that the flow channel pressure drop does not exceed the system's allowable value, computational fluid dynamics simulation is used to iteratively optimize the flow channel width, depth, and tortuous shape of each unit. The resulting flow channel topology exhibits a non-uniform distribution. In the region directly beneath the chip with high heat flux density, the flow channels present a denser serpentine or pin-rib array structure; in the region with lower heat flux density, the flow channels are simplified into straight-through or less branched shapes.

8. The packaging system for a multi-chip integrated module based on silicon carbide devices according to claim 7, characterized in that, The mapping model used by the adaptive controller for process parameters is constructed as follows: The virtual process simulation module within the design simulation platform generates process samples and their corresponding virtual intermediate product characteristics in a virtual environment by changing key process parameters. The electrothermal and reliability performance of the final package of each virtual sample is predicted using a multiphysics coupling simulation engine. Machine learning algorithms are used to train process parameters, intermediate features, and final performance index data to establish a nonlinear mapping model from real-time process features to final quality prediction and then to the required process parameter compensation.

9. A packaging system for a multi-chip integrated module based on silicon carbide devices according to claim 8, characterized in that, The objective function of the structural optimization module aims to minimize the maximum thermal stress and maximum junction temperature, and the constraints ensure that the electrical performance parameters and mechanical strength are not lower than the design threshold.

10. The packaging system for a multi-chip integrated module based on silicon carbide devices according to claim 9, characterized in that, The data fusion processor's processing steps for the chip mounting station include extracting solder or adhesive layer spread images and measuring the vertical height and planar angle offset of the mounted chip. The processing steps for interconnect forming stations include measuring the consistency between the bump height and diameter, or the arc height and tensile strength distribution of the bond wire; The processing steps at the molding station include monitoring the temperature and pressure distribution at the flow front of the molding compound.

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