Rectifier and method for rectifier

Abstract

The present disclosure relates generally to a rectifier, a method for a rectifier, and a computer program, and more particularly, to adjusting at least one switching time for a rectifier.

Description

Technical Field

[0001] This disclosure generally relates to a rectifier, a method for using a rectifier, and a computer program, and more specifically, to adjusting at least one switching time for a rectifier. Background Technology

[0002] A rectifier converts alternating current (AC) into direct current (DC). Rectifiers are key components in many electrical systems, such as wireless charging systems. High-efficiency rectifiers are required for a wide range of applications. Summary of the Invention

[0003] According to a first aspect of this disclosure, a rectifier is provided, comprising: a first input, a first switch,

[0004] The rectifier is configured to activate a first switch based on a first switching signal at a first time to provide an output voltage at the output, and the rectifier further includes:

[0005] An offset circuit is configured to generate an offset current signal based on an output voltage.

[0006] In one or more embodiments, the offset current signal is proportional to the output voltage.

[0007] In one or more embodiments, the offset circuit further includes: a reference current generator having a current converter for converting an output voltage into a reference current; at least one first node coupled to the output voltage; and an output node providing an offset current signal based on the reference current.

[0008] In one or more embodiments, the offset circuit further includes a voltage divider coupled between at least one first node and at least one second node coupled to ground, the voltage divider being configured to provide a second voltage proportional to the output voltage, wherein the voltage divider provides the second voltage to the input node of the current converter.

[0009] In one or more embodiments, the offset current signal is further based on a second current.

[0010] In one or more embodiments, the second current is based on: the first input at a first time and the output voltage at a first time.

[0011] In one or more embodiments, the offset circuit further includes a calibration current source configured to continuously provide a second current.

[0012] In one or more embodiments, the rectifier further includes a first switch signal generator that generates a first activation signal based on a first switch signal, wherein the first activation signal activates the first switch at a second time based on a first time.

[0013] In one or more embodiments, a first switching signal is generated based on a first input, an output voltage, and an offset current signal.

[0014] In one or more embodiments, a first switching signal is generated based on a comparison between a first input and an output voltage, wherein the comparison is biased by an offset current signal.

[0015] In one or more embodiments, the rectifier further includes: a calibration circuit for providing a second current, the calibration circuit comprising:

[0016] A comparator coupled to a first input and coupled to an output voltage, the comparator further including a trigger input coupled to a first switching signal.

[0017] The comparator is configured to provide a comparator signal based on a comparison of the output voltage with the first input, as a response to a trigger signal on the trigger input.

[0018] The calibration circuit is configured to provide a second current based on the comparator signal.

[0019] In one or more embodiments, the rectifier further includes:

[0020] Second input,

[0021] The second switch between the second input and the second output,

[0022] The rectifier includes a second switching signal generator configured to generate a third switching signal at a third time.

[0023] The rectifier is configured to activate the second switch based on the third switching signal to provide an output voltage at the output.

[0024] The third time is based on the offset current signal, and preferably further based on the second input and / or preferably further based on the output voltage.

[0025] According to a second aspect of this disclosure, a method for adjusting the switching time of a rectifier is provided, the rectifier having a first switch between a first input and an output, the method comprising:

[0026] The first switch is activated based on the first switching signal at the first moment to provide an output voltage at the output of the rectifier.

[0027] An offset current signal is generated based on the output voltage.

[0028] In one or more embodiments, the method further includes:

[0029] A second current is provided to modify the offset current signal, wherein the second current is preferably determined in the calibration step based on the first input at the first time and the output voltage at the first time;

[0030] In another preferred embodiment, the second current is continuously supplied when no calibration step is performed.

[0031] In one or more embodiments, the method further includes:

[0032] A first activation signal is generated based on a first switching signal, wherein the first switching signal is generated based on the following: a first input, an output voltage, and an offset current signal;

[0033] The first switch is activated at a second time based on a first activation signal.

[0034] According to a third aspect of this disclosure, a non-transitory machine-readable storage medium is provided, comprising instructions that, when executed by a controller for a rectifier, cause the controller to:

[0035] The first switch of the rectifier is activated based on the first switching signal at the first moment to provide an output voltage at the output of the rectifier.

[0036] An offset current signal is generated based on the output voltage.

[0037] In one or more embodiments, the instructions cause the controller to select an offset current signal proportional to the output voltage.

[0038] In one or more embodiments, the instructions cause the controller to select an offset current signal based on a second current.

[0039] In one or more embodiments, the instructions cause the controller to select a second current based on a first input at a first time and an output voltage at a first time.

[0040] In one or more embodiments, the instructions cause the controller to continuously provide a second current.

[0041] The foregoing discussion is not intended to present every exemplary embodiment or implementation within the scope of the present or future claims. Various exemplary embodiments are further illustrated in the accompanying drawings and the following detailed description. A fuller understanding of these exemplary embodiments can be achieved by considering the following detailed description in conjunction with the accompanying drawings. Attached Figure Description

[0042] The invention is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. Elements in the drawings are shown for simplicity and clarity, and are not necessarily drawn to scale.

[0043] Figure 1Example implementation of the rectification process;

[0044] Figure 2 The rectification process according to the example embodiment;

[0045] Figure 3a Example embodiments of rectifiers;

[0046] Figure 3b Example embodiment of the offset circuit;

[0047] Figure 4 Example embodiments of a reference current generator; and

[0048] Figure 5 Example embodiments of methods for rectifiers. Detailed Implementation

[0049] Figure 1 An example embodiment of the rectification process is shown. That is, Figure 1 The rectification process of providing voltage 110 according to time 100 is shown. Figure 1 An idealized state is shown, where due to the rectifier (e.g.) Figure 3a The operation of the rectifier switch converts the first input LA and the second input LB of the AC power into a rectified output voltage VRECT, as will be described in detail below.

[0050] To improve rectifier efficiency, special attention must be paid to the timing control of the rectifier's power switch to ensure that energy is delivered to the rectifier's output at the appropriate time, such as... Figure 1 As shown. Due to the electronic components of the rectifier, such as in... Figure 3a In the switch signal generators of the first switch signal generator 305 and the second switch signal generator 306 shown, there are already some inherent delays. Sometimes, the switch signal generator is also referred to as a control chain. Furthermore, the timing of the switches in the rectifier may be further disturbed, for example, due to parasitic capacitance, particularly due to the parasitic capacitance of the switches. It may be advantageous to at least partially compensate for the timing delays of the switches in the rectifier caused by these effects.

[0051] In rectifier applications, such as those for battery charging and others, the output voltage VRECT can change over time. When the battery is used as a load (e.g.) Figure 3a In the example of load 311 shown, the following situation may occur: if the battery is in a discharged state, the output voltage VRECT may be lower than that of a battery with an intermediate charge. As the battery approaches full charge, the output voltage VRECT may increase further. Therefore, it is desirable to provide a rectifier that adapts to changes in the output voltage VRECT. It is also desirable for the rectifier's efficiency to remain high even when the output voltage VRECT changes.

[0052] Figure 2 The rectification process according to an example embodiment is illustrated. Figure 2 In the example, the voltage 210 at the rectifier output is shown as varying over time 200. Curve 220 illustrates the misalignment timing of the first switch connecting the first input LA to the output voltage VRECT. If the first switch is activated too late, the voltage of LA will not match VRECT. Figure 2 As shown, curve 220 illustrates overshoot behavior, where the voltage across LA rises above the value of VRECT. This overshoot behavior, observed in region 240, introduces losses, thereby reducing the rectifier's efficiency. It is worth noting that in region 240, the rectifier can operate in passive mode, where the diode in the first switch may cause losses when current flows due to its high diode resistance.

[0053] According to an embodiment, the timing of switch VA is optimized as shown in curve 230. Curve 230 illustrates a first input LA with optimized timing. Here, for the first input LA, the situation is similar to... Figure 1 The ideal conditions are shown in the diagram. Here, the first switch is activated at the optimal time so that the first input slightly or not at all exceeds the output voltage VRECT. Therefore, no current flows through the diode in the first switch, avoiding losses in region 240.

[0054] like Figure 2 As shown, improving the timing, particularly improving the crossover between the first input LA and the output voltage VRECT, can be advantageous. Even more specifically, it might be desirable to improve the crossover timing between the first input LA and the output voltage VRECT, where the crossover occurs during the rise of the first input LA, since at this time most of the current flows through the first switch, for example through... Figure 3a The first switch is PS1.

[0055] Therefore, optimizing the timing, such as the timing of this crossover, can have a significant impact on the rectifier's efficiency. However, it may also be advantageous to optimize the timing of other crossovers, such as those used for other switches (e.g., at least one of switches PS2, PS3, and PS4).

[0056] To optimize the switching signal for activating the switch, it is necessary to use a signal that can offset the switching time of the rectifier, for example... Figure 3a The offset signal for the switching time of the first switch, PS1. Using such an offset signal allows for optimization of the switching signal time chain, as referenced above. Figure 2 The discussion.

[0057] The following will explain how this offset signal can be obtained. Specifically (but not limited to), the offset signal can be an offset current signal.

[0058] Because the output voltage VRECT can change over time, some embodiments provide improved offset signals and / or allow for improved rectifier timing, even when the output voltage VRECT changes in a simplified and energy-efficient manner.

[0059] Figure 3a An example embodiment of the rectifier is shown.

[0060] The rectifier 300 may include a first input LA and a first switch PS1. The rectifier 300 may be configured to activate the first switch PS1 at a first time based on a first switching signal (e.g., the signals swap and / or sw_clone) to provide an output voltage VRECT at output 310. The rectifier 300 may additionally include an offset circuit 320 configured to generate an offset current signal ioffset based on the output voltage VRECT.

[0061] The efficiency of a rectifier may be affected by the following factors: the resistive losses of the circuit system, the switching losses of the switches, and / or the timing accuracy of the activation of the rectifier switches (e.g., switches PS1, PS2, PS3 and / or PS4 of rectifier 300).

[0062] Resistance and switching losses can be optimized by selecting appropriate components for the switch, for example, by selecting the appropriate type of metal-oxide-semiconductor (MOS) for the correct size of the switch and / or switch. It is worth noting that switches PS1, PS2, PS3, and / or PS4 can be optimized accordingly. For switches PS1, PS2, PS3, and / or PS4, the choice of MOS type can affect the timing accuracy requirements for the activation of the switch. Specifically, the selection of switches PS1 through PS4 may affect the above references. Figure 2 The desired offset signal is discussed. For example, different switches may have different parasitic capacitances, resulting in different requirements for the offset signal. Furthermore, parasitic capacitance and / or other parameters may behave differently from external parameters such as temperature.

[0063] like Figure 3a As shown, the first input LA can be coupled to an AC power source 301, which includes, for example, an antenna and optionally a filter (not shown). The AC power source 301 can be a power source for transferring energy to a load 311. The load 311 can be a battery or another type of DC device. Figure 3a As shown, rectifier 300 may include additional switches, such as a second switch PS2, a third switch PS3, and / or a fourth switch PS4. (See reference...) Figure 2 As discussed, the first switch and / or additional switch can be activated according to time to provide the output voltage VRECT at output 310.

[0064] Using a current signal as an offset signal (e.g., the current signal ioffset) has the advantage of simplifying the comparison operation used for switch activation decisions. Using a current signal as an offset signal provides greater flexibility in designing electronic circuits and allows for a wide range of offset values. Furthermore, if the rectifier is used for a large range of output voltages (VRECT), the optimal timing for switch activation may change, and therefore a large offset signal may be required. In some examples, such as... Figure 2 As shown, the desired offset can correspond to timing adjustments of a few nanoseconds. In some embodiments, using an offset current signal may be superior to using other methods to transmit the offset signal, such as an offset voltage signal. For example, using an offset current signal allows for a simpler topology of the electronic circuitry compared to using a voltage signal for the offset signal. In some embodiments, achieving the desired offset range may require a less complex circuitry compared to using a voltage signal as the offset signal for the same desired offset range.

[0065] Generating an offset current signal ioffset based on the output voltage VRECT allows for optimization of rectifier timing based on the output voltage. Considering the output voltage VRECT can improve rectifier efficiency. In some embodiments, considering the output voltage VRECT improves rectifier efficiency because the output voltage changes, for example, during the charging of a battery connected to the rectifier as a load, such as when... Figure 3a The load is 311.

[0066] The first switch signal can be as follows: Figure 3a The signals shown are swap and / or sw_clone. The first switch signal can be generated by the first switch signal generator 305.

[0067] The offset current signal ioffset can be proportional to the output voltage VRECT. Making the offset current signal ioffset proportional to the output voltage allows for optimized switch activation, for example, when the optimal timing of switch activation is also proportional to the output voltage VRECT.

[0068] For reference Figure 2 As discussed, in many applications, the output voltage VRECT can change over time. Therefore, providing an offset current signal proportional to the output voltage VRECT allows the rectifier to adapt to changes in the output voltage VRECT in an efficient and / or simple manner, for example, due to different states of charge of the battery as load 311 over time.

[0069] like Figure 3b and Figure 4 As shown, rectifier (e.g.) Figure 3aThe offset circuit 320 of the rectifier 300 may further include: a reference current generator 350, 450, which is used to convert the output voltage VRECT into a reference current iref. For example, Figure 3b and Figure 4 Embodiments of reference current generators 350 and 450 are shown. Reference current generators 350 and 450 may include current converters, such as... Figure 4 The current converter 410 shown is illustrated.

[0070] The offset circuit 320 may additionally include at least one first node 401 coupled to the output voltage VRECT, and / or output nodes 360, 460 providing the offset current signal ioffset. Figure 4 As shown, the offset current signal ioffset provided at output node 460 can be based on the reference current iref. Figure 3b As shown, the offset current signal ioffset provided at output node 360 ​​can be based on the reference current iref.

[0071] The rectifier 300 may include a voltage divider 420, for example Figure 4 The voltage divider 420 shown is part of the reference current generator 450. (As shown...) Figure 4 As shown, voltage divider 420 can be coupled between at least one first node 401 and at least one second node 403 coupled to ground. Figure 4 The image shows three second nodes 403. Figure 4 In this example, all second nodes 403 are coupled to ground. In other embodiments, at least one second node 403 may be connected to a different potential than ground.

[0072] exist Figure 4 In this embodiment, voltage divider 420 is part of reference current generator 450. In other embodiments, the voltage divider may be part of offset circuitry or a different circuit.

[0073] Voltage divider 420 may include a first resistor R1 and a second resistor R2. Voltage divider 420 may be configured to provide a second voltage V2 proportional to the output voltage VRECT. The voltage divider may provide the second voltage V2 to an input node, for example... Figure 4 The input node 404 of the current converter 410 shown.

[0074] Voltage divider 420 can provide a simple component for generating a signal proportional to the output voltage VRECT and can simplify the design of current converter 410. Voltage dividers can contribute to low current consumption and / or improve energy efficiency. In embodiments where accuracy requirements for the second voltage V2 are relaxed, the use of a voltage divider may be advantageous.

[0075] like Figure 4 As shown, additional components may be present in the reference current generator 450, such as a tunable resistor Rtrim that allows for further optimization of the circuit system.

[0076] The offset current signal ioffset can be further based on the second current idac.

[0077] This allows for further modification of the offset current signal to further optimize the rectifier's switching (e.g., as...). Figure 3a The activation timing of the first switch (PS1) is shown. In some embodiments, using a second current can allow for further optimization of portions of the rectifier that exhibit characteristics that may not be proportional to the output voltage VRECT. For example, the second current can be used to calibrate the rectifier for changes such as temperature or component aging. Since changes in these characteristics (e.g., temperature) may not be as slow as changes in the output voltage VRECT, the calibration steps for determining the second current may not need to be performed frequently, thus reducing the amount of energy required to perform the calibration steps. In other words, making the offset current signal ioffset based on a component based on the output voltage VRECT and the second current (in some examples not based on the output voltage VRECT, and in some examples based on a previous value of the output voltage VRECT) can simplify timing optimization and / or reduce the requirement for calibration to determine an accurate value of the second current iac when operating and / or conditions (e.g., the voltage of the output voltage VRECT) change.

[0078] The second current idac can be based on the first input LA at the first time and / or the output voltage VRECT at the first time.

[0079] Making the second current idac based on the measurement results of the first input LA and / or output voltage VRECT at the first time can allow for the calibration of the rectifier.

[0080] The offset circuit 320 may additionally include a calibration current source 340, 440 configured to continuously provide a second current idac.

[0081] This allows for the provision of a post-calibrated offset current signal after calibration (e.g., calibration performed during the initial time period). Therefore, the offset current signal ioffset can dynamically change with the output voltage VRECT, thereby improving rectifier efficiency as the output voltage VRECT changes. Simultaneously, a second current idac can be continuously provided, allowing calibration information to be continuously considered without frequent calibration updates. Therefore, updating the value of the second current idac may be less frequently required if the offset current is not based on the output voltage VRECT.

[0082] The rectifier 300 may include a first switching signal generator 305. The first switching signal generator 305 may generate a first activation signal, for example... Figure 3a The first activation signal shown is swap. In some embodiments, the first activation signal and the first switch signal can be the same. For example, the first activation signal swap and the first switch signal sw_clone can be the same. In other embodiments, the first activation signal can be based on the first switch signal. For example, the first activation signal swap can be based on the first switch signal sw_clone. The first activation signal can activate the first switch based on a first time and a second time. For example, in Figure 3a In this process, the first activation signal swap can activate the first switch PS1 based on a first time and a second time.

[0083] Using this first activation signal can improve rectifier efficiency. For example, using the first activation signal can allow maximizing the startup current in the first switch PS1 and / or minimizing the reverse current occurring in the first switch PS1. If the first activation signal swap is based on the first switch signal sw_clone, then this can allow optimization of the rectifier timing based on the first switch signal, while driving the switch, such as the first switch PS1, with the first activation signal swap. Figure 3a As shown in the example. This can have the following advantages: the parasitic capacitance of the first switch PS1 has a reduced or no effect on the first switch signal sw_clone. This can simplify and / or improve upon, as shown in the reference. Figure 2 The timing optimizations discussed. Although explained with reference to the first switch PS1, the use of activation and switching signals also applies to other switches. For example, for the fourth switch PS4, operation can be based on the fifth switching signal swbn, or for other switches such as PS2 and PS3, operation can be performed using the associated switching signals swbp and swan respectively. Figure 3a As shown.

[0084] The first switching signal and / or the first activation signal can be generated based on the following:

[0085] The first input LA, the output voltage VRECT, and / or the offset current signal ioffset.

[0086] This allows the first switching signal to optimize the timing of the rectifier (e.g., rectifier 300), thereby improving efficiency. The offset current signal can also allow for timing optimization, thus at least partially achieving... Figure 2The behavior shown in curve 230 improves the rectifier's efficiency. Using an offset current signal allows for a simplified dynamic consideration of changes in the output voltage VRECT. In some embodiments, the required calibration steps for determining the second current can be reduced, thereby reducing the amount of energy required for calibration and improving the overall efficiency of rectifier 300.

[0087] A first switching signal, swap, or sw_clone, can be generated based on a comparison between the first input LA and the output voltage VRECT. This comparison can be biased by an offset current signal, ioffset. In other words, the comparison, and therefore the generation of the first switching signal, can depend on the value of the offset current signal ioffset. This allows for optimization of the switching time, as referenced... Figure 2 The discussion.

[0088] In some embodiments, this may allow Figure 3a The first switch signal generator 305 uses the offset current signal ioffset in a simple and effective manner. Offset comparison can be a simple way to optimize the timing of the first switch signal, as shown in the reference... Figure 2 As discussed, in embodiments where the offset current signal is proportional to the output voltage VRECT, the bias comparison can allow for simple and / or efficient optimization as the output voltage VRECT changes. This can reduce the need for calibrating the rectifier 300. For example, in some embodiments, the frequency at which the second current must be determined can be reduced.

[0089] like Figure 3b As shown, rectifier 300 may additionally include calibration circuitry 330 for providing a second current idac. Calibration circuitry 330 may include comparator 370 coupled to a first input LA and coupled to an output voltage VRECT, the comparator further including a trigger input 341 coupled to a first switching signal.

[0090] Comparator 370 can be configured to provide a comparator signal 380 based on a comparison of the output voltage VRECT with the first input LA, as a response to a trigger signal on trigger input 341. Calibration circuit 330 can be configured to provide a second current idac based on the comparator signal 380.

[0091] The comparator (e.g., comparator 370) can be a sample-and-hold comparator.

[0092] In some embodiments, the second current can be provided continuously. In some embodiments, the second current can be provided by controlling calibration current sources 340, 440.

[0093] Using the trigger input 341 of comparator 370 allows the values ​​of the first input LA and the output voltage VRECT to be determined at a first moment. The trigger input 341 can activate the sample-and-hold function of the comparator (e.g., comparator 370). Therefore, it is possible to provide a calibration current idac to account for system effects of the rectifier that affect the optimal timing of switch activation, such as the activation of the first switch PS1.

[0094] like Figure 3b As shown, the offset current ioffset can be the sum of the second current and the reference current iref. Therefore, the reference current iref can optimize timing when the output voltage VRECT changes, while the second current iref can provide an offset that is determined at the first time and can be independent of the dynamic changes in the output voltage VRECT.

[0095] like Figure 3a As shown, rectifier 300 may additionally include: a second input LB and / or a second switch PS2 between the second input LB and output 310.

[0096] The rectifier 300 may include a second switch signal generator 306 that can be configured to generate a third switch signal swbp at a third time. The rectifier 300 may also be configured to activate a second switch PS2 based on the third switch signal swbp to provide an output voltage VRECT at output 310. The third time may be based on at least one of the following: an offset current signal ioffset, a second input LB, and the output voltage VRECT.

[0097] This also allows for optimization of the timing of the second switch PS2. Using this second switch signal generator 306 reduces the complexity of the rectifier because the offset circuit 320 can be used with both the first switch signal generator 305 and the second switch signal generator 306, such as... Figure 3a As shown in the diagram. This can also improve the energy efficiency of rectifier 300, since any optimization of the offset current ioffset can be used to optimize the switching of the first switch PS1 and / or the second switch PS2.

[0098] In a similar manner, additional switching signals can be generated, such as the fourth switching signal swan for the third switch PS3 and the fifth switching signal swbn for the fourth switch PS4, as follows. Figure 3a As shown. Also as... Figure 3a As shown, the fourth switch signal swan can be generated by the second switch signal generator 306 and / or the fifth switch signal swbn can be generated by the first switch signal generator 305. By operating the switch using the first switch signal generator 305 and the second switch signal generator 306, the following can be achieved: Figure 1 The switch mode shown.

[0099] Figure 5 An example embodiment of a method for a rectifier is shown. For example... Figure 5 As shown, a method 500 for adjusting the switching time of a rectifier 300 may include the following steps, wherein the rectifier 300 has a first switch PS1 between a first input LA and an output 310:

[0100] In step 510, the first switch is activated based on the first switch signals swap and sw_clone at a first time to provide the output voltage VRECT at the output 310 of the rectifier 300.

[0101] Method 500 may further include: in step 520, generating an offset current signal ioffset based on the output voltage VRECT.

[0102] Generating a current signal (e.g., an offset current signal ioffset) for controlling the rectifier can improve the robustness of the rectifier when operating conditions change (e.g., the temperature of rectifier 300 and / or at least one of switches PS1 to PS4). Making the signal (e.g., the offset current signal ioffset) based on the output voltage VRECT can reduce the need for rectifier calibration, as described above.

[0103] Additionally, method 500 may further include providing a second current idac to modify the offset current signal ioffset. The second current idac may be determined during a calibration step. This determination may be based on a first input LA at a first time and / or an output voltage VRECT at a first time. When no calibration step is performed, the second current idac may be provided continuously.

[0104] As mentioned above, this can further improve the energy efficiency of the rectifier.

[0105] Method 500 may further include: generating a first activation signal swap based on a first switching signal sw_clone. The first switching signal swap and sw_clone may be generated based on at least one of the following: a first input LA, an output voltage VRECT, and an offset current signal ioffset.

[0106] The method may further include: activating a first switch PS1 at a second time based on a first time by means of a first activation signal swap.

[0107] As mentioned above, this can facilitate, as referenced Figure 1 and Figure 2 The timing optimizations discussed.

[0108] According to a third aspect of this disclosure, a non-transitory machine-readable storage medium is provided, comprising instructions that, when executed by a controller for a rectifier, cause the controller to:

[0109] The first switch of the rectifier is activated based on the first switching signal at the first moment to provide an output voltage at the output of the rectifier, and / or

[0110] An offset current signal is generated based on the output voltage.

[0111] In one or more embodiments, the instructions cause the controller to select an offset current signal proportional to the output voltage.

[0112] In one or more embodiments, the instructions cause the controller to select an offset current signal based on a second current.

[0113] In one or more embodiments, the instructions cause the controller to select a second current based on a first input at a first time and an output voltage at a first time.

[0114] In one or more embodiments, the instructions cause the controller to continuously provide a second current.

[0115] As discussed above, these instructions can facilitate the references mentioned above. Figure 1 Figure 2 The optimization of the rectifier is described.

[0116] In this specification, exemplary embodiments have been presented based on a selected set of details. However, those skilled in the art will understand that many other exemplary embodiments, including different selected sets of details, can be practiced. It is intended that the appended claims cover all possible exemplary embodiments. For example, the VRECT example based on the output voltage may additionally or alternatively be based on other voltages, such as… Figure 3a The VSSPWR shown.

Claims

1. A rectifier (300), characterized in that, include: First input (LA) First switch (PS1) The rectifier (300) is configured to activate the first switch (PS1) based on the first switch signal (swap, sw_clone) at a first time to provide an output voltage (VRECT) at the output (310). The rectifier (300) further includes: An offset circuit (320) is configured to generate an offset current signal (ioffset) based on the output voltage (VRECT).

2. The rectifier (300) according to claim 1, characterized in that, The offset current signal (ioffset) is proportional to the output voltage (VRECT).

3. The rectifier (300) according to any one of the preceding claims, characterized in that, The offset circuit (320) further includes: The reference current generator (350, 450) has a current converter (410) for converting the output voltage (VRECT) into a reference current (iref). At least one first node (401) is coupled to the output voltage (VRECT). Output nodes (360, 460) provide the offset current signal (ioffset) based on the reference current (iref).

4. The rectifier (300) according to claim 3, characterized in that, The offset circuit (320) further includes a voltage divider (420) coupled between the at least one first node (401) and at least one second node (403) coupled to ground. The voltage divider (420) is configured to provide a second voltage (V2) proportional to the output voltage (VRECT), wherein the voltage divider provides the second voltage (V2) to the input node (404) of the current converter (410).

5. The rectifier (300) according to any one of the preceding claims, characterized in that, The offset current signal (ioffset) is further based on a second current (idac).

6. The rectifier (300) according to claim 5, characterized in that, The second current (idac) is based on: The first input (LA) at the first time point, and The output voltage (VRECT) at the first time point.

7. The rectifier (300) according to claim 5 or claim 6, characterized in that, The offset circuit (320) further includes: A calibration current source (340, 440) is configured to continuously provide the second current (idac).

8. The rectifier (300) according to any one of claims 5 to 7, characterized in that, In addition, including: A calibration circuit (330) for providing the second current (idac), the calibration circuit (330) comprising: A comparator (370) coupled to the first input (LA) and the output voltage (VRECT) further includes a trigger input (341) coupled to the first switching signal (swap, sw_clone). The comparator (370) is configured to provide a comparator signal (380) based on a comparison of the output voltage (VRECT) with the first input (LA), as a response to a trigger signal on the trigger input (341). The calibration circuit (330) is configured to provide the second current (idac) based on the comparator signal (380).

9. The rectifier (300) according to any one of the preceding claims, characterized in that, The rectifier (300) further includes: Second input (LB) The second switch (PS2) is located between the second input (LB) and the output (310). The rectifier (300) includes a second switching signal generator (306) configured to generate a third switching signal (swbp) at a third time. The rectifier (300) is configured to activate the second switch (PS2) based on the third switching signal to provide the output voltage (VRECT) at the output (310). The third time is based on the offset current signal (ioffset), and preferably further based on the second input (LB) and / or preferably further based on the output voltage (VRECT).

10. A method (500) for adjusting the switching time of a rectifier (300), the rectifier (300) having a first switch (PS1) between a first input (LA) and an output (310), characterized in that, The method includes: The first switch is activated (510) based on the first switch signal (swap, sw_clone) at the first moment to provide an output voltage (VRECT) at the output (310) of the rectifier (300). An offset current signal (ioffset) is generated based on the output voltage (VRECT).

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