Semiconductor device

Abstract

A semiconductor device includes a substrate including an NMOS region and a PMOS region, a first gate stack and a first source / drain region adjacent to the first gate stack, and a transistor in the PMOS region, the transistor including a second gate stack and a second source / drain region adjacent to the second gate stack, the first gate stack comprises a first high-dielectric-constant insulating film, an insertion layer, a first metal layer and a first protection layer which are stacked in sequence, the second gate stack comprises a second high-dielectric-constant insulating film, a second metal layer and a second protection layer which are stacked in sequence, and the oxygen concentration of the first protection layer is higher than that of the first metal layer; and the oxygen concentration of the second protective layer is higher than that of the second metal layer.

Description

semiconductor devices

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0151412, filed on October 30, 2024, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device. Background Technology

[0004] Semiconductor devices such as dynamic random access memory (DRAM) may include a cell array region and a peripheral region (i.e., a core peripheral region). Specifically, the peripheral region or core peripheral region may include a region in which PMOS transistors are formed and a region in which NMOS transistors are formed. Gate structures with different structures are disposed in the regions in which PMOS transistors are formed and the regions in which NMOS transistors are formed. Summary of the Invention

[0005] The inventive concept disclosed herein provides a semiconductor device that can improve device performance and reliability.

[0006] The inventive concept of this disclosure is not limited to the problems mentioned above, and those skilled in the art will clearly understand from the following description of this disclosure other problems not mentioned herein that are to be solved by the technical ideas of this disclosure.

[0007] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a substrate including an NMOS region and a PMOS region, a first gate stack and a first source / drain region, wherein the first source / drain region is adjacent to at least one side of the first gate stack, and a transistor in the PMOS region including a second gate stack and a second source / drain region, wherein the second source / drain region is adjacent to at least one side of the second gate stack, wherein the first gate stack includes a first high-dielectric-constant insulating film, an insertion layer, a first metal layer and a first protective layer sequentially stacked in a first direction, and the second gate stack includes a second high-dielectric-constant insulating film, a second metal layer and a second protective layer sequentially stacked in the first direction, wherein the oxygen concentration of the first protective layer is higher than the oxygen concentration of the first metal layer, and the oxygen concentration of the second protective layer is higher than the oxygen concentration of the second metal layer.

[0008] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a substrate including a cell array region and a peripheral region, wherein the cell array region includes a buried gate structure, and the peripheral region includes an NMOS region and a PMOS region having different conductivity types; a first transistor in the NMOS region including a first gate stack and a first source / drain region, wherein the first source / drain region is adjacent to at least one side of the first gate stack; and a second transistor in the PMOS region including a second gate stack and a second source / drain region, wherein the second source / drain region is adjacent to at least one side of the second gate stack; wherein the first gate stack includes a first high-dielectric-constant insulating film, an insertion layer, a first metal layer, and a first protective layer sequentially stacked in a first direction; the second gate stack includes a second high-dielectric-constant insulating film, a second metal layer, and a second protective layer sequentially stacked in the first direction; the oxygen concentration of the first protective layer is higher than the oxygen concentration of the first metal layer, and the oxygen concentration of the second protective layer is higher than the oxygen concentration of the second metal layer.

[0009] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a substrate including an NMOS region and a PMOS region; a first transistor in the NMOS region including a first gate stack and a first source / drain region, wherein the first source / drain region is adjacent to at least one side of the first gate stack; and a second transistor in the PMOS region including a second gate stack and a second source / drain region, wherein the second source / drain region is adjacent to at least one side of the second gate stack. The first gate stack includes a first high-dielectric-constant insulating film, an insertion layer, a first metal layer, and a first protective layer sequentially stacked in a first direction. The second gate stack includes a second high-dielectric-constant insulating film, a second metal layer, and a second protective layer sequentially stacked in the first direction. The oxygen concentration of the first protective layer is higher than that of the first metal layer, the oxygen concentration of the second protective layer is higher than that of the second metal layer, and the lanthanum (La) concentration in the first high-dielectric-constant insulating film is higher than that in the second high-dielectric-constant insulating film.

[0010] It should be noted that the embodiments of this disclosure are not limited to those described above, and other embodiments of this disclosure will be clearly understood by those skilled in the art from the following description. Attached Figure Description

[0011] The above and other aspects of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0012] Figure 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0013] Figure 2 is a cross-sectional view illustrating a semiconductor device according to other embodiments of the present disclosure.

[0014] Figure 3 is a plan view illustrating a substrate for describing a semiconductor device according to some embodiments of the present disclosure.

[0015] Figure 4 is a schematic enlarged layout diagram of the first region R1 in Figure 3.

[0016] Figure 5 is a cross-sectional view taken along lines A-A', B-B', and C-C' in Figure 3, and

[0017] Figures 6, 7, 8, 9, 10, 11, 12, 13, and 14 are diagrams illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0018] In this disclosure, it should be understood that the terms “first,” “second,” “third,” etc., as used herein can describe various elements or components regardless of their order and / or priority, and are used only to distinguish one element from another, without limiting the exemplary embodiments. These elements or components should not be limited by these terms. For example, the first element and the second element can be different entities, but they can also be elements of the same type; for example, the first carbon portion and the second carbon portion are both elements of the same type, namely carbon. Therefore, without departing from the scope of this disclosure, the first element or component discussed below can be referred to as the second element or component, and similarly, the third direction DR3 can be referred to as the first direction.

[0019] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit this disclosure. As used herein, the singular terms “a” and “an” are intended to include plural terms as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprise,” “comprising,” “include,” and “including” specify the presence of the stated features, integers, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, operations, elements, components, and / or portions thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. The term “at least one of…” may modify the entire list of elements and / or may not modify individual elements in the list when it precedes the list of elements. When “C through D” is mentioned, unless otherwise stated, it means that C through D are included. As used herein, the term “on…” may refer to an element, component, or layer directly or indirectly on a different element, component, or layer, and covers physical and / or functional dependencies. It should be noted that aspects described with respect to one embodiment may be incorporated into different embodiments, although not specifically described therein. That is, features of all and / or any embodiment may be combined in any manner and / or combination.

[0020] Figure 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0021] Referring to FIG1, a semiconductor device according to some embodiments of the present disclosure may include a substrate 100, a first gate stack G1, a first gate spacer 181, a second gate stack G2, and a second gate spacer 182.

[0022] Substrate 100 may include an NMOS region RN and a PMOS region RP. The NMOS region RN and the PMOS region RP may be regions that are separate from each other or connected to each other. As used herein, the term "connection" means an electrical and / or physical connection between elements or components, and does not exclude the presence of additional elements or components therebetween.

[0023] Transistors with different conductivity types can be disposed in the NMOS region RN and the PMOS region RP, respectively. For example, an NMOS transistor can be formed in the NMOS region RN, and a PMOS transistor can be formed in the PMOS region RP.

[0024] The substrate 100 may be, for example, bulk silicon or silicon-on-insulator (SOI). The substrate 100 may be a silicon substrate or may include other materials, such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, and / or gallium antimonide. The substrate 100 may be an epitaxial layer formed on a base substrate.

[0025] The substrate 100 may include device isolation films 110. Multiple device isolation films 110 may be disposed in the substrate 100. The device isolation films 110 may be formed in the substrate 100 to define an NMOS region RN and a PMOS region RP, respectively. Furthermore, at least one transistor may be disposed between the device isolation films 110. At least one transistor may be adjacent to each other within (i.e., between) the device isolation films 110.

[0026] Device isolation film 110 may include silicon oxide, silicon nitride, and / or combinations thereof, but the scope of this disclosure is not limited thereto. Device isolation film 110 may be a single layer made of (i.e. constituted, formed, or included therefrom) one type of insulating material, or may be a multilayer made of (i.e. constituted, formed, or included therefrom) a combination of various types of insulating materials.

[0027] The first transistor may be disposed in the NMOS region RN. The first transistor may include a first gate stack G1, a first gate spacer 181, and a first source / drain region 105. The first transistor may be an n-type planar transistor.

[0028] The first gate spacer 181 may be disposed on at least one side of the first gate stack G1. For example, the first gate spacer 181 may be disposed on both sides of the first gate stack G1.

[0029] The first gate spacer 181 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), and / or combinations thereof.

[0030] The first gate stack G1 may include a first interface insulating film 121, a first high dielectric constant insulating film 131, an insertion layer 210, a first metal layer 141, a first protective layer 151, a first conductive film structure 161, and a first hard mask pattern 171, which are stacked sequentially.

[0031] The first interface insulating film 121 can be directly disposed on the substrate. The first interface insulating film 121 may include, for example, a silicon oxide film and / or a silicon oxynitride film. A first high dielectric constant insulating film 131 may be disposed on the first interface insulating film 121. The first high dielectric constant insulating film 131 may include, for example, a high-k dielectric material having a dielectric constant higher than that of silicon oxide. The first high dielectric constant insulating film 131 may include, for example, hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), lead scandium tantalum oxide (PbScTaO), and / or combinations thereof, but the scope of this disclosure is not limited thereto. For example, the first high dielectric constant insulating film 131 may not include lanthanum.

[0032] The insertion layer 210 may be disposed on the first high dielectric constant insulating film 131. The insertion layer 210 may include lanthanum. For example, the insertion layer 210 may include at least one of lanthanum and / or lanthanum oxide.

[0033] The first metal layer 141 may be disposed on the insertion layer 210. The first metal layer 141 may include, for example, at least one of titanium (Ti), aluminum (Al), tungsten (W), molybdenum (Mo) and / or lanthanum (La).

[0034] The first protective layer 151 can be disposed on the first metal layer 141. The first protective layer 151 can be disposed directly on the first metal layer 141, for example, without inserting another layer between the first protective layer 151 and the first metal layer 141.

[0035] The first protective layer 151 may include an oxide or oxynitride of a metal included in the first metal layer 141. For example, when the first metal layer 141 includes titanium aluminum nitride (TiAlN), the first protective layer 151 may include titanium oxide (TiO).

[0036] The concentration of oxygen (O) contained in the first protective layer 151 is higher than the concentration of oxygen contained in the first metal layer 141. For reference, comparing the oxygen concentration contained in the first protective layer 151 also applies even when the first metal layer 141 does not contain oxygen. That is, even when the first metal layer 141 does not contain oxygen, the concentration of oxygen contained in the first protective layer 151 can be higher than the concentration of oxygen contained in the first metal layer 141. In other words, even when the first metal layer 141 does not contain oxygen (i.e., the oxygen concentration in the first metal layer 141 is practically undetectable or negligible), the concentration of oxygen in the first protective layer 151 is still higher than the concentration of oxygen in the first metal layer 141.

[0037] When the first protective layer 151 has a higher oxygen concentration than the first metal layer 141, oxygen can be prevented from flowing into the first metal layer 141 from the top of the first protective layer 151. Therefore, the performance and reliability of the semiconductor device can be improved.

[0038] The first conductive film structure 161 may be disposed on the upper surface of the first protective layer 151. The first conductive film structure 161 may include a metallic material. The first conductive film structure 161 may include a first lower conductive film 161a, a first inserted conductive film 161b, and a first upper conductive film 161c. The first lower conductive film 161a, the first inserted conductive film 161b, and the first upper conductive film 161c may be sequentially stacked on the upper surface of the first protective layer 151. In other words, the first inserted conductive film 161b may be disposed between the first lower conductive film 161a and the first upper conductive film 161c.

[0039] The first lower conductive film 161a may include a conductive semiconductor material. The first lower conductive film 161a may include at least one of polycrystalline silicon, polycrystalline silicon germanium, polycrystalline germanium, amorphous silicon, amorphous silicon germanium, and / or amorphous germanium. The first insertion conductive film 161b may include, for example, a metal silicide material. The first upper conductive film 161c may include, for example, at least one of tungsten, aluminum, and / or copper. In some embodiments, each of the first lower conductive film 161a, the first insertion conductive film 161b, and the first upper conductive film 161c may include multiple film materials.

[0040] The first hard mask pattern 171 may be disposed on the first conductive film structure 161. The first hard mask pattern 171 may include silicon nitride or silicon oxide.

[0041] The second transistor (i.e., the transistor) can be disposed in the PMOS region RP. The second transistor may include a second gate stack G2, a second gate spacer 182, and a second source / drain region 107. The second transistor may be a p-type planar transistor.

[0042] The second gate spacer 182 may be disposed on at least one side of the second gate stack G2. For example, the second gate spacer 182 may be disposed on both sides of the second gate stack G2.

[0043] The second gate spacer 182 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon carbonitride (SiCN), and / or combinations thereof.

[0044] The second gate stack G2 may include a second interface insulating film 122, a second high dielectric constant insulating film 132, a second metal layer 142, a second protective layer 152, a second conductive film structure 162, and a second hard mask pattern 172, which are stacked sequentially.

[0045] The second interface insulating film 122 can be directly disposed on the substrate. The second interface insulating film 122 may include, for example, a silicon oxide film or a silicon oxynitride film. The second high dielectric constant insulating film 132 may be disposed on the second interface insulating film 122. The second high dielectric constant insulating film 132 may include, for example, a high-k dielectric material having a dielectric constant higher than that of silicon oxide. The second high dielectric constant insulating film 132 may include, for example, hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), lead scandium tantalum oxide (PbScTaO), and / or combinations thereof, but the scope of this disclosure is not limited thereto.

[0046] For example, when both the first high dielectric constant insulating film 131 and the second high dielectric constant insulating film 132 contain lanthanum, the concentration of lanthanum contained in the second high dielectric constant insulating film 132 can be higher than the concentration of lanthanum contained in the first high dielectric constant insulating film 131.

[0047] The second metal layer 142 may be disposed on the second high dielectric constant insulating film 132. The second metal layer 142 may include at least one of, for example, titanium (Ti), aluminum (Al), tungsten (W), molybdenum (Mo), and / or lanthanum (La). The second metal layer 142 may include the same metal material as the first metal layer 141.

[0048] The second protective layer 152 may be disposed on the second metal layer 142. For example, the second protective layer 152 may be disposed directly on the second metal layer 142. Therefore, in some embodiments, it is not necessary to insert another layer between the second protective layer 152 and the second metal layer 142.

[0049] The second protective layer 152 may include an oxide or oxynitride of a metal contained in the second metal layer 142. For example, when the second metal layer 142 includes titanium aluminum nitride (TiAlN), the second protective layer 152 may include titanium oxide (TiO).

[0050] The concentration of oxygen (O) contained in the second protective layer 152 is higher than the concentration of oxygen contained in the second metal layer 142. For reference, comparing the oxygen concentration contained in the second protective layer 152 also applies even if the second metal layer 142 does not contain oxygen. That is, even if the second metal layer 142 does not contain oxygen, the oxygen concentration contained in the second protective layer 152 can be expressed as higher than the oxygen concentration contained in the second metal layer 142. In other words, even when the second metal layer 142 does not contain oxygen (i.e., the oxygen concentration in the second metal layer 142 is practically undetectable or negligible), it is still a case where the oxygen concentration in the second protective layer 152 is higher than the oxygen concentration in the second metal layer 142.

[0051] When the second protective layer 152 has a higher oxygen concentration than the second metal layer 142, oxygen can be prevented from flowing into the second metal layer 142 from the top of the second protective layer 152. Therefore, the performance and reliability of the semiconductor device can be improved.

[0052] The second conductive film structure 162 may be disposed on the upper surface of the second protective layer 152. The second conductive film structure 162 may include a metallic material. The second conductive film structure 162 may include a second lower conductive film 162a, a second inserted conductive film 162b, and a second upper conductive film 162c. The second lower conductive film 162a, the second inserted conductive film 162b, and the second upper conductive film 162c may be sequentially stacked on the upper surface of the second protective layer 152. In other words, the second inserted conductive film 162b may be disposed between the second lower conductive film 162a and the second upper conductive film 162c.

[0053] The second lower conductive film 162a may include a conductive semiconductor material. The second lower conductive film 162a may include at least one of polycrystalline silicon, polycrystalline silicon germanium, polycrystalline germanium, amorphous silicon, amorphous silicon germanium, and / or amorphous germanium. The second insertion conductive film 162b may include, for example, a metal silicide material. The second upper conductive film 162c may include, for example, at least one of tungsten, aluminum, and / or copper. In some embodiments, each of the second lower conductive film 162a, the second insertion conductive film 162b, and the second upper conductive film 162c may include multiple film materials.

[0054] The second hard mask pattern 172 may be disposed on the second conductive film structure 162. The second hard mask pattern 172 may include silicon nitride or silicon oxide.

[0055] The height H1 of the first gate stack G1 on the third-direction DR3 can be greater than the height H2 of the second gate stack G2 on the third-direction DR3. For example, the height H1 of the first gate stack G1 on the third-direction DR3 can be 10 Å (i.e., 10 angstroms) greater than the height H2 of the second gate stack G2 on the third-direction DR3, but it is not limited thereto.

[0056] The width T1 of the first protective layer 151 in the third direction DR3 can be less than the width T2 of the first metal layer 141 in the third direction DR3. The width T4 of the second protective layer 152 in the third direction DR3 can be less than the width T5 of the second metal layer 142 in the third direction DR3. For example, the width T2 of the first metal layer 141 in the third direction DR3 can be three times (i.e., 3X) the width T1 of the first protective layer 151 in the third direction DR3. As used herein, the term "width" refers to the thickness in any corresponding direction. For example, the width T1 of the first protective layer 151 can refer to the thickness of the first protective layer in the third direction DR3.

[0057] The width T1 of the first protective layer 151 on the third-direction DR3 can be the same as the width T4 of the second protective layer 152 on the third-direction DR3. The width T2 of the first metal layer 141 on the third-direction DR3 can be the same as the width T5 of the second metal layer 142 on the third-direction DR3. The width T3 of the first high-dielectric-constant insulating film 131 on the third-direction DR3 can be smaller than the width T6 of the second high-dielectric-constant insulating film 132 on the third-direction DR3.

[0058] Figure 2 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure. For ease of description, the description of Figure 2 will be based on the differences from Figure 1.

[0059] Referring to FIG2, a semiconductor device according to other embodiments of the present disclosure may include a substrate 100, a first gate stack G1, a first gate spacer 181, a second gate stack G2, and a second gate spacer 182.

[0060] The first gate stack G1 may include a first interface insulating film 121, a first high dielectric constant insulating film 131, a first metal layer 141, a first protective layer 151, a first conductive film structure 161, and a first hard mask pattern 171, which are stacked sequentially.

[0061] The first metal layer 141 may be disposed on the first high dielectric constant insulating film 131. The first metal layer 141 may, for example, be disposed directly on the first high dielectric constant insulating film 131. In some embodiments, it is not necessary to insert another layer between the first high dielectric constant insulating film 131 and the first metal layer 141. The width K1 (e.g., T3) of the first high dielectric constant insulating film 131 in the third direction DR3 may be greater than the width K2 (e.g., T6) of the second high dielectric constant insulating film 132 in the third direction DR3.

[0062] Figure 3 is a plan view illustrating a substrate for describing a semiconductor device according to some embodiments of the present disclosure. Figure 4 is a schematic enlarged layout view of the first region R1 of Figure 3. Figure 5 is a cross-sectional view taken along lines A-A', B-B', and C-C' of Figure 3. For ease of description, the descriptions of Figures 3, 4, and 5 will be based on the differences from Figure 1.

[0063] For reference, the height of the upper surface 110US of the device isolation film 110 in the A-A' cross-sectional view is shown to be different from the height of the upper surface 110US of the device isolation film 110 in the B-B' cross-sectional view and the height of the upper surface 110US of the device isolation film 110 in the C-C' cross-sectional view. However, this is only for ease of description and does not limit the exemplary embodiment. That is, the height of the upper surface 110US of the device isolation film 110 in the A-A' cross-sectional view, the height of the upper surface 110US of the device isolation film 110 in the B-B' cross-sectional view, and the height of the upper surface 110US of the device isolation film 110 in the C-C' cross-sectional view can all be the same height.

[0064] Referring to Figures 3, 4, and 5, the substrate 100 may include a first region R1 and a second region R2. The first region R1 may be surrounded by the second region R2. For example, in a plan view of a horizontal plane formed by a first direction DR1 and a second direction DR2, the second region R2 may surround the first region R1. The first region R1 may be a cell array region. The second region R2 may be a peripheral region or a core peripheral region. The first region R1 may be a region where memory cells of memory devices are arranged. The second region R2 may be a region where transistors are formed around the memory cell region and control the operation of the memory cells.

[0065] The first region R1 may include a word line WL, a bit line BL, a buried contact BC, a direct contact DC, and a landing pad LP. Multiple buried gate structures 114 may be disposed on the substrate 100 of the first region R1. The multiple buried gate structures 114 may be parallel to each other while being spaced apart from each other at predetermined intervals.

[0066] Multiple gate electrodes extending in the first direction DR1 can be configured to span the cell active region ACT. The multiple gate electrodes can extend parallel to each other. The multiple gate electrodes can be, for example, multiple word lines WL. The word lines WL can be arranged at equal intervals. The width of the word lines WL or the spacing between the word lines WL can be determined depending on design rules.

[0067] Multiple bit lines BL, orthogonal to the word line WL and extending in the second direction DR2, can be set on the word line WL. The multiple bit lines BL can extend parallel to each other (i.e., extend in parallel to each other). The bit lines BL can be set at equal intervals. The width of the bit lines BL or the interval between the bit lines BL can be determined depending on design rules.

[0068] Semiconductor memory devices according to some embodiments may include various contact arrangements formed on the cell active region ACT. For example, various contact arrangements may include direct contact DC, buried contact BC, and / or landing pad LP.

[0069] In this context, direct contact DC can refer to the contact used to electrically connect the cell active region ACT to the bit line BL. Buried contact BC can refer to the contact used to connect the cell active region ACT to the lower electrode of the data storage pattern. The contact area between the buried contact BC and the cell active region ACT may be small. Therefore, to expand the contact area with the cell active region ACT and the contact area with the lower electrode, a conductive landing pad LP can be introduced.

[0070] The landing pad LP can be positioned between the cell active region ACT and the buried contact BC, or between the buried contact BC and the lower electrode. Introducing the landing pad LP to expand the contact area can reduce the contact resistance between the cell active region ACT and the lower electrode of the capacitor.

[0071] When the buried contact BC is located at both ends of the cell active region ACT, the landing pad LP can be configured to partially overlap with the buried contact BC by being adjacent (i.e., physically or electrically connected) to both ends of the cell active region ACT.

[0072] Word lines WL can be formed in the substrate 100 in a buried structure. Word lines WL can be configured to intersect with a cell active region ACT between a direct contact DC or a buried contact BC. As shown, two word lines WL can be configured to intersect with a single cell active region ACT. When the cell active region ACT extends on the third direction DR3, the word line WL can have an angle of less than 90° with the cell active region ACT.

[0073] The direct contact DC and the buried contact BC can be arranged symmetrically. Therefore, the direct contact DC and the buried contact BC can be arranged on a straight line in the first direction DR1 and the second direction DR2.

[0074] The landing pad LP can be set in a zigzag shape on the second direction DR2 where the bit line BL extends. In addition, the landing pad LP can be set to overlap with the same side portion of each bit line BL on the first direction DR1 where the word line WL extends.

[0075] For example, each of the landing pads LP of the first line can overlap with the left side of the corresponding bit line BL, and each of the landing pads LP of the second line can overlap with the right side of the corresponding bit line BL.

[0076] The buried gate structure 114 may include a buried gate insulating film 108, a buried gate electrode 111, and a buried mask pattern 112. The buried gate insulating film 108 may be disposed between the buried gate electrode 111 and the substrate 100, between the buried gate electrode 111 and the device isolation film 110, between the buried mask pattern 112 and the substrate 100, and between the buried mask pattern 112 and the device isolation film 110. The buried mask pattern 112 may be disposed on the buried gate electrode 111. The buried gate electrode 111 may be in contact with the substrate 100 and the device isolation film 110. The buried mask pattern 112 may be in contact with the substrate 100 and the device isolation film 110.

[0077] The buried gate insulating film 108 may include, for example, silicon oxide. The buried gate electrode 111 may include a metallic material or a polycrystalline silicon material. The buried gate electrode 111 may have, for example, a barrier metal film and a stacked structure of metal films. The buried mask pattern 112 may include, for example, a nitride film.

[0078] Contact plug 134 may be disposed on buried mask pattern 112. Contact plug 134 may include, for example, polysilicon material, but is not limited thereto.

[0079] An insulating film structure 190, comprising multiple insulating films, may be disposed on a substrate 100 between contact plugs 134. The insulating film structure 190 may include a first insulating film 191 and a second insulating film 192. The first insulating film 191 and the second insulating film 192 may comprise different materials from each other. Each of the first insulating film 191 and the second insulating film 192 may comprise, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride. As another example, the insulating film structure 190 may be a structure comprising a single film.

[0080] The third conductive film structure 163 can be disposed on the upper surface of the second insulating film 192. The third conductive film structure 163 may include the same material as the first conductive film structure 161 and may have the same stacking structure as the first conductive film structure 161. That is, the third conductive film structure 163 may include a third lower conductive film 163a, a third insert conductive film 163b, and a third upper conductive film 163c, which are stacked sequentially. In other words, the third insert conductive film 163b may be disposed between the third lower conductive film 163a and the third upper conductive film 163c. For reference, each of the first conductive film structure 161, the second conductive film structure 162, and the third conductive film structure 163 may correspond to bit line BL in FIG. 4.

[0081] The third hard mask pattern 170 may be disposed on the third conductive film structure 163. The third hard mask pattern 170 may include the same material as the first hard mask pattern 171.

[0082] Figures 6, 7, 8, 9, 10, 11, 12, 13, and 14 are diagrams illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0083] Referring to Figure 6, a substrate 100 may be provided, including a device isolation film 110, a first source / drain region 105, and a second source / drain region 107. A pre-interface insulating film 120p, a pre-high dielectric constant insulating film 130p, a pre-insertion layer 210p, a pre-dummy layer 220p, and a coating layer 501 may be sequentially stacked on the substrate 100.

[0084] The coating layer 501 may include, for example, a bottom anti-reflective coating (BARC) material.

[0085] Referring to Figure 7, mask 601 can be formed on coating layer 501 in NMOS region RN. Mask 601 can be, for example, a photoresist (PR). Mask 601 is not formed in PMOS region RP.

[0086] Referring to Figure 8, portions of the coating layer 501, the pre-dummy layer 220p, and the pre-insertion layer 210p of the PMOS region RP can be removed. Portions of the coating layer 501, the pre-dummy layer 220p, and the pre-insertion layer 210p of the PMOS region RP can be selectively removed using etching. The coating layer 501 and the pre-dummy layer 220p of the PMOS region RP can be completely removed. The pre-insertion layer 210p of the PMOS region RP is partially removed and partially retained.

[0087] Referring to Figure 9, the mask (e.g., 601 in Figure 8), coating layer 501, and pre-dummy layer 220p of the NMOS region RN can be removed. The coating layer 501 and pre-dummy layer 220p of the NMOS region RN can be completely removed.

[0088] Referring to Figure 10, a pre-metal layer 140p can be formed on the NMOS region RN and the PMOS region RP. The pre-metal layer 140p can be formed on the pre-insertion layer 210p in the NMOS region RN. The pre-metal layer 140p can also be formed on the partially removed pre-insertion layer 210p in the PMOS region RP.

[0089] Referring to Figure 11, a lower preconductive film 160ap, a pre-insertion conductive film 160bp, and a upper preconductive film 160cp can be sequentially formed on the NMOS region RN and the PMOS region RP. In other words, the lower preconductive film 160ap, the pre-insertion conductive film 160bp, and the upper preconductive film 160cp can be sequentially formed on the pre-metal layer 140p in the NMOS region RN, and the lower preconductive film 160ap, the pre-insertion conductive film 160bp, and the upper preconductive film 160cp can be sequentially formed on the pre-metal layer 140p in the PMOS region RP.

[0090] Subsequently, referring to FIG12, an annealing process 1000 can be performed on the NMOS region RN and the PMOS region RP. A pre-protective layer 150p can be formed on the upper portion of the pre-metallization layer 140p in the NMOS region RN and the PMOS region RP through the annealing process 1000. In other words, the pre-protective layer 150p can be formed between the pre-metallization layer 140p and the pre-lower conductive film 160ap. The pre-protective layer 150p may comprise an oxide or oxynitride formed from the pre-metallization layer 140p by applying heat to the pre-metallization layer 140p.

[0091] The pre-insertion layer (see 210p in FIG11) that was not completely removed from the PMOS region RP by the annealing process 1000 is diffused into the pre-high dielectric constant insulating film (see 130p in FIG11), so that a pre-second high dielectric constant insulating film 132p can be formed.

[0092] Referring to Figure 13, a gate mask can be formed on the pre-upper conductive film 160cp in the NMOS region RN and the PMOS region RP. The pre-interface insulating film 120p, pre-high dielectric constant insulating film 130p, pre-insertion layer 210p, pre-metal layer 140p, pre-protective layer 150p, pre-lower conductive film 160ap, pre-insertion conductive film 160bp, and pre-upper conductive film 160cp in the NMOS region RN, which are not covered by the gate mask, can be removed. Similarly, the pre-interface insulating film 120p, pre-second high dielectric constant insulating film 132p, pre-metal layer 140p, pre-protective layer 150p, pre-lower conductive film 160ap, pre-insertion conductive film 160bp, and pre-upper conductive film 160cp in the PMOS region RP, which are not covered by the gate mask, can be removed. The terms “cover” and the like used in this document can specify an element, component, or layer that is partially or completely on, around, overlaps with, or surrounds another element, component, or layer.

[0093] Referring to Figure 14, a first gate stack G1 and a second gate stack G2 can be formed. The first gate stack G1 can be formed on the NMOS region RN, and the second gate stack G2 can be formed on the PMOS region RP. A first interface insulating film 121, a first high-dielectric-constant insulating film 131, an insertion layer 210, a first metal layer 141, a first protective layer 151, a first conductive film structure 161, and a first hard mask pattern 171 can be formed, which are sequentially stacked on the NMOS region RN. A second interface insulating film 122, a second high-dielectric-constant insulating film 132, a second metal layer 142, a second protective layer 152, a second conductive film structure 162, and a second hard mask pattern 172 can be formed, which are sequentially stacked on the PMOS region RP.

[0094] The first gate stack G1 can be formed by removing a portion of the stacked structure of the NMOS region RN, which does not overlap with the gate mask of FIG13, until the upper surface of the exposed substrate 100 is exposed. The second gate stack G2 can be formed by removing a portion of the stacked structure of the PMOS region RP, which does not overlap with the gate mask of FIG13, until the upper surface of the exposed substrate 100 is exposed.

[0095] For example, the first interface insulating film 121 of the NMOS region RN and the second interface insulating film 122 of the PMOS region RP can be formed by patterning the pre-interface insulating film 120p. The first high-dielectric-constant insulating film 131 of the NMOS region RN can be formed by patterning the pre-high-dielectric-constant insulating film 130p. The second high-dielectric-constant insulating film 132 of the PMOS region RP can be formed by patterning the pre-second high-dielectric-constant insulating film 132p.

[0096] The insertion layer 210 of the NMOS region RN can be formed by patterning the pre-insertion layer 210p. The first metal layer 141 of the NMOS region RN can be formed by patterning the pre-metal layer 140p. The second metal layer 142 of the PMOS region RP can be formed by patterning the pre-metal layer 140p.

[0097] The first protective layer 151 of the NMOS region RN can be formed by patterning the pre-protective layer 150p. The second protective layer 152 of the PMOS region RP can be formed by patterning the pre-protective layer 150p. The first lower conductive film 161a of the NMOS region RN can be formed by patterning the pre-lower conductive film 160ap. The second lower conductive film 162a of the PMOS region RP can be formed by patterning the pre-lower conductive film 160ap. The first insertion conductive film 161b of the NMOS region RN can be formed by patterning the pre-insertion conductive film 160bp. The second insertion conductive film 162b of the PMOS region RP can be formed by patterning the pre-insertion conductive film 160bp. The first upper conductive film 161c of the NMOS region RN can be formed by patterning the pre-upper conductive film 160cp. The second upper conductive film 162c of the PMOS region RP can be formed by patterning the pre-upper conductive film 160cp.

[0098] Next, referring to FIG1, a first gate spacer 181 may be formed on at least one side of the first gate stack G1. A second gate spacer 182 may be formed on at least one side of the second gate stack G2.

[0099] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without departing from the technical spirit and inventive concept of this disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A semiconductor device, comprising: A substrate comprising an NMOS region and a PMOS region; a first transistor in the NMOS region comprising a first gate stack and a first source / drain region, wherein the first source / drain region is adjacent to at least one side of the first gate stack; and a second transistor in the PMOS region comprising a second gate stack and a second source / drain region, wherein the second source / drain region is adjacent to at least one side of the second gate stack, wherein the first gate stack comprises a first high-dielectric-constant insulating film, an insertion layer, a first metal layer and a first protective layer sequentially stacked in a first direction, and the second gate stack comprises a second high-dielectric-constant insulating film, a second metal layer and a second protective layer sequentially stacked in the first direction, wherein the oxygen concentration of the first protective layer is higher than the oxygen concentration of the first metal layer, and the oxygen concentration of the second protective layer is higher than the oxygen concentration of the second metal layer.

2. The semiconductor device according to claim 1, wherein, In the first direction, the thickness of the first protective layer is less than the thickness of the first metal layer, and in the first direction, the thickness of the second protective layer is less than the thickness of the second metal layer.

3. The semiconductor device according to claim 1, wherein, In the first direction, the thickness of the first protective layer is equal to the thickness of the second protective layer, and in the first direction, the thickness of the first metal layer is equal to the thickness of the second metal layer.

4. The semiconductor device according to claim 1, wherein, In the first direction, the thickness of the first high dielectric constant insulating film is less than the thickness of the second high dielectric constant insulating film.

5. The semiconductor device according to claim 1, wherein, The first protective layer comprises an oxide or oxynitride of a first element, wherein the first element is the same as the element of the first metal layer, and the second protective layer comprises an oxide or oxynitride of a second element, wherein the second element is the same as the element of the second metal layer.

6. The semiconductor device according to claim 1, wherein, The lanthanum (La) concentration in the second high-dielectric-constant insulating film is higher than that in the first high-dielectric-constant insulating film.

7. The semiconductor device according to claim 1, wherein, In the first direction, the thickness of the first gate stack is greater than the thickness of the second gate stack.

8. The semiconductor device according to claim 1, wherein, The first metal layer and the second metal layer respectively include at least one of titanium (Ti), aluminum (Al), tungsten (W), molybdenum (Mo), or lanthanum (La).

9. The semiconductor device according to claim 1, wherein, The first metal layer and the second metal layer comprise the same metallic material.

10. A semiconductor device, comprising: A substrate comprising a cell array region and a peripheral region, wherein the cell array region includes a buried gate structure, and the peripheral region includes an NMOS region and a PMOS region with different conductivity types; a first transistor in the NMOS region including a first gate stack and a first source / drain region, wherein the first source / drain region is adjacent to at least one side of the first gate stack; and a second transistor in the PMOS region including a second gate stack and a second source / drain region, wherein the second source / drain region is adjacent to at least one side of the second gate stack, wherein the first gate stack includes a first high-dielectric-constant insulating film, an insertion layer, a first metal layer and a first protective layer sequentially stacked in a first direction, and the second gate stack includes a second high-dielectric-constant insulating film, a second metal layer and a second protective layer sequentially stacked in the first direction, wherein the oxygen concentration of the first protective layer is higher than the oxygen concentration of the first metal layer, and the oxygen concentration of the second protective layer is higher than the oxygen concentration of the second metal layer.

11. The semiconductor device according to claim 10, wherein, The first transistor further includes a first gate spacer on at least one side of the first gate stack, and the second transistor further includes a second gate spacer on at least one side of the second gate stack.

12. The semiconductor device according to claim 10, wherein, The first metal layer and the second metal layer comprise the same metallic material.

13. The semiconductor device according to claim 10, wherein, The insertion layer comprises lanthanum (La).

14. The semiconductor device according to claim 10, wherein, The first high dielectric constant insulating film does not include lanthanum (La), and the second high dielectric constant insulating film includes lanthanum (La).

15. The semiconductor device according to claim 10, wherein, The lanthanum (La) concentration in the second high-dielectric-constant insulating film is higher than that in the first high-dielectric-constant insulating film.

16. The semiconductor device according to claim 10, wherein, In the first direction, the thickness of the first protective layer is less than the thickness of the first metal layer, and in the first direction, the thickness of the second protective layer is less than the thickness of the second metal layer.

17. The semiconductor device according to claim 10, wherein, The first protective layer comprises an oxide or oxynitride of a first element, wherein the first element is the same as the element of the first metal layer, and the second protective layer comprises an oxide or oxynitride of a second element, wherein the second element is the same as the element of the second metal layer.

18. The semiconductor device according to claim 10, wherein, In the first direction, the thickness of the first protective layer is equal to the thickness of the second protective layer.

19. The semiconductor device according to claim 10, wherein, In the first direction, the thickness of the first metal layer is equal to the thickness of the second metal layer.

20. A semiconductor device, comprising: A substrate comprising an NMOS region and a PMOS region; a first transistor in the NMOS region comprising a first gate stack and a first source / drain region, wherein the first source / drain region is adjacent to at least one side of the first gate stack; and a second transistor in the PMOS region comprising a second gate stack and a second source / drain region, wherein the second source / drain region is adjacent to at least one side of the second gate stack, wherein the first gate stack comprises a first high-dielectric-constant insulating film, an insertion layer, a first metal layer and a first protective layer sequentially stacked in a first direction, and the second gate stack comprises a second high-dielectric-constant insulating film, a second metal layer and a second protective layer sequentially stacked in the first direction, wherein the oxygen concentration of the first protective layer is higher than the oxygen concentration of the first metal layer, the oxygen concentration of the second protective layer is higher than the oxygen concentration of the second metal layer, and the lanthanum (La) concentration in the first high-dielectric-constant insulating film is higher than the lanthanum (La) concentration in the second high-dielectric-constant insulating film.

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