Three-dimensional core particle stacking type storage system chip based on independent TSV array adapter body core particles and manufacturing method of three-dimensional core particle stacking type storage system chip
By independently setting TSV array adapter cores on the side of the memory device cores, efficient manufacturing of three-dimensional core-stacked memory systems has been achieved, solving the problems of process complexity and cost of traditional three-dimensional stacked memory devices, and improving integration and signal interconnection efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 上海曜感科技有限公司
- Filing Date
- 2026-01-20
- Publication Date
- 2026-05-01
AI Technical Summary
Traditional three-dimensional stacked storage devices suffer from problems such as large storage cell area, high process complexity, high cost and low manufacturing yield. Furthermore, the adapter board cannot efficiently support the vertical stacking of multiple layers of chips and signal aggregation and extraction.
A three-dimensional stacked memory system based on independent TSV array adapter chips is adopted. By independently setting TSV array adapter chips on the side of the memory device chip, vertical TSV array interconnection is achieved, and each layer of pads is connected by lateral interconnects and metal microbumps. Signals are led out from the memory device chip through the TSV array adapter chips.
It simplifies the manufacturing process of memory device chips, improves integration and yield, reduces manufacturing costs, and enables high-bandwidth signal interconnection and fan-out.
Smart Images
Figure CN121969221A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor chip three-dimensional packaging and system integration technology, and in particular to a three-dimensional chip stacked memory system chip and manufacturing method based on independent TSV array adapter chips, suitable for high bandwidth memory (HBM) and other scenarios. Background Technology
[0002] With the rapid increase in demand for storage bandwidth and capacity from applications such as artificial intelligence and high-performance computing, three-dimensional stacked memories (such as HBM) have become an important solution. Traditional three-dimensional stacking often uses TSVs (Through Silicon Vias) embedded inside each memory chip to achieve vertical interconnection, but this occupies valuable memory cell area, increases chip process complexity and cost, and negatively impacts the manufacturing yield of memory devices.
[0003] On the other hand, interposers have been used as interconnect carriers in 2.5D packaging, but they are usually located below the chip and only achieve planar interconnects, which cannot efficiently support the vertical stacking of multi-layer chips and signal aggregation and outgoing.
[0004] Therefore, a new three-dimensional stacked interconnect architecture is needed that can maintain the simplicity and high density of memory device chips while achieving high-bandwidth interconnects under multi-layer stacking. Summary of the Invention
[0005] To address the aforementioned problems, the present invention aims to provide a three-dimensional stacked memory system chip based on independent TSV array adapter chips, comprising: The bottom substrate layer is either a carrier wafer or a logic chip wafer; Several layers of memory device chips are stacked upside down on the bottom substrate layer; At least one TSV array adapter chip is independently disposed on the side of the memory device chip stack layer, and a vertically penetrating TSV array is integrated inside it. They are stacked upside down on the bottom substrate layer. Among them, the front I / O pads of the first layer memory device chip are interconnected with the I / O pads of the bottom substrate layer, and the front I / O pads of the first layer TSV array adapter chip are interconnected with the I / O pads of the bottom substrate layer. Starting from the second layer, the front I / O pads of each memory device chip are interconnected with the back I / O pads of the adjacent memory device chip below it, and the front I / O pads of each TSV array adapter chip are interconnected with the back I / O pads of the adjacent TSV array adapter chip below it. Lateral interconnects located on the back of the memory device chip and the TSV array adapter chip interconnect the back I / O pads of the memory device chip and the TSV array adapter on the same layer. The TSV array adapter core chip leads the signal to the external I / O pads through its TSV array.
[0006] Optionally, the bottom substrate layer has a TSV and external I / O pads interconnected with the TSV.
[0007] Optionally, the TSV array adapter core is disposed on the I / O pad side of the memory device, including one side, two sides, three sides, or four sides of the memory device.
[0008] Optionally, when the bottom substrate layer is a logic chip wafer, its surface I / O pads are directly interconnected with the front I / O pads of the first layer memory device chip on it through metal microbumps.
[0009] Optionally, the front I / O pads of the first layer memory device chip and the I / O pads of the bottom substrate layer, and the front I / O pads of the first layer TSV array adapter chip and the I / O pads of the bottom substrate layer are interconnected by a first interconnect metal. Starting from the second layer, the front I / O pads of each memory chip layer and the back I / O pads of the adjacent memory chip layer below it, as well as the front I / O pads of each TSV array adapter chip layer and the back I / O pads of the adjacent TSV array adapter chip layer below it, are interconnected by corresponding interconnect metals.
[0010] Optionally, the interconnect metal is a hybrid bonding in-situ interconnect bonding metal.
[0011] Optionally, in the three-dimensional stacked memory system chip based on independent TSV array adapter chips, the interconnect metal is a microbump.
[0012] Optionally, the interconnect metal is a metal-bonded in-situ interconnect metal.
[0013] Optionally, the interconnecting metal is a solder ball.
[0014] Optionally, the lateral interconnects are embedded microstrip lines, silicon bridge interconnects, or metal traces formed using thin film deposition and photolithography processes.
[0015] Optionally, the storage device chip is a storage device chip without embedded TSV, and its storage cell array area is not occupied by TSV.
[0016] Optionally, the TSV array adapter core is made of silicon, glass, or an organic substrate, and the metal filled in the TSV is copper, tungsten, or polycrystalline silicon.
[0017] A method for manufacturing a three-dimensional stacked memory system chip based on independent TSV array adapter chips as described above includes the following steps: S10: Provide a bottom substrate layer and fabricate bottom substrate layer I / O pads on its upper surface; S20: Fabricate multiple memory device chips and multiple TSV array adapter chips; wherein, the memory device chip is a traditional memory device chip without embedded TSV, and front I / O pads and back I / O pads are fabricated on its front and back sides respectively; the TSV array adapter chip integrates a vertically penetrating TSV array, and front I / O pads are fabricated on its front side. S30: Perform the first layer stacking and bonding, and bond the first layer memory device chip and the first layer TSV array adapter chip to the bottom substrate layer inverted, so that the front I / O pads of each chip are perpendicular to the corresponding I / O pads on the bottom substrate layer. S40: Perform vertically opposite front I / O pads to bottom substrate I / O pads; S50: A lateral interconnect is formed on the back side of the first layer stacked structure to electrically interconnect the back side I / O pads of the first layer memory device chip and the back side I / O pads of the first layer TSV array adapter chip. S60: Perform Nth layer stacking, bonding and interconnection, where N≥2; S70: Repeat step S60 until the preset number of layers are stacked to obtain the three-dimensional stacked memory system chip; wherein, the TSV array adapter chip leads the signal to the external I / O pad through its TSV array.
[0018] Optionally, in step S40, in-situ growth of the first layer of interconnect metal is performed: metal is selectively grown on the surfaces of the vertically opposite front I / O pads and bottom substrate I / O pads through the first bonded cavity or the channel connected thereto, until the grown metals are connected as one to form the first interconnect metal connecting the upper and lower pads.
[0019] Optionally, in step S30, the first layer stacking and bonding are performed: the first layer memory device chip and the first layer TSV array adapter chip are flipped upside down and bonded to the bottom substrate layer using bonding material; wherein, the bonding material is located outside the pad area, so that the front I / O pads of each chip are perpendicularly opposite to the corresponding I / O pads on the bottom substrate layer.
[0020] Optionally, the bottom substrate layer is a carrier wafer, and step S10 further includes the steps of forming a TSV in the carrier wafer and forming external I / O pads interconnected with the TSV on its lower surface.
[0021] Optionally, step S60 includes: The Nth layer memory device chip and the Nth layer TSV array adapter chip are flip-bonded to the back side of the N-1 layer stacked structure; In this configuration, the front I / O pads of the Nth layer core are perpendicularly opposite to the back I / O pads of the corresponding N-1 layer core. Lateral interconnects are formed on the back side of the Nth layer stacked structure to electrically interconnect the back side I / O pads of the Nth layer memory device chip and the back side I / O pads of the Nth layer TSV array adapter chip.
[0022] Optionally, step S60 includes: The Nth layer memory device chip and the Nth layer TSV array adapter chip are flipped upside down and bonded to the back side of the (N-1)th layer stack structure using bonding material; wherein the bonding material is located outside the pad area, such that the front I / O pad of the Nth layer chip is perpendicularly opposite to the back I / O pad of the corresponding chip in the (N-1)th layer, and an Nth bonded cavity is formed therebetween. Metal is selectively grown onto the vertically opposite pad surfaces through the Nth bonded cavity or the channel connected to it, until the grown metal is connected as one, forming the Nth metal microbump connecting the upper and lower pads. Lateral interconnects are formed on the back side of the Nth layer stacked structure to electrically interconnect the back side I / O pads of the Nth layer memory device chip and the back side I / O pads of the Nth layer TSV array adapter chip.
[0023] Optionally, in steps S40 and S60, the lateral interconnect is formed in one of the following ways: Metal traces are directly formed on the back side of the stacked structure using thin film deposition and photolithography. A silicon bridge containing an embedded microstrip line is fabricated and bonded to the back of the stacked structure to interconnect the corresponding pads; The metal traces are formed using a redistribution layer process.
[0024] Optionally, in steps S30 and S50, the TSV array adapter chip is configured on the I / O pad side of the memory device chip, and its layout includes being located on one side, two sides, three sides, or four sides of the memory device.
[0025] Optionally, the bonding material is a dry film or a bonding adhesive.
[0026] Optionally, in steps S40 and S60, the selective metal growth process is one or more combinations of electroplating, PVD, CVD, or electroless plating.
[0027] Beneficial effects of this invention: 1. Fundamentally eliminating the need for vertical embedding of silicon through-hole metal interconnect pillars into each chip to achieve vertical interconnection between chips, this not only significantly simplifies the manufacturing process of cell array memory chip wafers, but also eliminates the need for chip stacking and micro-bump array flip-chip bonding or copper-copper micro-solder hybrid bonding interconnection. At the same time, the chip area required for embedding the silicon through-hole metal interconnect pillar array is allocated to the cell array memory. This provides an effective technical approach to simplify the chip processing technology of cell array memory, reduce the overall packaging process difficulty of system chips, improve the overall yield of system chips, and reduce the overall manufacturing cost.
[0028] 2. This invention solves the problem that chips with different process technologies cannot be formed on the same production line by three-dimensional chip stacking, as well as the problem of increased size caused by packaging chips with different process technologies. This results in larger computing chips with higher integration, lower power consumption, and faster speed. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1 This is a cross-sectional schematic diagram of a three-dimensional stacked memory system chip based on an independent TSV array adapter chip according to an embodiment of the present invention. Figures 2-5 This is a cross-sectional schematic diagram of a method for manufacturing a three-dimensional stacked memory system chip based on an independent TSV array adapter chip, according to an embodiment of the present invention. Figure 6 This is a schematic diagram illustrating a method for manufacturing a three-dimensional stacked memory system chip based on an independent TSV array adapter chip, according to an embodiment of the present invention.
[0031] For ease of understanding and explanation, the labels in the diagram are as follows: 100 - Bottom substrate layer; 110 - Bonding material; 2001 - First layer memory device chip; 2002 - Second layer memory device chip; 211 - Front I / O pads of the memory device chip; 212 - Back I / O pads of the memory device chip; 2110 - Bottom substrate layer I / O pads; 2120 - Front I / O pads of the first layer memory device chip; 3001 - First metal microbumps; 3002 - Second metal microbump; 3003-Third metal microbump; 3004-Fourth metal microbump; 310-Cavity; 400-TSV array adapter core; 410-TSV array; 4001-Front-side I / O pads of the TSV array adapter core; 4002-Rear-side I / O pads of the TSV array adapter core; 500-Lateral interconnect; 600-External I / O pads; 601-Through silicon via. Detailed Implementation
[0032] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.
[0033] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower parts of the device in its normal operating state, while "inner" and "outer" refer to the parts relative to the outline of the device. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. This invention pertains to electrical devices; therefore, connection and interconnection both refer to conductive interconnection. Since the accompanying drawings describe the same device, the same reference numerals denote the same components. The term "chip front" as used herein refers to the side of the wafer used to form the device during chip manufacturing, and "back" refers to the substrate side of the wafer.
[0034] like Figure 1 As shown, one embodiment of the present invention provides a three-dimensional stacked memory system chip based on independent TSV array adapter chips, comprising: The bottom substrate layer 100 can be a simple carrier wafer or a logic chip wafer, such as a CPU or SoC (System-on-a-Chip). Figure 1As shown, in this embodiment, the bottom substrate layer 100 is a logic chip wafer with through-silicon vias (TSVs) 601 fabricated inside, and external I / O pads 600 interconnecting with the TSVs 601 are formed on its lower surface. In this embodiment, the bottom substrate layer I / O pads 2110 are directly interconnected with the first layer memory device chip 2001 on it via interconnect metal. In this specific embodiment, the interconnect metal is a metal microbump.
[0035] The memory chip stack layer includes a first layer of memory chip 2001, a second layer of memory chip 2002, etc., which are stacked upside down on the bottom substrate layer 100. Crucially, these memory chips are all conventional memory chips without embedded TSVs, such as DRAM chips using a 1αnm process. Their memory cell array areas are complete and not occupied by any TSVs, thus achieving higher storage density.
[0036] TSV array adapter chip 400: It is independently disposed on the side of the storage device chip stack layer. For example... Figure 1 As shown, this embodiment employs a symmetrical arrangement on both sides, with two TSV array adapter chips 400 located on opposite sides of the memory device stack layer. Each TSV array adapter chip 400 integrates a vertically penetrating TSV array 410. The substrate material can be silicon, and the TSVs (Through Silicon Vias) are filled with copper. In other embodiments, a glass substrate or an organic substrate can also be used, with the TSVs filled with tungsten or polycrystalline silicon.
[0037] In this configuration, the front I / O pad 2120 of the first-layer memory chip is interconnected with the bottom substrate I / O pad 2110. The front I / O pad 4001 of the first-layer TSV array adapter chip 400 is interconnected with the bottom substrate I / O pad 2110. The front I / O pad 211 of the second-layer memory chip 2002 is interconnected with the back I / O pad 212 of the first-layer memory chip 2001. The front I / O pad 4001 of the second-layer TSV array adapter chip is interconnected with the back I / O pad 4002 of the first-layer TSV array adapter chip.
[0038] In this embodiment, the interconnect metal is an integrated metal structure formed by in-situ growth of metal microbumps within a reserved cavity 310 between vertically opposite upper and lower I / O pads after the stack bonding. In other words, all of the aforementioned metal microbumps are not prefabricated solder balls, but rather an integrated metal structure formed in-situ by selective metal growth processes (such as electroless plating) within the reserved cavity 310 between vertically opposite I / O pads after the entire stack structure has been bonded and fixed. Figure 4 and Figure 5It vividly illustrates the process of cavities and bumps growing and fusing.
[0039] In this embodiment, the front I / O pad 2120 of the first layer memory device chip and the I / O pad 2110 of the bottom substrate layer 100 are interconnected by the first metal microbump 3001.
[0040] In this embodiment, the front I / O pads 4001 of the TSV array adapter core 400 of the first layer TSV array adapter core and the corresponding I / O pads of the bottom substrate layer 100 are also interconnected by metal microbumps (not separately labeled in the figure) similar to the first metal microbumps.
[0041] In this embodiment, the front I / O pad 211 of the memory chip of the second layer memory chip 2002 and the back I / O pad 212 of the memory chip of the first layer memory chip 2001 are interconnected by a second metal microbump 3002.
[0042] In this embodiment, the front I / O pads of the second-layer TSV array adapter core and the back I / O pads 4002 of the first-layer TSV array adapter core 400 are also interconnected by metal microbumps (not separately labeled in the figure) similar to the first metal microbumps 3001.
[0043] In other embodiments, the interconnect metal is a hybrid bonding in-situ interconnect bonding metal.
[0044] In other embodiments, the interconnect metal is a microbump. In other embodiments, the interconnect metal is a metal-bonded in-situ interconnect metal.
[0045] In other embodiments, the interconnecting metal is a solder ball.
[0046] Lateral interconnect 500: Located on the back side of each layer of memory device chip and TSV array adapter chip. For example... Figure 1 As shown, the lateral interconnect 500 electrically interconnects the back I / O pads 212 of the memory device die in the same layer (e.g., the first layer) and the back I / O pads 4002 of the TSV array adapter die in the same layer. In this embodiment, the lateral interconnect 500 is an embedded copper trace formed using thin-film deposition and photolithography. In other embodiments, silicon bridge interconnects or microstrip lines may also be used.
[0047] Signal extraction: Signals originate from the memory device chip and enter the TSV array adapter chip 400 via the lateral interconnect 500. They are then vertically transmitted through the internal TSV array 410 and finally extracted from the external I / O pads 600 of the bottom substrate layer 100. This achieves high-bandwidth vertical signal interconnection and fan-out.
[0048] In one embodiment, such as Figure 1 As shown, the TSV array adapter chip 400 is disposed on the side where the I / O pads 211 of the memory device chip are located, including single-sided, symmetrically arranged on both sides, three-sided, or four-sided surround arrangement, for example in... Figure 1 The two sides are shown. When positioned on both sides or all four sides, they can be used for signal transmission and power / ground distribution respectively to optimize signal integrity and power supply stability. For example, in a symmetrical arrangement on both sides, one side of the TSV array adapter core is dedicated to signal transmission, with a TSV pitch of 40-100μm and a diameter of 5-20μm; the other side is used for power / ground distribution, with the TSV pitch increased to 100-200μm and the diameter increased to 20-50μm to reduce resistance. In a four-sided surround arrangement, the TSVs can be allocated as: address / command bus, data bus, power, and ground, respectively, achieving optimal signal integrity and power supply network.
[0049] In one embodiment, when the bottom substrate layer 100 is a logic chip wafer, its surface I / O pads 2110 are directly interconnected with the front I / O pads 2120 of the first layer memory device chip 2001 via metal microbumps. In this case, the logic chip wafer 100 serves as both the substrate and the main control unit of the system, with the memory device chips stacked on it as high-bandwidth memory (HBM). For example, when the bottom substrate layer 100 is a logic chip wafer, its surface I / O pads 2110 are interconnected with the first layer memory device chip 2001 via aluminum.
[0050] In one embodiment, the lateral interconnect 500 is an embedded microstrip line, a silicon bridge interconnect, or a metal trace formed using thin-film deposition and photolithography. Specifically, copper, aluminum, or tungsten can be used as the conductor material, formed by electroplating or physical vapor deposition, and embedded in a low-k dielectric material to reduce parasitic capacitance. For example, in one embodiment, the lateral interconnect 500 adopts an embedded copper interconnect structure, specifically as follows: Deposit a 0.5-2 μm thick low-k dielectric layer (k=2.5-3.5), such as SiCOH (amorphous silicon-carbon-oxygen-hydrogen alloy film) or polyimide; define the interconnect pattern using photolithography with 193 nm immersion lithography, with linewidth / spacing of 0.5 μm / 0.5 μm to 2 μm / 2 μm; form trenches using reactive ion etching with C as the etching gas. Tetrafluoromethane / CH Trifluoromethane / Oxygen-mixed gas etching depth 1-3 μm; physical vapor deposition of 10 nm Ta / 20 nm TaN tantalum nitride diffusion barrier layer and 50 nm Cu copper seed layer; copper plating filler, current density 1-5 mA / cm², plating time 5-20 minutes, forming copper interconnects with a thickness of 1-3 μm; chemical mechanical polishing to remove excess copper, polishing solution containing Si. The abrasive is an alkaline slurry, and the polishing pressure is 1-3 psi (pounds per square inch).
[0051] In one embodiment, the memory chip 200 is a conventional memory chip without embedded TSVs, and its memory cell array area is not occupied by TSVs. For example, it can be a DRAM (Dynamic Random Access Memory) chip, whose memory array remains intact without TSV vias, thereby improving memory density and manufacturing yield. For example, the memory chip 200 is a 1αnm DRAM chip without embedded TSVs, with a memory cell array density of 0.1-0.2 Gb / mm². The chip thickness is reduced to 30-50 μm by back-side grinding, and the back-side pad 212 is made of aluminum-copper alloy (Al-0.5%Cu) with a thickness of 0.5-1 μm, and is connected to the silicon substrate through a titanium / titanium nitride adhesion layer.
[0052] In one embodiment, the TSV array adapter core 400 is made of silicon, glass, or an organic substrate, and the metal filling the TSV is copper, tungsten, or polysilicon. The silicon-based TSV array adapter core 400 can be manufactured using a TSV fabrication process compatible with CMOS technology to achieve high-density interconnects; glass-based or organic substrates are suitable for cost-sensitive applications or applications requiring larger sizes. For example, the TSV array adapter core 400 uses a silicon-based adapter with the following parameters: substrate thickness: 100 μm, TSV density: 100-1000 units / mm², TSV size: diameter 10 μm, aspect ratio 5:1 to 10:1, TSV insulating layer: 0.5 μm Si. Silica (PECVD deposition, temperature 300℃), TSV filler metal: electroplated copper (additives include accelerators, inhibitors and leveling agents).
[0053] Rewiring layers: 3-5 layers, line width / spacing 2μm / 2μm. The TSV array adapter core 400 uses a glass-based adapter, specifically with a thickness of 150μm. The TSV is formed by laser ablation or wet etching and filled with copper / tin composite metal. It is suitable for high-frequency applications (>10GHz) because the dielectric constant of glass (k=5-6) is lower than that of silicon (k=11.7).
[0054] In one embodiment, the memory chip is one or a combination of DRAM based on charge storage cells, NAND Flash (non-volatile memory) based on floating gate charge-type memory, RRAM (resistive random access memory) based on resistive cells, and MRAM (magnetic random access memory) based on magnetoresistive cells. Memory chips in different layers of a multilayer stack can be of the same or different memory types, achieving heterogeneous integration. In one embodiment, the memory chip 200 is a 3D NAND Flash chip with 128-256 stacked layers, and the peripheral circuitry is located below the memory array. The front I / O pads 211 of the memory chip are Al redistribution layer terminals with a pad spacing of 40 μm. They are interconnected to the lower layer via metal microbumps composed of Al (aluminum), with a diameter of 25 μm and a height of 15 μm.
[0055] In one embodiment, the package further includes a package that covers the memory device die stack and the TSV array adapter die 400, and exposes the back I / O pads 4002 of the TSV array adapter die. The package may be an epoxy molding compound, providing mechanical protection and a heat dissipation path.
[0056] In one embodiment, the metal microbumps are Al (aluminum) pillar bumps, tin-silver solder balls, or copper-tin hybrid bumps, with a height of 5-50 μm and a diameter of 10-100 μm, to achieve low-resistance, high-reliability interlayer interconnects.
[0057] The manufacturing method embodiments are described in detail below with reference to the accompanying drawings. Figure 5 This is a flowchart of a manufacturing method according to an embodiment of the present invention. Please refer to it. Figures 1 to 6 The manufacturing method of the three-dimensional stacked memory system chip based on independent TSV array adapter chips, such as... Figure 6 As shown, the steps include: S10: Provides a bottom substrate layer and prepares bottom substrate layer I / O pads on its upper surface.
[0058] like Figure 2 As shown, a bottom substrate layer 100 is provided, and bottom substrate layer I / O pads 2110 are prepared on its upper surface by physical vapor deposition, photolithography and etching processes. The material of the bottom substrate layer I / O pads 2110 is, for example, aluminum or copper. In this embodiment, it is a carrier wafer.
[0059] The following steps are performed: First, a through-silicon via (TSV) 601 is formed within the carrier wafer; then, a bottom substrate I / O pad 2110 is fabricated on its upper surface. In this embodiment, the bottom substrate 100 can be a silicon carrier wafer or a wafer containing logic circuitry. If it is a logic die wafer, its surface already has a multilayer interconnect structure and a bottom substrate I / O pad 2110. It should be noted that the steps of forming the TSV 601 and the external I / O pads 600 interconnected with the TSV can also be performed after the entire structure is formed, that is, after step S60.
[0060] S20: Fabricate multiple memory device chips, including a first-layer memory chip 2001, a second-layer memory chip 2002, and multiple TSV array adapter chips 400. The memory chip is a conventional chip without embedded through-silicon vias 601. Its front side has front I / O pads 211, and its back side has back I / O pads 212 to be fabricated. The TSV adapter chip 400 has an integrated TSV array 410 and also has the front I / O pads 4001 of the TSV array adapter chip.
[0061] S30: Perform the first layer stacking and bonding: the first layer memory device chip 2001 and the first layer TSV array adapter chip 400 are flip-bonded to the bottom substrate layer 100, so that the front I / O pads of each chip are perpendicular to the corresponding bottom substrate layer I / O pads 2110 on the bottom substrate layer.
[0062] like Figure 2 As shown, in this embodiment, the first layer stacking and bonding is performed: the first layer memory device chip 2001 and the first layer TSV array adapter chip 400 are flipped over and bonded to the bottom substrate layer 100 using bonding material 110; wherein, the bonding material 110 is located outside the pad area, such that the front I / O pads of each chip are perpendicularly opposite to the corresponding bottom substrate I / O pads 2110 on the bottom substrate layer, forming a first bonding cavity 310 therebetween. Layout configuration: Before bonding, according to the system design, the TSV array adapter chip 400 is positioned on the I / O pad side of the first layer memory device chip 2001. This embodiment adopts a symmetrical layout on both sides. Other embodiments may adopt a single-sided, three-sided, or four-sided layout.
[0063] Bonding operation: The first layer memory device chip 2001 and the first layer TSV array adapter chip 400 are flipped over and bonded to the bottom substrate layer 100 using bonding material 110.
[0064] The bonding material 110 is a dry film, such as polyimide (PI). In other embodiments, other bonding adhesives may be used. Specifically, in this embodiment, the bonding material 110 may be a dielectric material such as polyimide, benzocyclobutene, or silicon dioxide, formed by spin coating, deposition, and patterning to expose the bottom substrate I / O pads 2110. It should be noted that the I / O pads used for interconnection with the outside via TSVs in the bottom substrate may be covered.
[0065] The bonding material 110 is patterned using photolithography and etching processes to ensure that it is located outside the pad area, i.e., arranged around the I / O pads without covering the pad surface.
[0066] Cavity 310 is formed: After bonding, the front I / O pads 2120 of the first layer memory device chip 2001 are precisely perpendicular to the corresponding bottom substrate I / O pads 2110 on the bottom substrate layer 100; simultaneously, the front I / O pads 4001 of the TSV array adapter chip 400 of the first layer TSV array adapter chip 400 are also perpendicular to the corresponding I / O pads on the bottom substrate layer 100. Due to the support of the patterned bonding material 110, a first bonded cavity 310 is formed between each pair of perpendicularly opposite pads.
[0067] The memory device chip is a bare chip with front-end processing and back-end interconnection completed, and has aluminum or copper I / O pads on the front side. The TSV array adapter chip 400 forms TSV holes on the silicon substrate through deep reactive ion etching, fills them with copper or tungsten, and performs chemical mechanical polishing to form a redistribution layer and pads on the front side.
[0068] In other embodiments, metal bonding can also be performed directly between the vertically opposite front I / O pads and the bottom substrate I / O pads 2210, such as mixed metal bonding, ubump bonding, metal bonding, and solder ball bonding.
[0069] S40: Perform vertically opposite front I / O pads to bottom substrate I / O pads interconnect.
[0070] like Figure 3 As shown, in this embodiment, the first layer of metal microbumps 3001 is grown in situ: metal is selectively grown onto the surfaces of the vertically opposite front I / O pads and bottom substrate I / O pads 2110 through the first bonded cavity 310 or a channel communicating with it, until the grown metals are connected as one, forming the first metal microbumps 3001 connecting the upper and lower pads. The first layer of metal microbumps 3001 is grown in situ. A chemical plating solution is injected into the first bonded cavity 310 through a pre-designed microchannel or using the capillary channel of the bonding interface (as a channel communicating with the cavity 310). Metal ions (such as Cu) in the chemical plating solution... Divalent copper ions selectively undergo a catalytic reduction reaction on the surfaces of vertically opposite I / O pads, such as the front I / O pad 2120 and the bottom substrate I / O pad 2110 of the first layer memory device chip, depositing metal. The metal grows simultaneously outward from the surfaces of the two pads until they meet and connect in the middle of the cavity, thereby forming a first metal microbump 3001 and a corresponding metal microbump on the TSV side, forming an integrated structure connecting the upper and lower pads.
[0071] S50: A lateral interconnect 500 is formed on the back side of the first layer stacked structure to electrically interconnect the back side I / O pads of the first layer memory device chip and the back side I / O pads of the first layer TSV array adapter chip.
[0072] like Figure 3 As shown, lateral interconnects 500 are formed on the back side of the first-layer stacked structure. The back side of the bonded structure is thinned and chemically mechanically polished to achieve planarization. Through thin film deposition, photolithography, and etching processes, the back side I / O pads 212 of the first-layer memory device die and the back side I / O pads 4002 of the first-layer TSV array adapter die are fabricated. Lateral interconnects 500 are formed to electrically interconnect the back side I / O pads 212 of the first-layer memory device die and the back side I / O pads 4002 of the first-layer TSV array adapter die. In this embodiment, as... Figure 3 As shown, the back I / O pads 212 of the first-layer memory device chip, the back I / O pads 4002 of the first-layer TSV array adapter chip, and the lateral interconnects 500 are continuous metal interconnects formed in the same step. In other embodiments, they can also be formed layer by layer in different steps.
[0073] In this embodiment, the lateral interconnect 500 is a metal trace (specifically, a copper interconnect formed by a mosaic process) directly formed on the back side of the stacked structure using thin film deposition and photolithography. In other embodiments, silicon bridge bonding or redistribution layer processes may also be used.
[0074] Specifically, CMP can be used to thin the top surface of the structure formed after step S20, and then fill it with an insulating dielectric layer, such as silicon dioxide. Next, back-side I / O pads are formed, wherein the back-side I / O pads of the memory device chip are used only for lateral and TSV array adapter chip 400 interconnection, and are not interconnected with the internal layers of the underlying memory device chip. The back-side I / O pads of the TSV array adapter chip 400 are interconnected with the TSVs within the TSV array adapter chip.
[0075] S60: Perform Nth layer stacking, bonding and interconnection, where N≥2; like Figure 4As shown, in this embodiment, the specific steps include: flipping over the Nth layer memory device chip and the Nth layer TSV array adapter chip, for example, the second layer memory device chip 2002 and the second layer TSV array adapter chip 400, and bonding them to the back side of the (N-1)th layer stacked structure using bonding material 110; wherein, the bonding material 110 is located outside the pad area, such that the front I / O pad of the Nth layer chip is perpendicularly opposite to the back I / O pad of the corresponding chip in the (N-1)th layer, and forming the Nth bonded cavity 310 therebetween; Metal is selectively grown onto the vertically opposite pad surfaces through the Nth bonded cavity 310 or a channel connected thereto, until the grown metal is connected as one to form the Nth metal microbump connecting the upper and lower pads. Lateral interconnects 500 are formed on the back side of the Nth layer stacked structure to electrically interconnect the back side I / O pads of the Nth layer memory device chip and the back side I / O pads of the Nth layer TSV array adapter chip.
[0076] In other embodiments, the Nth layer memory device chip and the Nth layer TSV array adapter chip can be flip-bonded to the back side of the (N-1)th layer stacked structure, such that the front I / O pads of the Nth layer chip are perpendicularly opposite to the back I / O pads of the corresponding chip in the (N-1)th layer. Lateral interconnects are formed on the back side of the Nth layer stacked structure to electrically interconnect the back side I / O pads of the Nth layer memory device chip and the back side I / O pads of the Nth layer TSV array adapter chip.
[0077] S70: Repeat step S60 until the preset number of layers are stacked to obtain the three-dimensional stacked memory system chip; wherein, the TSV array adapter chip leads the signal to the external I / O pad 600 through its TSV array.
[0078] like Figure 4 , Figure 5 As shown, step S60 is repeated to stack subsequent first-layer memory device chips 2001, second-layer memory device chips 2002, etc., layer by layer. The front I / O pads of each layer of memory device chips are interconnected with the back I / O pads of the next layer through metal microbumps, and the I / O pads of each layer are connected to the corresponding pads of the TSV array adapter chip 400 through newly formed lateral interconnects 500. In this embodiment, the number of TSV arrays included in the TSV array adapter chip 400 corresponds to the number of layers of memory device chips to be stacked. In other words, each layer of memory device chips is laterally connected to a column of TSVs in the TSV array adapter chip, so each stacked layer of memory device chips occupies one column of TSVs.
[0079] Preferably, the memory chip is connected to the TSV array adapter chip vias 601 from bottom to top and from the inside to the outside, which can avoid the crossover of the lateral interconnects 500. For example, if three layers of memory chip are stacked, then two layers of TSV array adapter chips are needed. Each TSV array adapter chip contains two columns of TSVs. In the first layer of TSV array adapter chip 400, the first column of TSVs closest to the memory chip is interconnected upwards to the back I / O pads of the memory chip, and the second column of TSVs is interconnected upwards to the back I / O pads 211 of the memory chip of the upper layer of TSV array adapter chip. In the second layer of TSV array adapter chip 400, the first column of TSVs may not be interconnected, the second column of TSVs is interconnected upwards to the back I / O pads 211 of the memory chip, and the third column of TSVs is interconnected upwards to the back I / O pads 211 of the memory chip of the upper layer of TSV array adapter chip. Then, they are stacked upwards in sequence. The number of layers is not limited here and can be set according to actual needs.
[0080] In steps S40 and S60, the selective metal growth process is one or more combinations of electroplating, PVD (physical vapor deposition), CVD (chemical vapor deposition), or electroless plating.
[0081] It also includes the step of: drawing out a solder ball array from the TSV on the back side of the carrier wafer.
[0082] Specifically: such as Figure 5 As shown, the back side of the carrier wafer is thinned to expose the bottom end of the through-silicon via 601, as... Figure 1 As shown, a redistribution layer and solder balls are then fabricated to form a BGA or C4 solder ball array. For example, a TSV backside exposed process: Temporarily bonded to a glass substrate using benzocyclobutene (BCB) or wax as a temporary bonding agent; mechanically thinned to expose 5-10 μm of the TSV; dry etching to remove the TSV end insulating layer, using S... / Plasma etching of a mixture of sulfur hexafluoride and oxygen; deposition of UBM (under bump metallization) layer: sputtering of Ti (100nm) / Cu (300nm) / Ni (5μm) / Au (0.1μm); ball-forming process: printing tin-silver solder paste, 200μm in diameter, reflow to form solder balls.
[0083] In another embodiment, the external I / O pads 600 can also be formed by interconnecting the back side of the TSV array adapter core with the above structure, or by forming the external I / O pads 600 outward through the opening of the metal microbumps.
[0084] It also includes the steps of molding and cutting to complete the three-dimensional memory stacking packaging.
[0085] The entire stacked structure is covered with molding compound and then cut along the dicing track to form a single packaged memory system chip.
[0086] In one embodiment, the lateral interconnect 500 in step S40 is formed using electroplating, electroless plating, or physical vapor deposition. Electroplating copper can achieve interconnects with low resistance and high aspect ratio; electroless nickel-gold plating is suitable for temperature-sensitive applications; and physical vapor deposition of aluminum or tungsten can be used for fine-line interconnects.
[0087] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A three-dimensional stacked memory system chip based on independent TSV array adapter chips, characterized in that, include: The bottom substrate layer is either a carrier wafer or a logic chip wafer; Several layers of memory device chips are stacked upside down on the bottom substrate layer; At least one TSV array adapter chip is independently disposed on the side of the memory device chip stack layer, and a vertically penetrating TSV array is integrated inside it. They are stacked upside down on the bottom substrate layer. Among them, the front I / O pads of the first layer memory device chip are interconnected with the I / O pads of the bottom substrate layer, and the front I / O pads of the first layer TSV array adapter chip are interconnected with the I / O pads of the bottom substrate layer. Starting from the second layer, the front I / O pads of each memory device chip are interconnected with the back I / O pads of the adjacent memory device chip below it, and the front I / O pads of each TSV array adapter chip are interconnected with the back I / O pads of the adjacent TSV array adapter chip below it. Lateral interconnects located on the back of the memory device chip and the TSV array adapter chip interconnect the back I / O pads of the memory device chip and the TSV array adapter on the same layer. The TSV array adapter core chip leads the signal to the external I / O pads through its TSV array.
2. The three-dimensional stacked memory system chip based on independent TSV array adapter chips as described in claim 1, characterized in that, The bottom substrate layer has a TSV and external I / O pads interconnected with the TSV.
3. The three-dimensional stacked memory chip based on a TSV adapter as described in claim 1, characterized in that, The TSV array adapter core is disposed on the I / O pad side of the memory device, including one side, two sides, three sides, or four sides of the memory device.
4. The three-dimensional stacked memory system chip based on independent TSV array adapter chips as described in claim 1, characterized in that, When the bottom substrate layer is a logic chip wafer, its surface I / O pads are directly interconnected with the front I / O pads of the first layer memory device chip on it through metal microbumps.
5. The three-dimensional stacked memory system chip based on independent TSV array adapter chips as described in claim 1, characterized in that, The front I / O pads of the first layer memory device chip and the I / O pads of the bottom substrate layer, as well as the front I / O pads of the first layer TSV array adapter chip and the I / O pads of the bottom substrate layer, are all interconnected by a first interconnect metal. Starting from the second layer, the front I / O pads of each memory chip layer and the back I / O pads of the adjacent memory chip layer below it, as well as the front I / O pads of each TSV array adapter chip layer and the back I / O pads of the adjacent TSV array adapter chip layer below it, are interconnected by corresponding interconnect metals.
6. The three-dimensional stacked memory system chip based on independent TSV array adapter chips as described in claim 5, characterized in that, The interconnect metal is a hybrid bonding in-situ interconnect bonding metal.
7. The three-dimensional stacked memory system chip based on independent TSV array adapter chips as described in claim 1, characterized in that, The interconnecting metal consists of microbumps.
8. The three-dimensional stacked memory system chip based on independent TSV array adapter chips as described in claim 1, characterized in that, The interconnect metal is a metal-bonded in-situ interconnect metal.
9. The three-dimensional stacked memory system chip based on independent TSV array adapter chips as described in claim 5, characterized in that, The interconnecting metal is solder balls.
10. The three-dimensional stacked memory system chip based on independent TSV array adapter chips as described in claim 1, characterized in that, The lateral interconnects are embedded microstrip lines, silicon bridge interconnects, or metal traces formed by thin film deposition and photolithography.
11. The three-dimensional stacked memory system chip based on independent TSV array adapter chips as described in claim 1, characterized in that, The memory chip is a memory chip without embedded TSV, and its memory cell array area is not occupied by TSV.
12. The three-dimensional stacked memory system chip based on independent TSV array adapter chips as described in claim 1, characterized in that, The TSV array adapter core is made of silicon, glass, or an organic substrate, and the metal filled in the TSV is copper, tungsten, or polycrystalline silicon.
13. A method for manufacturing a three-dimensional stacked memory system chip based on independent TSV array adapter chips as described in any one of claims 1 to 12, characterized in that, Including the following steps: S10: Provide a bottom substrate layer and fabricate bottom substrate layer I / O pads on its upper surface; S20: Fabricate multiple memory device chips and multiple TSV array adapter chips; wherein, the memory device chip is a traditional memory device chip without embedded TSV, and front I / O pads and back I / O pads are fabricated on its front and back sides respectively; the TSV array adapter chip integrates a vertically penetrating TSV array, and front I / O pads are fabricated on its front side. S30: Perform the first layer stacking and bonding, and bond the first layer memory device chip and the first layer TSV array adapter chip to the bottom substrate layer inverted, so that the front I / O pads of each chip are perpendicular to the corresponding I / O pads on the bottom substrate layer. S40: Perform vertically opposite front I / O pads to bottom substrate I / O pads; S50: A lateral interconnect is formed on the back side of the first layer stacked structure to electrically interconnect the back side I / O pads of the first layer memory device chip and the back side I / O pads of the first layer TSV array adapter chip. S60: Perform Nth layer stacking, bonding and interconnection, where N≥2; S70: Repeat step S60 until the preset number of layers are stacked to obtain the three-dimensional stacked memory system chip; wherein, the TSV array adapter chip leads the signal to the external I / O pad through its TSV array.
14. The manufacturing method as described in claim 13, characterized in that, In step S40, the first layer of interconnect metal is grown in situ: metal is selectively grown on the surfaces of the vertically opposite front I / O pads and bottom substrate I / O pads through the first bonded cavity or the channel connected to it, until the grown metals are connected as one to form the first interconnect metal connecting the upper and lower pads.
15. The manufacturing method as described in claim 14, characterized in that, In step S30, the first layer stacking and bonding are performed: the first layer memory device chip and the first layer TSV array adapter chip are flipped upside down and bonded to the bottom substrate layer using bonding material; wherein, the bonding material is located outside the pad area, so that the front I / O pads of each chip are perpendicularly opposite to the corresponding I / O pads on the bottom substrate layer.
16. The manufacturing method as described in claim 13, characterized in that, The bottom substrate layer is a carrier wafer. In step S10, the method further includes forming a TSV in the carrier wafer and forming an external I / O pad interconnecting with the TSV on its lower surface.
17. The manufacturing method as described in claim 13, characterized in that, Step S60 includes: The Nth layer memory device chip and the Nth layer TSV array adapter chip are flip-bonded to the back side of the N-1 layer stacked structure; In this configuration, the front I / O pads of the Nth layer core are perpendicularly opposite to the back I / O pads of the corresponding N-1 layer core. Lateral interconnects are formed on the back side of the Nth layer stacked structure to electrically interconnect the back side I / O pads of the Nth layer memory device chip and the back side I / O pads of the Nth layer TSV array adapter chip.
18. The manufacturing method as described in claim 15, characterized in that, Step S60 includes: The Nth layer memory device chip and the Nth layer TSV array adapter chip are flipped upside down and bonded to the back side of the (N-1)th layer stack structure using bonding material; wherein the bonding material is located outside the pad area, such that the front I / O pad of the Nth layer chip is perpendicularly opposite to the back I / O pad of the corresponding chip in the (N-1)th layer, and an Nth bonded cavity is formed therebetween. Metal is selectively grown onto the vertically opposite pad surfaces through the Nth bonded cavity or the channel connected to it, until the grown metal is connected as one, forming the Nth metal microbump connecting the upper and lower pads. Lateral interconnects are formed on the back side of the Nth layer stacked structure to electrically interconnect the back side I / O pads of the Nth layer memory device chip and the back side I / O pads of the Nth layer TSV array adapter chip.
19. The manufacturing method as described in claim 13, characterized in that, In steps S40 and S60, the lateral interconnect is formed in one of the following ways: Metal traces are directly formed on the back side of the stacked structure using thin film deposition and photolithography. A silicon bridge containing an embedded microstrip line is fabricated and bonded to the back of the stacked structure to interconnect the corresponding pads; The metal traces are formed using a redistribution layer process.
20. The manufacturing method as described in claim 13, characterized in that, In steps S30 and S50, the TSV array adapter chip is configured on the I / O pad side of the memory device chip, and its layout includes being located on one side, two sides, three sides, or four sides of the memory device.
21. The manufacturing method as described in claim 18, characterized in that, The bonding material is a dry film or a bonding adhesive.
22. The manufacturing method as described in claim 18, characterized in that, In steps S40 and S60, the selective metal growth process is one or more combinations of electroplating, PVD, CVD, or electroless plating.