Heterogeneous cascade control laser equipment control system

Abstract

The invention discloses a laser equipment control system for heterogeneous cascade control. The laser equipment control system comprises an upper computer, a master station module and at least one slave station module, the slave station module comprises a slave station chip, a slave station FPGA and a slave station processor. The master station module and the slave station chip establish communication connection based on an EtherCAT protocol; the slave station chip is connected with the slave station FPGA through a high-speed parallel interface, and the slave station processor is connected with the slave station FPGA; the system comprises a cascade working mode and an independent working mode. And the slave station processor receives a control instruction of the upper computer, transmits the control instruction to the slave station FPGA, controls the working state of the laser equipment, collects state information and transmits the state information back to the upper computer. The high-speed parallel interface between the slave station chip and the slave station FPGA replaces a traditional serial interface, the data transmission rate is greatly improved, the high-real-time control requirement is met, the two modes are flexibly switched, multiple slave station modules do not need to be forcibly configured, and the application flexibility and expansibility are improved.

Description

Technical Field

[0001] This application relates to the field of laser control, specifically to a heterogeneous cascaded control system for laser equipment. Background Technology

[0002] In fields such as laser processing and laser synthesis, the synchronization accuracy, expansion flexibility, and monitoring convenience of laser control systems directly affect processing quality and application scope. Currently, ultra-high-speed communication buses such as RS485, CAN, Profinet, and EtherCAT are widely used in laser control systems to achieve communication and control between the main control unit and peripheral devices. Among them, the EtherCAT bus, due to its high real-time performance and high synchronization, is adopted by many laser control systems. For example, the bus-type laser control system based on the EtherCAT bus proposed in patent CN113540954B uses an ultra-high-speed communication bus to achieve interaction between the main control module and multiple slave control modules, improving the synchronization and real-time performance of light output.

[0003] However, this system, and the type of EtherCAT-based laser control system it represents, still suffers from several technical shortcomings: First, the system lacks web server functionality, making it impossible to conveniently monitor and control the laser modules via a webpage, resulting in insufficient operational flexibility; second, the use of serial communication interfaces between slave control units leads to slow data transmission speeds, making it difficult to meet the demands of high real-time control; third, power calibration relies on software, resulting in low calibration efficiency; and fourth, it only supports a pure cascaded operating mode, requiring at least two slave control modules and one master control module to operate normally, thus limiting the independent operation of individual slave control modules and restricting application scenarios with insufficient flexibility. These shortcomings make it difficult for existing laser control systems to meet the growing demands for high-precision, multi-scenario applications in terms of monitoring convenience, communication efficiency, and application scalability. Summary of the Invention

[0004] In view of this, the present invention proposes a heterogeneous cascaded control system for laser equipment, comprising: a host computer, a master station module, and at least one slave station module; The slave module includes a slave chip, a slave FPGA, and a slave processor; The master station module and the slave station chip establish a communication connection based on the EtherCAT protocol for transmitting control commands and status information. The slave chip is connected to the slave FPGA via a high-speed parallel interface, and the slave processor is connected to the slave FPGA; The system includes a cascaded working mode and an independent working mode. In the cascaded working mode, the master station module communicates with at least one of the slave station modules through a host computer. In the independent working mode, the host computer communicates directly with at least one of the slave station modules. During communication, the slave processor receives control commands from the host computer and transmits them to the slave FPGA to control the working status of the laser equipment and collect status information to send back to the host computer.

[0005] According to a preferred embodiment, the host computer is used to issue control commands, which include laser device power adjustment commands, modulation frequency adjustment commands, and duty cycle adjustment commands. The host computer is also used to acquire the status information of the laser equipment, including the laser equipment's operating voltage, operating current, photodiode detection data, and fault alarm data.

[0006] Furthermore, the master station module includes an Ethernet protocol stack, an EtherCAT master station protocol stack, a control command parsing module, and a status information parsing module; The Ethernet protocol stack is used to establish a communication connection with the host computer. The EtherCAT master protocol stack is used to establish a communication connection with the slave chip. The control command parsing module is used to parse the control commands issued by the host computer and forward the parsed control commands to the EtherCAT master station protocol stack. The status information parsing module is used to parse the status information fed back by the slave chip and send the parsed status information to the host computer through the Ethernet protocol stack.

[0007] Furthermore, the slave processor integrates a web server. In the cascaded working mode, the master station module receives control commands from the host computer and controls and monitors the slave station modules by accessing the web server; In the independent working mode, the host computer directly accesses the web server to issue control commands to control and monitor the slave module.

[0008] Furthermore, the slave processor also includes a unified monitoring module, a configuration information storage module, a power calibration module, and a real-time clock module; The unified monitoring module establishes a connection with the slave FPGA via an on-chip bus, and is used to read and write the laser device status information received by the slave FPGA; The configuration information storage module is used to store power calibration data and product configuration information; The power calibration module is used to read the power calibration data in the configuration information storage module, calculate the power compensation value, and write the power compensation value into the slave FPGA; The real-time clock module is used to provide the time information required for system operation.

[0009] Furthermore, the high-speed parallel interface has a processor control mode and an FPGA control mode; During the system power-on initialization phase, the high-speed parallel interface is in the processor control mode, and the slave chip is controlled by the slave processor to complete the initialization. After initialization, the high-speed parallel interface switches to the FPGA control mode, and the slave FPGA directly reads and writes the data of the slave chip.

[0010] According to a preferred embodiment, the slave chip is equipped with a dual-port RAM. Both the slave processor and the slave FPGA read and write the dual-port RAM through the high-speed parallel interface to achieve interactive data transmission with the master module. Furthermore, the slave processor and the slave FPGA can also read and write the registers of the slave chip through the high-speed parallel interface.

[0011] Furthermore, the slave chip is equipped with two network interfaces, PHY0 and PHY1, and the data transmission between the master module and the slave chip includes a forward path and a return path; The forward path includes: When there is only one slave module, the data frame sent by the master module enters through the receiving port of PHY0 of the slave chip. The slave chip writes control commands to the dual-port RAM and reads the status information of the laser device. After the data frame is processed, it is sent back to the master module through the sending port of PHY1. When there is more than one slave module, the data frame sent by the master module enters through the receiving port of the first slave chip's PHY0, and is then transmitted through the sending port of PHY1 to the receiving port of the next slave chip's PHY0, and so on, until it is passed to the last slave module and processed. The return path includes: When there is only one slave module, the data frame processed by the slave chip is directly transmitted back to the master module through the sending port of PHY0; When there is more than one slave module, the data frame processed by the last slave chip is transmitted through the sending port of PHY0 to the receiving port of PHY1 of the second to last slave chip, and then sequentially transmitted back to the first slave chip, and then transmitted back to the master module through the sending port of PHY0 of the first slave chip.

[0012] Furthermore, the slave chip is provided with a distributed clock synchronization unit. In the cascaded working mode, the master station module designates the slave chip of the first slave module as the reference clock source; the master station module sends a broadcast frame for reading the system time. When the broadcast frame is transmitted along the forward path, the distributed clock synchronization unit of each slave chip stamps a local timestamp. When the broadcast frame is transmitted along the return path, the distributed clock synchronization unit of each slave chip stamps a local timestamp again; the master station module calculates the delay of each slave chip relative to the reference clock source according to the difference between the two timestamps, and performs clock compensation on the corresponding slave chip based on the delay, so that the clocks of all slave chips are kept synchronized and a unified synchronization signal is generated. Wherein, the forward path refers to the propagation path from the master station module to the slave module, and the return path refers to the propagation path from the slave module to the master station module.

[0013] Furthermore, in the independent working mode, the upper computer issues control instructions to the slave processor through the web server of the slave processor, and the slave processor transmits the control instructions to the slave FPGA through the on-chip bus; the slave FPGA controls the working state of the laser execution component according to the control instructions, and collects the state information of the execution component and feeds it back to the slave processor, and the slave processor transmits the state information back to the upper computer through the web server.

[0014] The heterogeneous cascaded control laser device control system of the present invention is based on the EtherCAT protocol communication between the master station module and the slave chip, replaces the traditional serial interface with a high-speed parallel interface between the slave chip and the slave FPGA, greatly improves the data transmission rate, meets the high real-time control requirements, and at the same time cooperates with the collaborative architecture of the slave FPGA and the slave processor to ensure the efficient issuance of control instructions and the rapid feedback of device state information, improving communication efficiency and monitoring convenience. An independent working mode is added, and the upper computer can directly communicate with a single slave module to realize the independent operation of a single slave module. The cascaded mode retains the multi-module cooperation ability. The two modes can be flexibly switched without forced configuration of multiple slave modules, expanding multi-scenarios such as single-module application and multi-module linkage, and improving application flexibility and scalability. Considering the high synchronization advantage of the EtherCAT protocol and the high-speed characteristics of the parallel interface, while ensuring control accuracy, it optimizes communication efficiency, scenario adaptability and monitoring experience, and can meet the requirements of high-precision and multi-scenario laser processing and synthesis. Description of the Drawings

[0015] Figure 1 is a schematic diagram of a heterogeneous cascaded control laser device control system of the present invention; Figure 2This is a diagram illustrating the communication implementation of a master station module according to the present invention; Figure 3 This is a schematic diagram illustrating the functions of a host computer in accordance with the present invention; Figure 4 This is a diagram illustrating a slave processor communication implementation according to the present invention; Figure 5 This is a diagram illustrating a slave chip communication implementation of the present invention; Figure 6 This is a diagram illustrating a slave FPGA communication implementation of the present invention; Detailed Implementation In fields such as laser processing and laser synthesis, the synchronization accuracy, expansion flexibility, and monitoring convenience of laser control systems directly affect processing quality and application scope. Currently, ultra-high-speed communication buses such as RS485, CAN, Profinet, and EtherCAT are widely used in laser control systems to achieve communication and control between the main control unit and peripheral devices. Among them, the EtherCAT bus, due to its high real-time performance and high synchronization, is adopted by many laser control systems. For example, the bus-type laser control system based on the EtherCAT bus proposed in patent CN113540954B uses an ultra-high-speed communication bus to achieve interaction between the main control module and multiple slave control modules, improving the synchronization and real-time performance of light output.

[0016] However, this type of laser control system, and the one it represents, based on EtherCAT, still suffers from some technical shortcomings: It uses a serial communication interface, resulting in slow data transmission speeds that struggle to meet the demands of high real-time control; it only supports a pure cascaded operating mode, requiring at least two slave control modules and one master control module to function properly, thus limiting the independent operation of a single slave control module, restricting application scenarios, and compromising flexibility. These shortcomings make it difficult for existing laser control systems to meet the growing demands for high-precision, multi-scenario applications in terms of monitoring convenience, communication efficiency, and application scalability.

[0017] In view of this, the present invention proposes a laser equipment control system with heterogeneous cascade control.

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0019] In the following description, certain specific details are set forth for the purpose of illustrating various disclosed embodiments in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that embodiments may be practiced without one or more of these specific details. In other instances, well-known apparatuses, structures, and techniques associated with this application may not have been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0020] Unless the context requires otherwise, throughout the specification and claims, the word “comprising” and its variations, such as “including” and “having”, shall be understood to have an open, inclusive meaning, that is, to be interpreted as “including, but not limited to”.

[0021] The embodiments of this application will be described in detail below with reference to the accompanying drawings to provide a clearer understanding of the purpose, features, and advantages of this application. It should be understood that the embodiments shown in the drawings are not intended to limit the scope of this application, but are merely for illustrating the essential spirit of the technical solution of this application.

[0022] Throughout this specification, references to "an embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, the appearance of "in an embodiment" or "an embodiment" in various places throughout the specification does not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic may be combined in any manner in one or more embodiments.

[0023] This invention proposes a heterogeneous cascaded control system for laser devices, such as... Figure 1 As shown, it includes: a host computer, a master station module, and at least one slave station module; The slave module includes a slave chip, a slave FPGA, and a slave processor; The master station module and the slave station chip establish a communication connection based on the EtherCAT protocol for transmitting control commands and status information. The slave chip is connected to the slave FPGA via a high-speed parallel interface, and the slave processor is connected to the slave FPGA; The system includes a cascaded working mode and an independent working mode. In the cascaded working mode, the master station module communicates with at least one of the slave station modules through a host computer. In the independent working mode, the host computer communicates directly with at least one of the slave station modules. During communication, the slave processor receives control commands from the host computer and transmits them to the slave FPGA to control the working status of the laser equipment and collect status information to send back to the host computer.

[0024] In this invention, process data can be transmitted using a parallel bus.

[0025] The control system of the laser device with heterogeneous cascade control of the present invention is based on the EtherCAT protocol communication between the master station module and the slave chip. By replacing the traditional serial interface with a high-speed parallel interface between the slave chip and the slave FPGA, the data transmission rate is greatly improved, meeting the high real-time control requirements. At the same time, in cooperation with the collaborative architecture of the slave FPGA and the slave processor, it ensures the efficient issuance of control instructions and the rapid feedback of device status information, improving communication efficiency and monitoring convenience. An independent working mode is added, and the host computer can directly communicate with a single slave module to achieve the independent operation of a single slave module. The cascade mode retains the multi-module collaborative ability. The two modes can be flexibly switched without forcibly configuring multiple slave modules, expanding multi-scenarios such as single-module application and multi-module linkage, and improving application flexibility and scalability. Taking into account the high synchronization advantage of the EtherCAT protocol and the high-speed characteristics of the parallel interface, while ensuring control accuracy, it optimizes communication efficiency, scenario adaptability and monitoring experience, and can meet the high-precision and multi-scenario laser processing and synthesis requirements.

[0026] The host computer undertakes the core functions of issuing control instructions and obtaining status information. Among them, the issued control instructions specifically cover the adjustment requirements of key parameters for the operation of the laser device, including laser device power adjustment instructions, modulation frequency adjustment instructions, and duty cycle adjustment instructions. The power adjustment instruction is used to accurately control the size of the laser output energy to adapt to different processing materials and processing accuracy requirements; the modulation frequency adjustment instruction is used to change the repetition frequency of the laser pulse to meet the rhythm control requirements of pulsed laser processing; the duty cycle adjustment instruction is used to adjust the ratio of the conduction duration of the laser pulse to further optimize the laser energy output efficiency.

[0027] The host computer also synchronously obtains various status information of the laser device to achieve comprehensive monitoring of the device operation status. The obtained status information includes the working voltage, working current, photodiode detection data and fault alarm data of the laser device. The working voltage and working current are used to monitor the power supply stability of the device to avoid affecting the processing quality due to abnormal power supply; the photodiode detection data is used to feedback the actual output intensity of the laser to achieve closed-loop calibration of the output power; the fault alarm data is used to timely capture faults such as device short circuit, overload, and optical path abnormality to ensure the safe operation of the system and improve monitoring convenience.

[0028] Furthermore, the master station module includes an Ethernet protocol stack, an EtherCAT master protocol stack, a control command parsing module and a status information parsing module; [[ID=K]] The Ethernet protocol stack is used to establish a communication connection with the host computer, The EtherCAT master protocol stack is used to establish a communication connection with the slave chip; The control command parsing module is used to parse the control commands issued by the host computer and forward the parsed control commands to the EtherCAT master station protocol stack. The status information parsing module is used to parse the status information fed back by the slave chip and send the parsed status information to the host computer through the Ethernet protocol stack.

[0029] In a specific embodiment, the communication implementation of the master station module in the cascaded working mode is as follows: Figure 2 As shown.

[0030] With clear division of labor and efficient collaboration among multiple modules, it is compatible with standard Ethernet and EtherCAT protocols, balancing the stability of long-distance communication with the real-time performance of short-distance transmission. The parsing module reduces communication failures and data redundancy, significantly improving the adaptability and data processing efficiency of the master station module, and providing reliable central support for the collaborative work of multiple slave stations.

[0031] The slave processor integrates a web server and can connect to the master module; This web server is a lightweight embedded server that does not require the installation of dedicated client software. It enables interaction between the host computer or master station module and the slave station module through a browser, simplifying the operation process.

[0032] In cascaded operation mode, after receiving control commands from the host computer, the master station module accesses the web server of the slave processor in each slave station module through the network. Based on the web interaction protocol, it realizes the issuance of control commands and the collection of status information, thereby remotely controlling and monitoring the slave station modules in real time, ensuring the consistency of the collaborative work of multiple slave station modules.

[0033] In independent working mode, the host computer does not need to go through the master station module as an intermediary. It can directly access the web server of the target slave module through the network, send control commands to the slave processor, and obtain the status information fed back by the slave module through the web server. This enables independent control and monitoring of a single slave module, further improving the system's ease of operation and flexibility in adapting to different scenarios.

[0034] Users can log in to a browser and access the web server via IP address (Internet Protocol address). From the web interface, they can issue control commands and obtain status information about the laser equipment, such as... Figure 3 As shown.

[0035] The slave processor also includes a unified monitoring module, a configuration information storage module, a power calibration module, and a real-time clock module; The unified monitoring module establishes a communication connection with the slave FPGA through the on-chip bus, which can quickly read and write the laser equipment status information received by the slave FPGA, realize real-time control of the laser equipment operation status, and ensure the timeliness of status data acquisition. The configuration information storage module is used to store power calibration data and product configuration information for a long time. The power calibration data consists of calibration parameters for different operating conditions of the laser equipment, and the product configuration information consists of the adaptation parameters between the slave module and the laser equipment. This avoids the need to recalibrate and configure every time the system is started, thus improving system startup efficiency. The power calibration module reads the power calibration data from the configuration information storage module, combines it with the actual laser output data collected by the slave FPGA, calculates the power compensation value, writes the compensation value into the slave FPGA, and adjusts the output power of the laser device through the slave FPGA to ensure the laser output accuracy. The real-time clock module is used to provide the accurate time information required for system operation, and to provide a reference for the timestamp marking of the timing execution status information of control commands, so as to ensure the accuracy of system timing control; Each module performs its own function while working together. Unified monitoring ensures data real-time performance, the storage module improves startup efficiency, the power calibration module enhances output accuracy, and the real-time clock module ensures accurate timing. All these measures comprehensively improve the control reliability, accuracy, and operating efficiency of the slave modules, thus empowering the overall system performance. In one specific embodiment, the communication implementation of the slave processor in cascaded operation mode is as follows: Figure 4 As shown.

[0036] Furthermore, the high-speed parallel interface has two operating modes: processor control mode and FPGA control mode. The two modes automatically switch according to the system operation stage, taking into account both initialization reliability and real-time operation.

[0037] During the system power-on initialization phase, the high-speed parallel interface is in processor control mode by default. The slave processor takes the lead in controlling the slave chip to complete the initialization operation, including protocol parameter configuration register initialization, communication link detection, and other tasks. The logic control capability of the slave processor can ensure the accuracy and integrity of the initialization process and avoid initialization failures. Once all initialization operations are complete, the system automatically switches the high-speed parallel interface to FPGA control mode, allowing the slave FPGA to directly read and write data from the slave chip without going through the slave processor. This reduces data transmission links and further improves the rate of control command issuance and status information feedback, adapting to the high real-time control requirements of laser equipment.

[0038] The adaptive mode switching mechanism balances the reliability of initialization with the high speed of operation, avoiding the problems of easy initialization errors and insufficient transmission rate in single mode. The parallel transmission characteristics are superimposed and the relay link is omitted, which significantly improves the data interaction rate and accurately matches the high real-time control requirements of laser equipment.

[0039] The slave chip is equipped with dual-port RAM, which is a random access memory with two independent access ports, supporting simultaneous read and write operations by two devices to avoid data access conflicts.

[0040] Both the slave processor and the slave FPGA read and write the dual-port RAM through the high-speed parallel interface to achieve interactive data transmission with the master module. Furthermore, the slave processor and the slave FPGA can also read and write the registers of the slave chip through the high-speed parallel interface.

[0041] The dual-port design solves the data access conflict problem, enables parallel access between the slave processor and the FPGA, improves the efficiency of internal data interaction, and supports direct read and write of registers, enhancing the control flexibility and adaptability of the slave module and providing hardware support for high-speed data transmission and precise control.

[0042] Furthermore, the slave chip is equipped with two network interfaces, PHY0 and PHY1, and the data transmission between the master module and the slave chip includes a forward path and a return path; The forward path includes: When there is only one slave module, the data frame sent by the master module enters through the receiving port of PHY0 of the slave chip. The slave chip writes control commands to the dual-port RAM and reads the status information of the laser device. After the data frame is processed, it is sent back to the master module through the sending port of PHY1. When there is more than one slave module, the data frame sent by the master module enters through the receiving port of the first slave chip's PHY0, and is then transmitted through the sending port of PHY1 to the receiving port of the next slave chip's PHY0, and so on, until it is passed to the last slave module and processed. The return path includes: When there is only one slave module, the data frame processed by the slave chip is directly transmitted back to the master module through the sending port of PHY0; When there is more than one slave module, the data frame processed by the last slave chip is transmitted through the sending port of PHY0 to the receiving port of PHY1 of the second to last slave chip, and then sequentially transmitted back to the first slave chip, and then transmitted back to the master module through the sending port of PHY0 of the first slave chip.

[0043] The dual PHY interface separates the forward and return paths of data, enabling orderly data transmission in both single-slave and multi-slave scenarios. The multi-slave serial mode does not require additional interface switching, adapting to cascading expansion requirements. At the same time, the data frame transmission path is fixed, reducing transmission latency and error probability, and ensuring the stability of data communication when multiple modules work together.

[0044] In one specific embodiment, the communication implementation of the slave chip is as follows: Figure 5 As shown, the slave chip uses a "flying read / write" method to process data frames, which means that when the data frame passes through the slave, control commands are written to the dual-port RAM in real time, and status information is read at the same time.

[0045] The slave chip is equipped with a distributed clock synchronization unit. In the cascaded operating mode, the master station module designates the first slave chip of the slave station module as the reference clock source. The master station module sends a system time broadcast frame. When the broadcast frame is transmitted along the forward path, the distributed clock synchronization unit of each slave chip adds a local timestamp. When the broadcast frame is transmitted along the return path, the distributed clock synchronization unit of each slave chip adds a local timestamp again. The master station module calculates the delay of each slave chip relative to the reference clock source based on the difference between the two timestamps, and performs clock compensation on the corresponding slave chip based on the delay, so that the clocks of all slave chips are synchronized and a unified synchronization signal is generated. The forward path refers to the propagation path from the master station module to the slave station module, and the return path refers to the propagation path from the slave station module to the master station module.

[0046] By employing a dual timestamp and delay compensation mechanism, high-precision synchronization of clocks across multiple slave stations is achieved. A unified synchronization signal ensures coordinated operation of multiple laser devices, effectively solving the processing error problem caused by clock deviation in traditional cascade systems and significantly improving processing accuracy and collaborative reliability in cascade mode.

[0047] The slave FPGA includes a parallel arbitration module, a process data processing module, a synchronization unit, and a central control module; The parallel arbitration module is used to switch the working mode of the high-speed parallel interface. The process data processing module is used to read and write interactive data in the dual-port RAM; The synchronization unit is used to receive the synchronization signal output by the distributed clock synchronization unit and control the operation of the master control module according to the synchronization signal; The main control module is used to control the actuator of the laser and collect the status data of the actuator.

[0048] In one specific embodiment, the slave FPGA function in cascaded operation mode is as follows: Figure 6 As shown.

[0049] In standalone mode, the host computer sends control commands to the slave processor via the slave processor's web server. The slave processor then transmits the control commands to the slave FPGA via its on-chip bus. The slave FPGA controls the working state of the laser actuator according to the control commands and collects the status information of the actuator, feeding it back to the slave processor. The slave processor then transmits the status information back to the host computer via the web server.

[0050] In stand-alone mode, the host computer does not need to access the EtherCAT master station. Users log in to a browser and access the web server provided by the slave processor via IP address (Internet Protocol address).

[0051] In standalone mode, the slave processor performs the following functions: First, similar to the cascaded mode, the unified monitoring module in the slave processor reads the laser status stored in the slave FPGA via the AXI controller's on-chip bus, and also writes it to the relevant configuration registers of the slave FPGA via the on-chip bus, allowing the slave FPGA to control the laser's on / off state, power, etc. Second, the slave processor continues to provide web server functionality, processing the acquired laser status information through the status information parsing module and transmitting it to the Ethernet interface for use by the host computer; it also receives control commands from the host computer, parses them through the control command parsing module, and then sends them to the slave FPGA via the on-chip bus. Third, similar to the cascaded mode, the configuration information storage module stores configuration information such as power calibration and product number in a non-volatile memory chip, and reads this configuration information from the non-volatile memory chip after power-on. Fourth, similar to the cascaded mode, it implements the power calibration algorithm, calculating the compensated value from several discrete compensation values ​​read from the non-volatile memory chip using a polynomial fitting algorithm, and then writing it to the power compensation register group of the slave FPGA via the on-chip bus. Fifth, similar to the cascaded working mode, the system time is read from the RTC chip via the real-time clock (RTC) driver for use by the entire system, and a software interface for modifying the RTC time is also provided.

[0052] In stand-alone mode, the slave FPGA module and the slave chip stop exchanging information.

[0053] The operation of the master control module of the slave FPGA is no longer affected by the synchronization signal provided by the slave chip, but runs in a loop.

[0054] The core component of the slave FPGA is the central control module. On one hand, it receives control signals from the slave processor and controls the laser pump source, laser resonator, power supply, and driver board via serial interfaces and switches. It can also initialize the power calibration register set. On the other hand, it can store laser monitoring information, fault reports, and high-speed acquisition values ​​in registers for the slave processor to read.

[0055] The solutions provided by the embodiments of this application have been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0056] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0057] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

Claims

1. A heterogeneous cascaded control system for laser equipment, characterized in that, include: A host computer, a master station module, and at least one slave station module; The slave module includes a slave chip, a slave FPGA, and a slave processor; The master station module and the slave station chip establish a communication connection based on the EtherCAT protocol for transmitting control commands and status information. The slave chip is connected to the slave FPGA via a high-speed parallel interface, and the slave processor is connected to the slave FPGA; The system includes a cascaded working mode and an independent working mode. In the cascaded working mode, the master station module communicates with at least one of the slave station modules through a host computer. In the independent working mode, the host computer communicates directly with at least one of the slave station modules. During communication, the slave processor receives control commands from the host computer and transmits them to the slave FPGA to control the working status of the laser equipment and collect status information to send back to the host computer.

2. The heterogeneous cascaded control system for laser equipment according to claim 1, characterized in that, The host computer is used to issue control commands, which include laser equipment power adjustment commands, modulation frequency adjustment commands, and duty cycle adjustment commands. The host computer is also used to acquire the status information of the laser equipment, including the laser equipment's operating voltage, operating current, photodiode detection data, and fault alarm data.

3. The heterogeneous cascaded control system for laser equipment according to claim 1, characterized in that, The master station module includes an Ethernet protocol stack, an EtherCAT master station protocol stack, a control command parsing module, and a status information parsing module; The Ethernet protocol stack is used to establish a communication connection with the host computer. The EtherCAT master protocol stack is used to establish a communication connection with the slave chip. The control command parsing module is used to parse the control commands issued by the host computer and forward the parsed control commands to the EtherCAT master station protocol stack. The status information parsing module is used to parse the status information fed back by the slave chip and send the parsed status information to the host computer through the Ethernet protocol stack.

4. The heterogeneous cascaded control system for laser equipment according to claim 1, characterized in that, The slave processor integrates a web server. In the cascaded working mode, the master station module receives control commands from the host computer and controls and monitors the slave station modules by accessing the web server; In the independent working mode, the host computer directly accesses the web server to issue control commands to control and monitor the slave module.

5. The heterogeneous cascaded control system for laser equipment according to claim 4, characterized in that, The slave processor also includes a unified monitoring module, a configuration information storage module, a power calibration module, and a real-time clock module; The unified monitoring module establishes a connection with the slave FPGA via an on-chip bus, and is used to read and write the laser device status information received by the slave FPGA; The configuration information storage module is used to store power calibration data and product configuration information; The power calibration module is used to read the power calibration data in the configuration information storage module, calculate the power compensation value, and write the power compensation value into the slave FPGA; The real-time clock module is used to provide the time information required for system operation.

6. The heterogeneous cascaded control system for laser equipment according to claim 1, characterized in that, The high-speed parallel interface has both processor control mode and FPGA control mode; During the system power-on initialization phase, the high-speed parallel interface is in the processor control mode, and the slave chip is controlled by the slave processor to complete the initialization. After initialization, the high-speed parallel interface switches to the FPGA control mode, whereby the slave FPGA directly reads and writes the data of the slave chip.

7. The heterogeneous cascaded control system for laser equipment according to claim 6, characterized in that, The slave chip is equipped with dual-port RAM. Both the slave processor and the slave FPGA read and write the dual-port RAM through the high-speed parallel interface to achieve interactive data transmission with the master module. Furthermore, the slave processor and the slave FPGA can also read and write the registers of the slave chip through the high-speed parallel interface.

8. The heterogeneous cascaded control system for laser equipment according to claim 7, characterized in that, The slave chip has two network interfaces, PHY0 and PHY1. The data transmission between the master module and the slave chip includes a forward path and a return path. The forward path includes: When there is only one slave module, the data frame sent by the master module enters through the receiving port of PHY0 of the slave chip. The slave chip writes control commands to the dual-port RAM and reads the status information of the laser device. After the data frame is processed, it is sent back to the master module through the sending port of PHY1. When there is more than one slave module, the data frame sent by the master module enters through the receiving port of the first slave chip's PHY0, and is then transmitted through the sending port of PHY1 to the receiving port of the next slave chip's PHY0, and so on, until it is passed to the last slave module and processed. The return path includes: When there is only one slave module, the data frame processed by the slave chip is directly transmitted back to the master module through the sending port of PHY0; When there is more than one slave module, the data frame processed by the last slave chip is transmitted through the sending port of PHY0 to the receiving port of PHY1 of the second to last slave chip, and then sequentially transmitted back to the first slave chip, and then transmitted back to the master module through the sending port of PHY0 of the first slave chip.

9. The heterogeneous cascaded control system for laser equipment according to claim 1, characterized in that, The slave chip is equipped with a distributed clock synchronization unit. In the cascaded working mode, the master station module designates the slave chip of the first slave station module as the reference clock source; the master station module sends a broadcast frame to read the system time. When the broadcast frame is transmitted along the forward path, the distributed clock synchronization unit of each slave chip adds a local timestamp. When the broadcast frame is transmitted along the return path, the distributed clock synchronization unit of each slave chip adds a local timestamp again. The master station module calculates the delay of each slave chip relative to the reference clock source based on the difference between the two timestamps, and performs clock compensation on the corresponding slave chip based on the delay, so that the clocks of all slave chips are synchronized and a unified synchronization signal is generated. The forward path refers to the propagation path from the master station module to the slave station module, and the return path refers to the propagation path from the slave station module to the master station module.

10. The heterogeneous cascaded control system for laser equipment according to claim 1, characterized in that, In the independent working mode, the host computer sends control commands to the slave processor through the web server of the slave processor, and the slave processor transmits the control commands to the slave FPGA via the on-chip bus; The slave FPGA controls the working state of the laser actuator according to the control command, and collects the status information of the actuator and feeds it back to the slave processor. The slave processor then transmits the status information back to the host computer through the web server.

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