Method for forming low-k dielectric materials with reduced dielectric constant and high mechanical strength

Abstract

An example semiconductor processing method may include providing a first silicon-containing precursor and a second silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The first silicon-containing precursor may include a Si-O bond. The method may include forming a plasma of the first silicon-containing precursor and the second silicon-containing precursor in the processing region. The method may include forming a silicon-containing material layer on the substrate. The silicon-containing material layer may be characterized by a dielectric constant of less than or about 3.0.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 238,107, filed August 25, 2023, entitled “METHODS FOR FORMING LOW-K DIELECTRIC MATERIALS WITH REDUCED DIELECTRIC CONSTANT AND HIGH MECHANICAL STRENGTH”, which is incorporated herein by reference in its entirety.

[0002] This technology relates to deposition processes and chambers. More specifically, this technology relates to methods for forming low-κ materials. Background Technology

[0003] Integrated circuits can be fabricated by creating intricately patterned material layers on a substrate surface. The formation and removal of patterned material on a substrate requires controlled methods. Material properties can affect device operation and also influence how the film is removed relative to each other. Plasma-enhanced deposition can produce films with certain properties. To provide suitable properties, the formation of many films requires additional processing to adjust or enhance the film's material properties.

[0004] Therefore, there is a need for improved systems and methods for producing high-quality components and structures. This technology can meet these and other needs. Summary of the Invention

[0005] An exemplary semiconductor processing method may include providing a first silicon-containing precursor and a second silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The first silicon-containing precursor may include a Si-O bond. The method may include forming plasmas of the first and second silicon-containing precursors in the processing region. The method may also include forming a silicon-containing material layer on the substrate. The silicon-containing material layer may be characterized by a dielectric constant less than or about 3.0.

[0006] In some embodiments, the first silicon-containing precursor may be or may include: octamethylcyclotetrasiloxane, 2,4,6,8-tetramethyl-2,4,6,8-tetravinylcyclotetrasiloxane, 2,4,6,8-tetramethylcyclotetrasiloxane, dimethyldimethoxysilane, ethoxydimethylsilane, isobutylmethyldimethoxysilane, vinylmethyldimethoxysilane, 1,1,3,3-tetramethyl-1,3-dimethoxydisiloxane, 1,3-dimethyl-1,1,3 The precursor may be 3-tetramethoxydisiloxane, methoxy(dimethyl)silylmethane, methyl(dimethoxy)silylmethane, bis(trimethyl)methane, bis(methyldimethoxysilyl)methane, bis(dimethylmethoxysilyl)methane, 1,3-diethoxy-1,3-dimethyl-1,3-disilocyclobutane, 1,1,3,3-tetramethyl-1,3-disilocyclobutane, or 1,3-dimethyl-1,3-diphenyl-1,3-disilocyclobutane. The first silicon-containing precursor may be dimethyldimethoxysilane, and the second silicon-containing precursor may be 1,3-diethoxy-1,3-dimethyl-1,3-disilocyclobutane. The flow rate ratio of the first silicon-containing precursor to the second silicon-containing precursor may be greater than or about 1:1. The method may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber, along with the first and second silicon-containing precursors. When a silicon-containing material layer is formed on a substrate, the temperature within the semiconductor processing chamber can be maintained at less than or about 450 °C. When a silicon-containing material layer is formed on a substrate, the pressure within the semiconductor processing chamber can be maintained at less than or about 500 Torr. The silicon-containing material layer may be characterized by a hardness greater than or about 3.5 GPa. The silicon-containing material layer may be characterized by a dielectric constant less than or about 2.8. The method may include curing the silicon-containing material layer on the substrate by directing ultraviolet (UV) energy toward the substrate. Curing may include providing a helium-containing material, an argon-containing material, or both to a processing area of ​​the semiconductor processing chamber at a temperature between about 75 °C and about 400 °C and a pressure between about 3 Torr and about 100 Torr.

[0007] Some embodiments of this technology may cover semiconductor processing methods. The methods may include: providing a first silicon-containing precursor and a second silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The first silicon-containing precursor may include a Si-O bond. The methods may include: forming plasmas of the first and second silicon-containing precursors in the processing region. The methods may include: forming a silicon-containing material layer on the substrate. The silicon-containing material layer may be characterized by a dielectric constant less than or about 3.0. The methods may include: curing the silicon-containing material layer on the substrate by directing ultraviolet (UV) energy toward the substrate.

[0008] In some embodiments, the method may include: providing diatomic oxygen (O2) to a processing region of a semiconductor processing chamber along with a first silicon-containing precursor and a second silicon-containing precursor. The plasma containing the first and second silicon-containing precursors may be formed at less than or about 1,500 W. Curing the silicon-containing material layer on the substrate may include: directing a first UV energy toward the substrate for a first time period and directing a second UV energy toward the substrate for a second time period. The first and second UV energies may be characterized by different wavelengths. The methyl doping in the silicon-containing material layer on the substrate may be greater than or about 1.5%. The silicon-containing material layer may be characterized by a Young's modulus greater than or about 15.0 MPa.

[0009] Some embodiments of this technology may cover semiconductor processing methods. The methods may include: providing a first silicon-containing precursor and a second silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The first silicon-containing precursor may include a Si-O bond. The methods may include: forming plasmas of the first and second silicon-containing precursors in the processing region. The methods may include: forming a silicon-containing material layer on the substrate. The silicon-containing material layer may be characterized by a hardness greater than or about 3.5 GPa. The methods may include: hardening the silicon-containing material layer on the substrate by directing ultraviolet (UV) energy toward the substrate.

[0010] In some embodiments, the first silicon-containing precursor may be or may include: octamethylcyclotetrasiloxane, 2,4,6,8-tetramethyl-2,4,6,8-tetravinylcyclotetrasiloxane, 2,4,6,8-tetramethylcyclotetrasiloxane, dimethyldimethoxysilane, ethoxydimethylsilane, isobutylmethyldimethoxysilane, vinylmethyldimethoxysilane, 1,1,3,3-tetramethyl-1,3-dimethoxydisiloxane, 1,3-dimethyl-1,1,3 3-Tetramethoxydisiloxane, methoxy(dimethyl)silylmethane, methyl(dimethoxy)silylmethane, bis(trimethyl)methane, bis(methyldimethoxysilyl)methane, bis(dimethylmethoxysilyl)methane, 1,3-diethoxy-1,3-dimethyl-1,3-disilocyclobutane, 1,1,3,3-tetramethyl-1,3-disilocyclobutane, or 1,3-dimethyl-1,3-diphenyl-1,3-disilocyclobutane. The silicon-containing material layer is characterized by a dielectric constant less than or about 2.8. The silicon-containing material layer is characterized by a hardness greater than or about 4.5 GPa.

[0011] Such techniques offer numerous advantages over conventional systems and techniques. For example, the atomic structure of the material can be modified during deposition using silicon-containing precursors including Si-O bonds to increase Si-O-Si crosslinking and / or oxygen content in the deposited material. Furthermore, the increased Si-O-Si crosslinking and / or oxygen content in the deposited material can reduce the dielectric constant and improve the mechanical strength of the material. These and other embodiments, along with their numerous advantages and features, are described in more detail below with reference to the accompanying drawings. Attached Figure Description

[0012] The nature and advantages of the technology disclosed herein can be further understood by referring to the rest of the specification and the accompanying drawings.

[0013] Figure 1 Showing a top plan view of an exemplary processing system according to some embodiments of the present technology.

[0014] Figure 2 This shows a schematic cross-sectional view of an exemplary plasma system according to some embodiments of the present technology.

[0015] Figure 3 This illustrates the operation of exemplary methods for semiconductor processing according to some embodiments of the present technology.

[0016] Several figures are included schematically. It should be understood that these figures are for illustrative purposes only and should not be considered to be drawn to scale unless specifically stated otherwise. Furthermore, as schematic diagrams, these figures are intended to aid understanding and may not include all aspects or information compared to actual representations, and may include exaggerated material for illustrative purposes.

[0017] In the accompanying drawings, similar parts and / or features may have the same reference numerals. Furthermore, parts of the same class may be distinguished by adding a letter after the reference numeral (the letter distinguishing similar parts). If only the first reference numeral is used in the description, the description applies to any similar part having the same first reference numeral, regardless of the second symbol. Detailed Implementation

[0018] During back-end-of-line semiconductor processing, structures can be created to facilitate metallization, such as dual damascene structures. These structures can be produced through several processing steps utilizing a mask and a low-k film, which can be processed and removed. Removal can be achieved through chemical mechanical processes, which involve a certain amount of physical abrasion on the material to be removed. Low-k films are characterized by relatively low hardness and tensile modulus, which may limit their effectiveness during polishing, as the high shear stress during polishing can cause the low-k film to crack and lead to device failure. To improve hardness while maintaining a low k-value, many conventional techniques are forced to include additional processing steps, such as UV curing, to improve the film's hardness and / or density. These additional processes can significantly reduce yield and often require additional processing chambers on the tooling. Furthermore, these additional processes may not improve mechanical properties to meet desired specifications.

[0019] This technique overcomes these problems by providing deposited low-κ films characterized by reduced dielectric constant and improved mechanical strength. Additional Si-O-Si crosslinks and oxygen can be incorporated into the deposited material through deposition with specific precursors, such as silicon-containing precursors including Si-O bonds. The increased amount of Si-O-Si crosslinks and oxygen in the deposited material increases silicon and oxygen (Si-O) bonds within the film while maintaining the desired proportion of carbon to maintain a reduced dielectric constant. This overcomes the natural tendency for the dielectric constant to increase with, for example, Young's modulus and / or hardness, while also reducing the number of operations required during processing. Specifically, this technique eliminates the need for post-deposition processing (including UV exposure, plasma treatment, or other processing operations) to improve film density. However, post-deposition processing can still be performed to further reduce the dielectric constant and / or improve mechanical properties.

[0020] While the remainder of this disclosure will conventionally use the disclosed techniques to identify specific deposition processes, it will be readily understood that the systems and methods described are equally applicable to other deposition and cleaning chambers, and processes that may occur within said chambers. Therefore, the techniques should not be considered limited to use alone with these specific deposition processes or chambers. Before describing additional details of embodiments according to the present technology, this disclosure will discuss possible systems and chambers that can be used to perform deposition processes according to embodiments of the present technology.

[0021] Figure 1This figure shows a top plan view of one embodiment of a processing system 100 comprising deposition, etching, baking, and UV processing chambers according to an embodiment. In the figure, a pair of front-opening wafer transfer cassettes 102 supply substrates of various sizes, which are received by a robotic arm 104 and placed into a low-pressure holding area 106, and then placed into one of substrate processing chambers 108a to 108f, which are arranged in series blocks 109a to 109c. A second robotic arm 110 can be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a to 108f and back. Each substrate processing chamber 108a to 108f can be assembled to perform several substrate processing operations, including plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, UV processing, pre-cleaning, degassing, orientation, and other substrate processing (including annealing, ashing, etc.).

[0022] The substrate processing chambers 108a to 108f may include one or more system components for depositing, annealing, UV processing, and / or etching dielectrics or other materials on the substrate. In one configuration, two pairs of processing chambers, such as 108c and 108d and 108e and 108f, may be used to deposit dielectric materials onto the substrate, and a third pair of processing chambers, such as 108a and 108b, may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, such as 108a to 108f, may be configured to deposit alternating stacks of dielectric materials onto the substrate. Any one or more of the processes described herein may be performed in chambers separate from the manufacturing system, as shown in the various embodiments. It will be understood that other configurations for using system 100 as a chamber for dielectric material deposition, etching, annealing, and UV processing are also conceivable.

[0023] Figure 2 A schematic cross-sectional view of an exemplary plasma system 200 according to some embodiments of the present technology is shown. The plasma system 200 may illustrate a pair of processing chambers 108, which may be mounted in one or more tandem blocks 109 as described above, and may include a cover stack component according to embodiments of the present technology, further explained below. The plasma system 200 typically includes a chamber body 202 having sidewalls 212, a bottom wall 216, and an inner sidewall 201 defining a pair of processing regions 220A and 220B. The processing regions 220A to 220B may be configured in a similar manner, and each processing region 220A to 220B may include the same components.

[0024] For example, processing region 220B (whose components may also be included in processing region 220A) may include a stage 228 disposed in the processing region via a channel 222 formed in a bottom wall 216 in the plasma system 200. Stage 228 may provide a heater adapted to support a substrate 229 on an exposed surface (such as a body portion) of the stage. Stage 228 may include a heating element 232, such as a resistance heating element, which can heat and control the substrate temperature at a desired process temperature. Stage 228 may also be heated by a remote heating element such as a bulb assembly or any other heating element.

[0025] The main body of the pedestal 228 may be coupled to the shaft 226 by a flange 233. The shaft 226 may electrically couple the pedestal 228 to a power output or a power housing 203. The power housing 203 may include a drive system that controls the lifting and movement of the pedestal 228 within the processing area 220B. The shaft 226 may also include a power interface to provide power to the pedestal 228. The power housing 203 may also include interfaces for power and temperature indicators, such as thermocouple interfaces. The shaft 226 may include a base assembly 238 adapted for detachable coupling to the power housing 203. A surrounding ring 235 is shown above the power housing 203. In some embodiments, the surrounding ring 235 may be a shoulder adapted to serve as a mechanical stop, or a platform configured to provide a mechanical interface between the base assembly 238 and the upper surface of the power housing 203.

[0026] The system may include a rod 230 through a channel 224 formed in the bottom wall 216 of the processing area 220B, and the rod 230 may be used to position a substrate lifting rod 261 disposed on the main body of the platform 228. The substrate lifting rod 261 may selectively separate the substrate 229 from the platform to facilitate the exchange of the substrate 229 by a robot used to transport the substrate 229 into and out of the processing area 220B through the substrate transport port 260.

[0027] A chamber cover 204 may be coupled to the top portion of the chamber body 202. The cover 204 may accommodate one or more precursor distribution systems 208 coupled to the cover 204. The precursor distribution system 208 may include a precursor inlet channel 240 that delivers reactants and cleaning precursors into the processing area 220B via a dual-channel spray head 218. The dual-channel spray head 218 may include an annular base plate 248 having a barrier plate 244 disposed in the middle of a panel 246. A radio frequency (“RF”) source 265 may be coupled to the dual-channel spray head 218, and the RF source 265 may power the dual-channel spray head 218 to facilitate the generation of a plasma region between the panel 246 and the stage 228 of the dual-channel spray head 218. The dual-channel spray head 218 and / or panel 246 may include one or more openings to allow precursors to flow from the precursor distribution system 208 to processing areas 220A and / or 220B. In some embodiments, the openings may include at least one of straight-shaped and conical openings. In some embodiments, an RF source may be coupled to other parts of the chamber body 202, such as the pedestal 228, to facilitate plasma generation. A dielectric insulator 258 may be disposed between the cover 204 and the dual-channel spray head 218 to prevent RF power from being conducted to the cover 204. A shadow ring 206 may be disposed on the periphery of the pedestal 228 and coupled to the pedestal 228.

[0028] Optional cooling channels 247 may be formed in the annular base plate 248 of the precursor distribution system 208 to cool the annular base plate 248 during operation. Heat transfer fluids such as water, ethylene glycol, or gas may circulate through the cooling channels 247, allowing the base plate 248 to be maintained at a predetermined temperature. A liner assembly 227 may be disposed within the processing zone 220B adjacent to the sidewalls 201, 212 of the chamber body 202 to prevent the sidewalls 201, 212 from being exposed to the processing environment within the processing zone 220B. The liner assembly 227 may include a peripheral pumping chamber 225 coupled to a pumping system 264 configured to discharge gases and byproducts from the processing zone 220B and control the pressure within the processing zone 220B. Multiple discharge ports 231 may be formed on the liner assembly 227. The discharge port 231 can be configured to allow gas to flow from the treatment area 220B to the surrounding pumping chamber 225 in a manner that enhances the treatment within the system 200.

[0029] Figure 3This illustrates the operation of an exemplary method 300 for a semiconductor process according to some embodiments of the present technology. The method can be performed in various processing chambers, including the system 200 described above, as well as any other chambers in which plasma deposition can be performed. Method 300 may include several optional operations, which may or may not be specifically related to some embodiments of the method according to the present technology.

[0030] Method 300 may include a plasma-enhanced chemical vapor deposition (PECVD) process to form a deposited low-κ material. Method 300 may include operations as appropriate prior to the commencement of method 300, or method 300 may include additional operations following the deposition of the low-κ material. In embodiments, method 300, such as... Figure 3 As shown, the process may include: in operation 305, providing a deposition precursor to a processing region of a semiconductor processing chamber. While providing the deposition precursor to the chamber, a substrate may be accommodated within the processing region of the semiconductor processing chamber. In operation 310, a plasma effluent of the deposition precursor may be formed. In operation 315, a silicon-containing material layer may be deposited on the substrate. In an embodiment, in operation 320, depending on the circumstances, the silicon-containing material layer may be exposed to ultraviolet (UV) light.

[0031] In some embodiments, the deposition precursor may include a first silicon-containing precursor and a second silicon-containing precursor. The silicon-containing precursors that can be used may be, or may include, but are not limited to: octamethylcyclotetrasiloxane, 2,4,6,8-tetramethyl-2,4,6,8-tetravinylcyclotetrasiloxane, 2,4,6,8-tetramethylcyclotetrasiloxane, dimethyldimethoxysilane, ethoxydimethylsilane, isobutylmethyldimethoxysilane, vinylmethyldimethoxysilane, 1,1,3,3-tetramethyl-1,3-dimethoxydisiloxane, 1,3-dimethyl-1,1,3, 3-Tetramethoxydisiloxane, methoxy(dimethyl)silylmethane, methyl(dimethoxy)silylmethane, bis(trimethyl)methane, bis(methyldimethoxysilyl)methane, bis(dimethylmethoxysilyl)methane, 1,3-diethoxy-1,3-dimethyl-1,3-disilocyclobutane, 1,1,3,3-tetramethyl-1,3-disilocyclobutane, or 1,3-dimethyl-1,3-diphenyl-1,3-disilocyclobutane. In embodiments, at least one of the silicon-containing precursors, such as the first silicon-containing precursor, may include a Si-O bond. For example, the first silicon-containing precursor may be dimethyldimethoxysilane, ethoxydimethylsilane, isobutylmethyldimethoxysilane, or vinylmethyldimethoxysilane. In one exemplary embodiment, the first silicon-containing precursor may be dimethyldimethoxysilane, and the second silicon-containing precursor may be 1,3-diethoxy-1,3-dimethyl-1,3-disilocyclobutane.

[0032] By utilizing at least one silicon-containing precursor including Si-O bonds, an increased oxygen content can be present in the plasma effluent to be incorporated into the deposited material. Furthermore, an increased amount of Si-O-Si crosslinks may be present in the deposited film. This results in an increased amount of oxygen in the deposited silicon-containing material layer. The increased amount of oxygen and Si-O bonds can decrease the dielectric constant of the material while also increasing its density. Furthermore, the silicon-containing precursor with Si-O bonds can provide a backbone for additional silicon-containing precursors (multiple types) to introduce branched and / or linear structures into the deposited material. The combination of the Si-O backbone with branched and / or linear structures can increase the microporosity of the deposited material. The increased microporosity can provide a reduced dielectric constant for the material.

[0033] The deposition precursor may further include an oxygen-containing precursor. Usable oxygen-containing precursors may include, but are not limited to, diatomic oxygen (O2), ozone (O3), nitrogen dioxide (NO2), nitrous oxide (N2O), and any other oxygen-containing precursors that can be used for the formation of silicon-containing materials. In embodiments, the flow rate ratio of the oxygen-containing precursor to the silicon-containing precursor may be maintained and / or adjusted to facilitate the formation of a low-κ material having both a low dielectric constant (κ value) and high oxygen incorporation. The deposition precursor may also include one or more carrier gases, such as helium, argon, and nitrogen (N2). Although one or more carrier gases may be transported with the deposition precursor, the carrier gas may be considered an inert gas that will not react to form part of the deposited material. One or more carrier gases may be transported with other deposition precursors to act as a diluent.

[0034] By utilizing silicon-containing precursors that include Si-O bonds, such as the specific precursors previously listed, an increased amount of Si-O-Si crosslinks can be incorporated into the deposited material. As discussed above, the increased Si-O-Si crosslinks and / or oxygen content can decrease the dielectric constant of the deposited material. Furthermore, the increased oxygen content can provide increased density of the deposited material, which can improve its mechanical strength. In conventional techniques (such as those where the deposited precursor does not include at least two silicon-containing precursors, and one of the precursors includes Si-O bonds), a trade-off may be necessary between dielectric constant and mechanical strength.

[0035] The combined flow rates of the silicon-containing precursors can be: greater than or about 50 mgm, greater than or about 60 mgm, greater than or about 70 mgm, greater than or about 80 mgm, greater than or about 90 mgm, greater than or about 100 mgm, greater than or about 125 mgm, greater than or about 150 mgm, greater than or about 175 mgm, greater than or about 200 mgm, greater than or about 250 mgm, greater than or about 300 mgm, greater than or about 350 mgm, greater than or about 500 mgm, greater than or about 750 mgm, greater than or about 1,000 mgm, greater than or about 1,250 mgm, greater than or about 1,500 mgm, greater than or about 1,750 mgm, greater than or about 2,000 mgm, greater than or about 2,500 mgm, greater than or about 3,000 mgm or greater.

[0036] The flow rate of the oxygen-containing precursor can be greater than or about 50 sccm, greater than or about 60 sccm, greater than or about 70 sccm, greater than or about 80 sccm, greater than or about 90 sccm, greater than or about 100 sccm, greater than or about 125 sccm, greater than or about 150 sccm, greater than or about 175 sccm, greater than or about 200 sccm, greater than or about 225 sccm, greater than or about 250 sccm, greater than or about 275 sccm, greater than or about 300 sccm, greater than or about 400 sccm, greater than or about 500 sccm, greater than or about 750 sccm, greater than or about 1,000 sccm, greater than or about 1,250 sccm, greater than or about 1,500 sccm or greater. The flow rate of the oxygen-containing precursor may also be: less than or about 2,500 sccm, less than or about 2,250 sccm, less than or about 2,000 sccm, less than or about 1,750 sccm, less than or about 1,250 sccm, less than or about 1,000 sccm or less.

[0037] The flow rates of one or more carrier gases may be: greater than or about 200 sccm, greater than or about 300 sccm, greater than or about 400 sccm, greater than or about 500 sccm, greater than or about 750 sccm, greater than or about 1,000 sccm, greater than or about 2,000 sccm, greater than or about 3,000 sccm, greater than or about 3,000 sccm, greater than or about 4,000 sccm, greater than or about 5,000 sccm or greater.

[0038] In this embodiment, the flow rate ratio of the first silicon-containing precursor to the second silicon-containing precursor can be greater than or about 1:1. A flow rate ratio greater than or about 1:1 can introduce sufficient Si-O bonds to form a Si-O-Si backbone. The reduced amount of the second silicon-containing precursor relative to the first silicon-containing precursor can provide branched and / or linear structures into the silicon-containing material to be deposited. Incorporating branched and / or linear structures into the silicon-containing material having a Si-O-Si backbone can provide increased microporosity in the silicon-containing material layer, which can reduce the dielectric constant. Therefore, the flow rate ratio of the first silicon-containing precursor to the second silicon-containing precursor can be greater than or about 1.5:1, and can be greater than or about 2:1, greater than or about 2.5:1, greater than or about 3:1, or greater.

[0039] Implementations of method 300 may include: in operation 310, forming a plasma effluent from a deposition precursor. The plasma effluent can be generated from the deposition precursor within a processing region, for example, by providing RF power to the panel to generate plasma within a processing region of a semiconductor processing chamber. In implementations, the plasma effluent can be formed at plasma power less than or about 2,000 W. At increased plasma power, such as greater than 2,000 W, increased decomposition of the silicon-containing precursor may occur, and oxygen may be extracted from the deposited material. Conversely, at plasma power less than or about 2,000 W, less decomposition may occur, and Si-O bonds may be retained in the deposited material. Therefore, plasma effluents can be formed at plasma powers of less than or about 1,750 W, less than or about 1,500 W, less than or about 1,400 W, less than or about 1,300 W, less than or about 1,200 W, less than or about 1,100 W, less than or about 1,000 W, less than or about 900 W, less than or about 800 W, less than or about 700 W, less than or about 600 W, less than or about 500 W, less than or about 400 W, less than or about 300 W, less than or about 200 W, or even less.

[0040] The deposition rate of the silicon-containing material layer can be greater than or about 500 nm / min, and can be greater than or about 525 nm / min, greater than or about 550 nm / min, greater than or about 575 nm / min, greater than or about 600 nm / min, greater than or about 625 nm / min, greater than or about 650 nm / min, greater than or about 675 nm / min, greater than or about 700 nm / min, greater than or about 725 nm / min, greater than or about 750 nm / min, greater than or about 775 nm / min, greater than or about 700 nm / min or greater.

[0041] Implementations of method 300 may include: in operation 315, depositing a silicon-containing material onto a substrate. As discussed above, the substrate may be present in a processing region of a semiconductor processing chamber, and the silicon-containing material may be formed from plasma effluent generated by deposition plasma also present in the processing region. During deposition, the processing region and therefore the substrate may be characterized by temperatures less than or about 600 °C, less than or about 580 °C, less than or about 560 °C, less than or about 540 °C, less than or about 520 °C, less than or about 500 °C, less than or about 480 °C, less than or about 460 °C, less than or about 440 °C, less than or about 420 °C, less than or about 400 °C, less than or about 380 °C, less than or about 360 °C, less than or about 340 °C, less than or about 320 °C, less than or about 300 °C, less than or about 280 °C, less than or about 260 °C, or lower. Furthermore, during deposition, the processing area and thus the substrate may be characterized by temperatures greater than or about 250 °C, greater than or about 275 °C, greater than or about 300 °C, greater than or about 325 °C, greater than or about 350 °C, greater than or about 375 °C, greater than or about 400 °C, greater than or about 425 °C, greater than or about 450 °C, greater than or about 475 °C, greater than or about 500 °C, or greater.

[0042] During method 300, the pressure in the semiconductor processing chamber during deposition can be greater than or about 1 tor, greater than or about 2 tor, greater than or about 3 tor, greater than or about 4 tor, greater than or about 5 tor, greater than or about 6 tor, greater than or about 7 tor, greater than or about 8 tor, greater than or about 9 tor, greater than or about 10 tor, greater than or about 15 tor, greater than or about 20 tor, greater than or about 50 tor, greater than or about 100 tor, greater than or about 250 tor, greater than or about 500 tor, or greater. Increased pressure can lead to an increased residence time of the deposition precursor, which allows for more reaction time and increases oxygen incorporation into the deposited material. In addition, during deposition, the pressure in the semiconductor processing chamber may be: less than or about 500 torts, less than or about 250 torts, less than or about 100 torts, less than or about 50 torts, less than or about 20 torts, less than or about 15 torts, less than or about 14 torts, less than or about 13 torts, less than or about 12 torts, less than or about 11 torts, less than or about 10 torts, less than or about 9 torts, less than or about 8 torts, less than or about 7 torts, less than or about 6 torts, less than or about 5 torts, less than or about 4 torts, less than or about 3 torts, less than or about 2 torts, less than or about 1 tort or less.

[0043] The oxygen content in the material can be controlled depending on the flow rate of the deposition precursor and / or processing conditions. For example, the oxygen content in the material can be greater than or about 20.0 atomic%, and can be greater than or about 21.0 atomic%, greater than or about 22.0 atomic%, greater than or about 23.0 atomic%, greater than or about 24.0 atomic%, greater than or about 25.0 atomic%, greater than or about 26.0 atomic%, greater than or about 27.0 atomic%, greater than or about 28.0 atomic%, greater than or about 29.0 atomic%, greater than or about 30.0 atomic%, greater than or about 31.0 atomic%, greater than or about 32.0 atomic%, greater than or about 33.0 atomic%, greater than or about 34.0 atomic%, greater than or about 35.0 atomic% or more. As the oxygen content increases, the density can increase due to the increased amount of Si-O bonds.

[0044] In this embodiment, the silicon-containing material layer may be characterized in that the leakage current at 5 MV / cm is less than or approximately 2E-08 A / cm. 2 The increased Si-O-Si crosslinking and / or oxygen content in the material can reduce leakage current and increase the breakdown voltage. In this embodiment, the leakage current at 5 MV / cm can be less than or about 1.9E-08 A / cm. 2 Less than or approximately 1.8E-08 A / cm 2 Less than or approximately 1.7E-08 A / cm 2 Less than or approximately 1.6E-08 A / cm 2 Less than or approximately 1.5E-08 A / cm 2 Less than or approximately 1.4E-08A / cm 2 Less than or approximately 1.3E-08 A / cm 2 Less than or about 1.2E-08 A / cm 2 Less than or about 1.1E-08 A / cm 2 Less than or approximately 1E-08 A / cm 2 Or smaller.

[0045] As explained above, the method of this technology includes embodiments utilizing deposition precursors and processing conditions for forming a low-κ material with a low dielectric constant. In an embodiment of method 300, the deposited low-κ material may be formed as a silicon-, oxygen-, and carbon-containing material having the following dielectric constants: less than or about 4.0, less than or about 3.8, less than or about 3.6, less than or about 3.2, less than or about 3.0, less than or about 2.98, less than or about 2.96, less than or about 2.94, less than or about 2.92, less than or about 2.9, less than or about 2.88, less than or about 2.86, less than or about 2.84, less than or about 2.82, less than or about 2.8, or less.

[0046] The dielectric constant is generally associated with the material properties of a film, with a lower dielectric constant resulting in a lower Young's modulus and / or hardness. However, by producing films according to some embodiments of the present technology, it is possible to maintain a hardness and modulus higher than that of conventional techniques capable of producing films with corresponding deposited dielectric constant values. For example, in some embodiments, the materials that can be produced by the present technology are characterized by a Young's modulus greater than or about 15.0 GPa, and the materials that can be produced by the present technology may be characterized by the following Young's moduli: greater than or about 15.5 GPa, greater than or about 16.0 GPa, greater than or about 16.5 GPa, greater than or about 17.0 GPa, greater than or about 17.5 GPa, greater than or about 18.0 GPa, greater than or about 18.5 GPa, greater than or about 19.0 GPa, greater than or about 19.5 GPa, greater than or about 20.0 GPa, or greater. Similarly, the materials produced by this technology are characterized by a hardness greater than or about 3.5 GPa, and may be characterized by the following hardnesses: greater than or about 3.6 GPa, greater than or about 3.7 GPa, greater than or about 3.8 GPa, greater than or about 3.9 GPa, greater than or about 4.0 GPa, greater than or about 4.1 GPa, greater than or about 4.2 GPa, greater than or about 4.3 GPa, greater than or about 4.4 GPa, greater than or about 4.5 GPa, greater than or about 4.6 GPa, greater than or about 4.7 GPa, greater than or about 4.8 GPa, greater than or about 4.9 GPa, greater than or about 5.0 GPa, or higher. Therefore, this technology can produce films characterized by a low dielectric constant while maintaining high Young's modulus and hardness properties.

[0047] The material properties resulting from embodiments of this technology may be related to the amount of methyl groups bound to the membrane, as well as the amount of non-methyl carbons (such as CH2 or CH bonded within the membrane) bound to the membrane. The treatment may release a certain amount of these materials, which may impart a certain porosity to the membrane, while retaining a certain amount of methyl groups, which may help reduce the dielectric constant of the resulting membrane. Retaining a higher amount of non-methyl carbon within the membrane may increase the dielectric constant to a value higher than those mentioned above. For example, in some embodiments, the deposited material produced according to the present technology is characterized by having a percentage of methyl or CH3 incorporated or retained in the film greater than or about 1.25%, and is characterized by having a percentage of methyl incorporated in the film greater than or about 1.5%, greater than or about 1.75%, greater than or about 2.0%, greater than or about 2.25%, greater than or about 2.5%, greater than or about 2.6%, greater than or about 2.7%, greater than or about 2.8%, greater than or about 2.9%, greater than or about 3.0%, greater than or about 3.1%, greater than or about 3.2%, greater than or about 3.3%, greater than or about 3.4%, greater than or about 3.5%, greater than or about 3.6%, greater than or about 3.7%, greater than or about 3.8%, greater than or about 3.9%, greater than or about 4.0%, or greater.

[0048] Furthermore, the percentage of CH2 and / or CH and / or Si-C-Si in the deposited material may be less than or about 3.0%, and may be less than or about 2.8%, less than or about 2.6%, less than or about 2.4%, less than or about 2.2%, less than or about 2.0%, less than or about 1.8%, less than or about 1.6%, less than or about 1.4%, less than or about 1.2%, less than or about 0.8%, less than or about 0.6%, less than or about 0.5%, less than or about 0.4%, less than or about 0.3%, or even less.

[0049] This technology includes embodiments utilizing deposition precursors and processing conditions that can also form low-κ materials with increased density. In an embodiment of method 300, the deposited low-κ material can be formed to have a density greater than or about 2.0 g / cm³. 3 Greater than or approximately 2.05 g / cm³ 3 Greater than or approximately 2.1 g / cm³ 3 Greater than or approximately 2.15 g / cm³ 3 Greater than or approximately 2.2 g / cm³ 3 Greater than or approximately 2.25 g / cm³ 3 Greater than or approximately 2.3 g / cm³ 3 Greater than or approximately 2.35 g / cm³ 3 Greater than or approximately 2.4 g / cm³ 3 Greater than or approximately 2.45 g / cm³ 3 Greater than or approximately 2.5 g / cm³3 Or larger silicon-containing materials.

[0050] Implementations of method 300 may further include: exposing the deposited silicon-containing material to ultraviolet (UV) light during operation 320, depending on the situation. In one embodiment, the UV treatment may be performed in a semiconductor processing chamber used for depositing low-κ material. However, it is also conceivable to transfer the substrate with the deposited low-κ material to another semiconductor processing chamber for the UV treatment operation. In one embodiment, the UV treatment at operation 320, depending on the situation, may expose the silicon-containing material layer to ultraviolet light to provide a hardened silicon-containing material layer. This treatment may produce a hardened low-κ material characterized by increased porosity and / or a lower dielectric constant (κ value) than the deposited material. In one embodiment, hardening may include: providing a helium-containing material, an argon-containing material, or both, to a processing area of ​​the semiconductor processing chamber at a temperature between about 75 °C and about 400 °C and a pressure between about 3 Torr and about 100 Torr.

[0051] In an embodiment, the silicon-containing material layer on the hardened substrate may include: directing a first UV energy toward the substrate for a first time period and directing a second UV energy toward the substrate for a second time period. The first and second UV energies may be characterized by different wavelengths. For example, one type of UV energy may be characterized by being predominantly UVA wavelength output, such as in the wavelength range of 315 nm to 400 nm. UV energy characterized by being predominantly UVA wavelength output can retain carbon in the deposited material while increasing the hardness of the deposited material. UV energy characterized by being predominantly UVA wavelength output can also facilitate leakage in the deposited material. Other UV energies may be characterized by enhanced emission at UVC wavelengths (such as from 200 nm to 280 nm) while also emitting light in the range of 315 nm to 500 nm. UV energy characterized by enhanced emission at UVC wavelengths can increase the microporosity of the deposited material, thereby reducing the dielectric constant. UV energy characterized by enhanced emission at UVC wavelengths can also induce Si-O-Si and Si-C-Si crosslinking in the deposited material, thereby improving mechanical strength.

[0052] In some embodiments, the deposited silicon-containing material can be deposited to thicknesses greater than or about 750 Å, greater than or about 800 Å, greater than or about 850 Å, greater than or about 900 Å, greater than or about 950 Å, greater than or about 1,000 Å, greater than or about 1,100 Å, greater than or about 1,200 Å, greater than or about 1,300 Å, or greater. The deposited silicon-containing material can be deposited in two or more deposition and UV processing cycles to complete the final UV-treated low-κ material. For example, the number of deposition and processing cycles can be greater than or about three cycles, greater than or about five cycles, greater than or about ten cycles, greater than or about 15 cycles, greater than or about 20 cycles, greater than or about 30 cycles, greater than or about 40 cycles, greater than or about 50 cycles, or more.

[0053] In the foregoing description, numerous details have been set forth for illustrative purposes to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art to which this application pertains that certain embodiments may be practiced without some of these details or with additional details.

[0054] Having disclosed several embodiments, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the art, several well-known processes and components have not been described. Therefore, the foregoing description should not be construed as limiting the scope of the art.

[0055] Where a range of values ​​is provided, unless otherwise expressly specified herein, it should be understood that each intermediate value between the upper and lower limits of that range is specifically disclosed, with precision to the least quantile of the lower limit unit. Any narrower range between any stated or unstated intermediate value within the stated range and any other stated or intermediate value within that stated range is also included. The upper and lower limits of such narrower ranges may be independently included in or excluded from the range, and each range in which any of the limits, no limit, or both limits are included is also covered by this technique, each range being governed by any specifically excluded limit within the stated range. Where a stated range includes one or both of these limits, it also includes ranges excluding one or both of the included limits.

[0056] As used herein and in the appended claims, unless expressly specified otherwise, the singular forms “a”, “an”, and “the” include plural references. Thus, for example, reference to “a layer” includes multiple such layers, and reference to “the precursor” includes reference to one or more precursors and equivalents known to a person skilled in the art to which this application pertains, etc.

[0057] Furthermore, when the terms “comprise,” “comprising,” “contain,” “include,” and “including” are used in this specification and in the claims below, they are intended to specify the presence of a stated feature, integer, component, or operation, but such terms do not preclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A semiconductor processing method, the semiconductor processing method comprising: A first silicon-containing precursor and a second silicon-containing precursor are provided to a processing region of a semiconductor processing chamber, wherein a substrate is disposed in the processing region of the semiconductor processing chamber, and wherein the first silicon-containing precursor comprises a Si-O bond. Plasma forming the first silicon-containing precursor and the second silicon-containing precursor in the processing region; and A silicon-containing material layer is formed on the substrate, wherein the silicon-containing material layer is characterized by a dielectric constant of less than or about 3.

0.

2. The semiconductor processing method of claim 1, wherein the first silicon-containing precursor comprises octamethylcyclotetrasiloxane, 2,4,6,8-tetramethyl-2,4,6,8-tetravinylcyclotetrasiloxane, 2,4,6,8-tetramethylcyclotetrasiloxane, dimethyldimethoxysilane, ethoxydimethylsilane, isobutylmethyldimethoxysilane, vinylmethyldimethoxysilane, 1,1,3,3-tetramethyl-1,3-dimethoxydisiloxane, 1,3-dimethyl-1 1,3,3-Tetramethoxydisiloxane, methoxy(dimethyl)silylmethane, methyl(dimethoxy)silylmethane, bis(trimethsilyl)methane, bis(methyldimethoxysilyl)methane, bis(dimethylmethoxysilyl)methane, 1,3-diethoxy-1,3-dimethyl-1,3-disilocyclobutane, 1,1,3,3-tetramethyl-1,3-disilocyclobutane, or 1,3-dimethyl-1,3-diphenyl-1,3-disilocyclobutane.

3. The semiconductor processing method according to claim 1, wherein the first silicon-containing precursor is dimethyldimethoxysilane, and the second silicon-containing precursor is 1,3-diethoxy-1,3-dimethyl-1,3-disilocyclobutane.

4. The semiconductor processing method of claim 1, wherein the flow rate ratio of the first silicon-containing precursor to the second silicon-containing precursor is greater than or about 1:

1.

5. The semiconductor processing method of claim 1, further comprising: Along with the first silicon-containing precursor and the second silicon-containing precursor, an oxygen-containing precursor is provided to the processing region of the semiconductor processing chamber.

6. The semiconductor processing method of claim 1, wherein while forming the silicon-containing material layer on the substrate, the temperature inside the semiconductor processing chamber is maintained at less than or about 450 °C.

7. The semiconductor processing method of claim 1, wherein while forming the silicon-containing material layer on the substrate, the pressure within the semiconductor processing chamber is maintained at less than or about 500 Torr.

8. The semiconductor processing method of claim 1, wherein the silicon-containing material layer is characterized by a hardness greater than or about 3.5 GPa.

9. The semiconductor processing method of claim 1, wherein the silicon-containing material layer is characterized by a dielectric constant of less than or about 2.

8.

10. The semiconductor processing method of claim 1, further comprising: The silicon-containing material layer on the substrate is hardened by directing ultraviolet (UV) energy to the substrate.

11. The semiconductor processing method of claim 10, wherein the hardening comprises: providing a helium-containing material, an argon-containing material, or both to the processing region of the semiconductor processing chamber at a temperature between about 75 °C and about 400 °C and a pressure between about 3 torts and about 100 torts.

12. A semiconductor processing method, the semiconductor processing method comprising: A first silicon-containing precursor and a second silicon-containing precursor are provided to a processing region of a semiconductor processing chamber, wherein a substrate is disposed in the processing region of the semiconductor processing chamber, and wherein the first silicon-containing precursor comprises a Si-O bond. Plasma forming the first silicon-containing precursor and the second silicon-containing precursor in the processing region; A silicon-containing material layer is formed on the substrate, wherein the silicon-containing material layer is characterized by a dielectric constant of less than or about 3.0; and The silicon-containing material layer on the substrate is hardened by directing ultraviolet (UV) energy to the substrate.

13. The semiconductor processing method of claim 12, further comprising: Along with the first silicon-containing precursor and the second silicon-containing precursor, diatomic oxygen (O2) is provided to the processing region of the semiconductor processing chamber.

14. The semiconductor processing method of claim 12, wherein the plasma that forms the first silicon-containing precursor and the second silicon-containing precursor is at less than or about 1,500 W.

15. The semiconductor processing method of claim 12, wherein hardening the silicon-containing material layer on the substrate comprises: directing a first UV energy to the substrate for a first time period and directing a second UV energy to the substrate for a second time period, wherein the first UV energy and the second UV energy are characterized by different wavelengths.

16. The semiconductor processing method of claim 12, wherein the methyl incorporation in the silicon-containing material layer on the substrate is greater than or about 1.5%.

17. The semiconductor processing method of claim 12, wherein the silicon-containing material layer is characterized by a Young's modulus greater than or about 15.0 MPa.

18. A semiconductor processing method, the semiconductor processing method comprising: A first silicon-containing precursor and a second silicon-containing precursor are provided to a processing region of a semiconductor processing chamber, wherein a substrate is disposed in the processing region of the semiconductor processing chamber, and wherein the first silicon-containing precursor comprises a Si-O bond. Plasma forming the first silicon-containing precursor and the second silicon-containing precursor in the processing region; A silicon-containing material layer is formed on the substrate, wherein the silicon-containing material layer is characterized by a hardness greater than or about 3.5 GPa; and The silicon-containing material layer on the substrate is hardened by directing ultraviolet (UV) energy to the substrate.

19. The semiconductor processing method of claim 18, wherein the first silicon-containing precursor comprises octamethylcyclotetrasiloxane, 2,4,6,8-tetramethyl-2,4,6,8-tetravinylcyclotetrasiloxane, 2,4,6,8-tetramethylcyclotetrasiloxane, dimethyldimethoxysilane, ethoxydimethylsilane, isobutylmethyldimethoxysilane, vinylmethyldimethoxysilane, 1,1,3,3-tetramethyl-1,3-dimethoxydisiloxane, 1,3-dimethyl- 1,1,3,3-Tetramethoxydisiloxane, methoxy(dimethyl)silylmethane, methyl(dimethoxy)silylmethane, bis(trimethyl)methane, bis(methyldimethoxysilyl)methane, bis(dimethylmethoxysilyl)methane, 1,3-diethoxy-1,3-dimethyl-1,3-disilocyclobutane, 1,1,3,3-tetramethyl-1,3-disilocyclobutane, or 1,3-dimethyl-1,3-diphenyl-1,3-disilocyclobutane.

20. The semiconductor processing method of claim 18, wherein the silicon-containing material layer is characterized by a dielectric constant of less than or about 2.8, and wherein the silicon-containing material layer is characterized by a hardness of greater than or about 4.5 GPa.

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