Management method and device of all-flash array power protection memory and storage medium
By dividing the power-saving memory of the all-flash array into multiple zones and adopting a redundancy protection mechanism, the problems of memory leakage and system availability in traditional memory management schemes are solved, achieving efficient and flexible memory management and fault recovery.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUGON INFORMATION IND
- Filing Date
- 2025-12-19
- Publication Date
- 2026-05-08
AI Technical Summary
In traditional all-flash array storage systems, the memory management scheme lacks effective redundancy protection, resulting in memory leaks, high maintenance difficulty, high interaction costs, and difficulty in ensuring high system availability in the event of controller failure or abnormal power loss.
The power-saving memory of each controller is divided into multiple intervals, including the memory root object and the memory management module. Through the division of the object description area and the data object area and the redundancy protection mechanism, the memory management is efficient and flexible, and critical information is synchronized, verified and recovered in the event of a failure.
It improves the processing efficiency and scalability of all-flash arrays, ensures no data loss in the event of failure, reduces maintenance costs and interaction complexity, and improves system availability.
Smart Images
Figure CN121996155A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory management, and more specifically to a management method, apparatus and storage medium for a power-saving all-flash array memory. Background Technology
[0002] In all-flash array storage systems, two or four controllers are typically configured. The memory of each controller is primarily used to store critical data structures and cached logs during system operation. To improve system reliability, related technologies employ a memory segment multi-copy mechanism, synchronously writing data mirrors to other controllers. Once data is stored in memory, it is considered persistent. When a controller fails, the data in the power-saving memory can be persisted to disk using power from a backup power module. After the system regains power, the data is restored from the disk to the power-saving memory, thus restoring the system to its pre-failure state and ensuring no data loss.
[0003] In an all-flash array software system, the memory requirements of each user are random, including parameters such as the controller where the memory resides, the number of replicas, and the amount of memory needed. Therefore, it is necessary to partition and manage the memory on each controller in a unified manner to store system data at different stages, and at the same time, provide multi-replica memory segment management services to ensure that memory segments can be efficiently rotated during system operation.
[0004] However, traditional controller memory management schemes have many drawbacks: On the one hand, the memory of traditional controllers is managed uniformly by the operating system, and memory users need to perform memory allocation, reading, writing, and release operations themselves. Moreover, the memory of different controllers is relatively independent, lacking effective redundancy protection measures. Since the number of business module processes in the all-flash array software system is large and distributed across different controllers, both controllers and processes may encounter various failure scenarios, which can easily lead to memory leaks and is not conducive to the long-term stable operation of the entire system. At the same time, the architecture of independent memory management by each module also increases the difficulty of software maintenance, not only increasing maintenance costs but also resulting in excessively high interaction costs between modules.
[0005] On the other hand, in traditional solutions, memory allocation, release, read and write operations all rely on interfaces provided by the operating system, and garbage collection is also mainly handled by the operating system. However, actual business scenarios are more complex. All-flash arrays are typically equipped with a backup power module, whose core function is to provide short-term power supply when the controller fails, ensuring that the system completes unfinished tasks before the power outage. At this time, the memory stores the entry information that boots the operating system, various data structures of each module during operation, and customer data that has not been written to disk. This data needs to be persisted to the backup hard drive in sequence within a short period of time. When the controller power is restored, each software module in the array needs to restore its original memory layout to ensure that the array returns to its state before the power outage. However, traditional memory management methods that rely on the operating system typically allocate memory across the entire memory pool, making it impossible to uniformly classify and manage various types of data, and failing to provide redundancy protection with multiple controllers and multiple replicas. In the face of extreme scenarios such as controller failure and abnormal power outages, it is difficult to guarantee the high availability of the all-flash array storage system. Summary of the Invention
[0006] The purpose of this invention is to provide a management method, device, and storage medium for power-saving memory of an all-flash array, which improves the processing efficiency of the all-flash array.
[0007] To achieve the above objectives, embodiments of the present invention provide a method for managing the power-saving memory of an all-flash array, wherein the all-flash array includes multiple controllers, and the method includes: A power-saving memory space is set for each controller. The power-saving memory space includes a memory root object and a memory management module. The memory root object is used to store the controller's startup initialization information and configuration information. The memory management module includes an object description area, a data root object area, and a data object area. The data root object area and the data object area are each divided into at least one memory segment, and each memory segment corresponds to a physical memory address. The data root object area includes a valid bitmap for recording the validity of the controller. The object description area is used to store the description information of the memory segments in the data root object area and the data object area, and each object description corresponds to one memory segment; The all-flash array is adjusted according to the working state of the controller.
[0008] Optionally, adjusting the all-flash array according to the operating state of the controller includes: When all controllers are in normal working condition, key information is synchronously written to the data root object area of the corresponding controller, and the valid bitmap of the corresponding controller is in a valid state. When a controller acts as the master controller of the all-flash array, grant that controller permission to modify the object description area of all other controllers. When all controllers fail simultaneously, the marked states of the valid bitmaps in the data root object area are all invalid, and the all-flash array is in an incompatible state.
[0009] Optionally, the step of adjusting the all-flash array according to the operating state of the controller further includes: When any controller restarts after a failure, the failed controller initiates a critical information read request to other valid controllers in the cluster. The critical information includes data root object area metadata, object mapping relationships, and transaction logs. The effective controller transmits the key information to the faulty controller via a high-speed data synchronization channel in a combination of incremental synchronization and verification. The fault controller uses a double hash check algorithm to verify the integrity of key information, and at the same time uses a hierarchical index reconstruction mechanism to restore the object index and complete the alignment construction of the root object area of the full data.
[0010] Optionally, the alignment construction includes: The memory management module counts the memory segments within the expansion area and sends a set of memory unit IDs to the memory proxy module. The memory proxy module then downgrades the memory units in the set of memory unit IDs. The memory management module polls the memory segments of each controller expansion area to release empty memory units, and then aligns the empty memory units.
[0011] Optionally, the management method may also include: Each controller stores the object description area of other controllers, and the object description areas are isolated from each other through a hardware-level memory isolation mechanism. The memory isolation mechanism adopts dual protection of page table-level access control and hardware access monitoring. When the memory management module is migrated, each controller uses incremental copy and description area mapping redirection technology to copy the valid area related to memory management in the object description area of the former master controller to the object description area of the new master controller. After the copy is completed, the new master controller marks the object description area of the former master controller as historical read-only, while the object description area of the new master controller is marked as writable.
[0012] Optionally, the description information of each memory segment in the object description area includes at least: the region identifier to which the memory segment belongs, the physical memory start address corresponding to the memory segment, the usage status of the memory segment, and the capacity information of the memory segment; The region identifier of the memory segment includes the memory unit ID, verification information, status, reserved identifier, and number of replicas.
[0013] Optionally, the data object area includes all memory segments that can be allocated to business modules for each controller and a memory segment occupancy bitmap. The memory segment occupancy bitmap is used to record the usage of all memory segments in the current controller.
[0014] Optionally, the management method may also include: Adjust the number of memory segments and the size of each memory segment in the data root object area according to user needs.
[0015] On the other hand, this application also proposes a management device for power-saving memory of an all-flash array, wherein the all-flash array includes multiple controllers, and the device includes: The first processing module is used to set up a power-saving memory space for each controller. The power-saving memory space includes a memory root object and a memory management module. The memory root object is used to store the controller's startup initialization information and configuration information. The memory management module includes an object description area, a data root object area, and a data object area. The second processing module is used to divide the data root object area and the data object area into at least one memory segment, each memory segment corresponding to a physical memory address. The data root object area includes a valid bitmap for recording the validity of the controller. The third processing module is used to store the description information of the data root object area and the memory segment in the data object area using the object description area, and each object description corresponds to a memory segment; The fourth processing module is used to adjust the all-flash array according to the working state of the controller.
[0016] On the other hand, this application also proposes a machine-readable storage medium storing instructions for causing a machine to execute the all-flash array power-saving memory management method described above.
[0017] This invention discloses a method for managing the power-saving memory of an all-flash array. The all-flash array includes multiple controllers. The method includes: setting a power-saving memory space for each controller, the power-saving memory space including a memory root object and a memory management module. The memory root object is used to store the controller's startup initialization information and configuration information. The memory management module includes an object description area, a data root object area, and a data object area. The data root object area and the data object area are each divided into at least one memory segment, each memory segment corresponding to a physical memory address. The data root object area includes a valid bitmap used to record the validity of the controller. The object description area is used to store the description information of the memory segments in the data root object area and the data object area, with each object description corresponding to one memory segment. The all-flash array is adjusted according to the working state of the controller. This method, by dividing the power-saving memory of each controller into multiple intervals with different data structures and replica configurations, caches key data at different stages of system operation, making memory management more efficient and flexible, unifying the memory call interface of business modules, and improving the scalability and processing efficiency of the all-flash array.
[0018] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description section. Attached Figure Description
[0019] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of a management method for a power-saving memory array of an all-flash array according to the present invention; Figure 2 This is a schematic diagram of the power-saving memory space division of the four-control array of the present invention; Figure 3 This is a schematic diagram of the root memory unit and memory unit copy structure of the present invention; Figure 4 This is a schematic diagram of the root memory unit expansion process of the present invention; Figure 5 This is a schematic diagram of a power-saving memory management device for an all-flash array according to the present invention.
[0020] Explanation of reference numerals in the attached figures Management device for 100-all-flash array power-saving memory; 200 - First Processing Module; 300 - Second processing module; 400 - Third Processing Module; 500 - Fourth processing module. Detailed Implementation
[0021] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.
[0022] It should be noted that the acquisition, transmission, storage, use, and processing of data in the technical solution of this application all comply with relevant laws and regulations. In the embodiments of this application, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that the applicant has already used or necessarily used such solutions.
[0023] Example 1 Figure 1 This is a schematic diagram of a management method for a power-saving memory array of the present invention, as shown below. Figure 1 As shown, the method includes: Step S101 involves setting up a power-saving memory space for each controller. The power-saving memory space includes a memory root object and a memory management module. The memory root object is used to store the controller's startup initialization information and configuration information. The memory management module includes an object description area, a data root object area, and a data object area.
[0024] In one specific implementation, the data object area includes all memory segments that can be allocated to business modules for each controller and a memory segment occupancy bitmap. The memory segment occupancy bitmap is used to record the usage of all memory segments in the current controller.
[0025] Specifically, such as Figure 2 As shown, each controller in the all-flash array has a power-saving memory space of the same size. Excluding the memory root object at the head, the remaining portion of this memory space is uniformly managed by the memory management module. The memory management module is divided into three regions in sequence: an object description area, a data root object area, and a data object area. The data root object area and the data object area are divided into memory segments of 1MB each, with each segment corresponding to a segment of physical memory address. The object description area stores the description information of all memory segments; each object description corresponds to one memory segment. The number of object description areas is the same as the number of controllers. When a controller acts as the master controller of the array's memSeg module (MemorySegment module), it modifies the object description area of the corresponding object.
[0026] This method divides the power-saving memory of each controller into multiple intervals, with different data structures and replica configurations for each interval, thus caching key data at different stages of system operation.
[0027] Step S102 involves dividing the data root object area and the data object area into at least one memory segment, with each memory segment corresponding to a physical memory address. The data root object area includes a valid bitmap used to record the validity of the controller.
[0028] According to a specific implementation, the description information of each memory segment in the object description area includes at least: the region identifier to which the memory segment belongs, the physical memory start address corresponding to the memory segment, the usage status of the memory segment, and the capacity information of the memory segment; the region identifier to which the memory segment belongs includes memory unit ID, verification information, status, reserved identifier, and number of replicas.
[0029] Specifically, each object description in the object description area corresponds to a memory segment, and the description information includes: memory unit ID, CRC check information, status, reserved identifier, number of replicas, and the controller to which it belongs. When the controller starts, the memory management agent scans the description area of the controller and reconstructs the layout of all data object areas.
[0030] The memory cell ID is a unique identifier for a memory cell, indicating the memory cell to which the memory segment belongs. The management of memory cell IDs follows certain constraints: the memory cell ID consists of two parts: a round number and a slot. The round number increments with system runtime, and the slot is used to identify a specific memory cell. Therefore, the combination of round number and slot ensures that all memory cell IDs provided to users are unique.
[0031] The state of a memory segment is maintained by the user of the memory unit it belongs to. Its possible values are: Invalid, sealed, free, and dirty. Invalid indicates that the memory is unused, but it's uncertain whether it can be reclaimed; sealed indicates read-only; free indicates pending release; and dirty indicates that read and write operations are allowed.
[0032] The reservation identifier indicates whether the memory unit to which the memory segment belongs is reserved. During normal system operation, the memory management module reserves a portion of memory unit resources. These memory units are only allocated to business applications during critical processes.
[0033] The reserved identifier indicates how many replicas of the memory cell exist. For the same memory cell, each controller in the array has at most one replica. The associated controller indicates the controller where the main logic service of the requester of the memory cell resides.
[0034] The data object area contains all memory segments that can be allocated to business modules for each controller, and they are managed uniformly on it. For each controller, a memory segment occupancy bitmap is maintained to record the usage of all memory segments in the current controller; at the same time, a memory unit occupancy bitmap is maintained to record the usage of all memory units. The index of the memory unit occupancy bitmap is the slot.
[0035] Step S103 involves using the object description area to store the description information of the memory segments in the data root object area and the data object area, with each object description corresponding to one memory segment.
[0036] In one specific implementation, each controller stores the object description areas of other controllers. These object description areas are isolated from each other. Only when a controller acts as the memory management master will it modify the corresponding area of its own controller within the object description area. When the memory management module master migrates, each controller only needs to copy the object description area of the former master to the object description area of the new master. This saves time spent clearing the old object description area, and modifications to the former master's object description area do not affect the new master.
[0037] This method divides the power-saving memory of each controller into multiple intervals, with different data structures and replica composition methods for each interval. It caches key data at different stages of system operation, making memory management more efficient and flexible, and making the memory call interface of business modules more unified.
[0038] Step S104 involves adjusting the all-flash array according to the operating state of the controller.
[0039] According to one specific implementation, the step of controlling the all-flash array based on the working state of the controller includes: when all controllers are in normal working state, key information is synchronously written into the data root object area of the corresponding controller, and the valid bitmap of the corresponding controller is in a valid state; when a controller acts as the master controller of the all-flash array, the controller is given the permission to modify the object description areas of all other controllers; when all controllers fail simultaneously, the marking states of the valid bitmaps in the data root object area are all invalid, and the all-flash array is in an incompatible state.
[0040] Specifically, each controller has a data root object area (rootmseg) of the same size, used to store key information for the business modules within each controller, supporting dynamic expansion. The data root object area consists of the same number of memory segments, collectively forming a batch of fully replicated memory units. Full replication means the number of replicas matches the number of controllers in the array. Figure 3As shown, the memory management module maintains a bitmap of the data root object area to record which controllers have valid data root object area content. When all controllers are in normal working condition, key information is synchronously written into the data root object area of each controller, and the corresponding controller is marked as valid. When a controller fails and restarts, it can read the key information from the data root object area of other valid controllers, ensuring that the controller that failed can start normally without data loss, i.e., data root object area alignment. If all controllers fail simultaneously, the valid bitmap of the data root object area will be 0, and the array will be in an over-redundant state, i.e., unavailable.
[0041] The step of regulating the all-flash array according to the working status of the controller further includes: when any controller restarts after a failure, the failed controller initiates a critical information read request to other valid controllers in the cluster. The critical information includes metadata of the data root object area, object mapping relationships, and transaction logs. The valid controllers transmit the critical information to the failed controller through a high-speed data synchronization channel in a combination of incremental synchronization and verification. The failed controller uses a double hash verification algorithm to verify the integrity of the critical information and simultaneously uses a hierarchical index reconstruction mechanism to restore the object index, completing the alignment and construction of the full data root object area.
[0042] The alignment process includes: the memory management module counts the memory segments within the expansion area and sends a set of memory unit IDs to the memory proxy module; the memory proxy module downgrades the memory units in the set of memory unit IDs; the memory management module polls the memory segments in each controller's expansion area to release empty memory units; and the memory management module aligns the empty memory units.
[0043] Specifically, the data root object area on the master controller is synchronized to the data root object areas of other controllers. First, the list of currently valid controllers needs to be determined, i.e., the bitmap of controllers to be aligned; then, the contents of the root memory units are read from the master controller's memory and stored in the cache; next, based on the bitmap of controllers to be aligned obtained earlier, the cache image is written to the root memory units of the corresponding controllers; finally, the valid root memory unit bitmap is updated and persisted to the critical disks of the array.
[0044] The management method further includes: each controller stores the object description area of other controllers, and each object description area is isolated from each other through a hardware-level memory isolation mechanism. The memory isolation mechanism adopts dual protection of page table-level access control and hardware access monitoring. When the memory management module is migrated, each controller uses incremental copy and description area mapping redirection technology to copy the effective area related to memory management in the object description area of the former master controller to the object description area of the new master controller. After the copy is completed, the new master controller marks the object description area of the former master controller as historical read-only, while the object description area of the new master controller is marked as writable.
[0045] The management method also includes adjusting the number of memory segments and the size of each memory segment in the data root object area according to user needs.
[0046] Specifically, the data root object area consists of several memory segments. Its space needs to be as small as possible, just enough to store critical information; otherwise, it will occupy too many memory segments within the data objects. Furthermore, the all-flash array hardware and software support expansion and updates, allowing the data root object area to be expanded according to actual space requirements. The process includes: collecting memory units to be emptied, broadcasting an emptying message, waiting for emptying, setting the occupied range, expanding the data root object area, and aligning the data root object area.
[0047] like Figure 4 As shown, when the data root object area space expands from m Mb to n Mb, the description area information of each controller maintained on the memory management module is traversed first to collect all memory segments located in the [m, n] interval. After deduplication, the corresponding set of memory unit IDs is obtained. Next, this set is broadcast to each controller's memory management agent. Then, the memory management agent sets the memory unit ID set received to TRUE, and the corresponding memory unit downgrade mark is set to TRUE. This operation requires semaphore locking to ensure non-reentrancy. At the same time, the starting number of memory segment allocation for this controller is set to n+1 to ensure that after the memory unit user releases the memory unit, the newly requested memory segment will not continue to be allocated to the memory segment in the [m, n] interval. Then, on the memory management master controller, the description area information is scanned. If all memory segments in the [m, n] interval have been released, it means that the emptying has been completed. Otherwise, the scan continues until the emptying is completed. Finally, the memory segments in the [m, n] interval are marked as root memory units and aligned according to the new root memory unit size. This completes the expansion operation.
[0048] The business modules also distinguish between master and slave. The business master can be on any controller, so it can send a request to the memory management module from any controller in the array to request a specific number of replica memory units. Upon receiving the request, the memory management module first generates a memory unit ID, finds an unused slot in the memory segment occupancy bitmap, and combines it with the current round to obtain the memory unit ID; then it determines the replica distribution, and the creation of memory units must include replicas of the controller where the business master resides. For an array with n controllers, if m replica memory units are requested, then there are a total of... The system iterates through each controller combination bitmap, checking if there are any free memory segments in the memory segment occupancy bitmap. If so, it retrieves and marks the segment as occupied. Otherwise, it continues to check the next bitmap. Once all controllers in the required bitmap have selected available memory segments, a memory unit with m copies is obtained, with the default state being dirty. Then, for all selected memory segments, the system modifies the configuration information in the object descriptor area of the corresponding controller, including the memory unit ID, state, and reserved flag. At the same time, the memory unit occupancy bitmap is persisted to the root memory unit. At this point, the memory unit is successfully created and can be returned to the applicant for read and write operations.
[0049] When a service sends a request to the memory management module to release a memory unit, the memory management module marks the corresponding memory unit as free and informs the service that the release is complete. The actual release action is performed by a periodic task in the background of the memory management module, which iterates through all memory units in the free state, releases each memory segment copy, modifies the memory segment occupancy bitmap, updates the descriptor area, and finally persists the memory unit occupancy bitmap to complete the release of the memory segment.
[0050] Example 2 Figure 5 This is a schematic diagram of a management device for a power-saving memory array of the present invention, as shown below. Figure 5 As shown, the all-flash array power-saving memory management device 100 includes a first processing module 200, used to set a power-saving memory space for each controller. The power-saving memory space includes a memory root object and a memory management module. The memory root object is used to store the controller's startup initialization information and configuration information. The memory management module includes an object description area, a data root object area, and a data object area. A second processing module 300 is used to divide the data root object area and the data object area into at least one memory segment. Each memory segment corresponds to a physical memory address. The data root object area includes a valid bitmap used to record the validity of the controller. A third processing module 400 is used to use the object description area to store the description information of the memory segments in the data root object area and the data object area, and each object description corresponds to one memory segment. A fourth processing module 500 is used to adjust the all-flash array according to the working status of the controller.
[0051] This device divides the power-saving memory of each controller into multiple zones, each with different data structures and replica configurations. It caches critical data at different stages of system operation, enabling more efficient and flexible memory management and a more unified memory access interface for business modules. Furthermore, the device supports simultaneous failures of multiple controllers in the array; as long as one controller has a persistent and valid root memory unit replica, the entire array can be restored to normal operation. Dynamic expansion of the root memory region during operation meets future storage needs after hardware expansion, improving software scalability. A multi-replica bitmap optimization mechanism ensures that every memory unit requested by a business application contains a replica of the corresponding controller, making read and write operations more efficient. Multiple replicas provide data redundancy protection, enabling the handling of more complex failure scenarios. A background recycling mechanism ensures rapid response during memory unit rotation for business modules, improving processing efficiency.
[0052] This invention discloses a method for managing the power-saving memory of an all-flash array. The all-flash array includes multiple controllers. The method includes: setting a power-saving memory space for each controller, the power-saving memory space including a memory root object and a memory management module. The memory root object is used to store the controller's startup initialization information and configuration information. The memory management module includes an object description area, a data root object area, and a data object area. The data root object area and the data object area are each divided into at least one memory segment, each memory segment corresponding to a physical memory address. The data root object area includes a valid bitmap used to record the validity of the controller. The object description area is used to store the description information of the memory segments in the data root object area and the data object area, with each object description corresponding to one memory segment. The all-flash array is adjusted according to the working state of the controller. This method, by dividing the power-saving memory of each controller into multiple intervals with different data structures and replica configurations, caches key data at different stages of system operation, making memory management more efficient and flexible, unifying the memory call interface of business modules, and improving the scalability and processing efficiency of the all-flash array.
[0053] The all-flash array power-saving memory management device 100 includes a processor and a memory. The first processing module 200, the second processing module 300, the third processing module 400, the fourth processing module 500, etc. are all stored in the memory as program units. The processor executes the program units stored in the memory to realize the corresponding functions.
[0054] The processor contains a core, which retrieves the corresponding program unit from memory. One or more cores can be configured; adjusting core parameters improves the scalability and processing efficiency of the all-flash array.
[0055] The memory may include non-permanent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.
[0056] This invention provides a storage medium storing a program that, when executed by a processor, implements a method for managing the power-saving memory of the all-flash array.
[0057] This invention provides a processor for running a program, wherein the program executes a method for managing the power-saving memory of the all-flash array.
[0058] This invention provides a device including a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, it performs the following steps: setting a power-saving memory space for each controller, the power-saving memory space including a memory root object and a memory management module. The memory root object stores the controller's startup initialization information and configuration information. The memory management module includes an object description area, a data root object area, and a data object area. The data root object area and the data object area are each divided into at least one memory segment, each memory segment corresponding to a physical memory address. The data root object area includes a valid bitmap used to record the validity of the controller. The object description area stores description information of the memory segments in the data root object area and the data object area, with each object description corresponding to one memory segment. The all-flash array is controlled according to the controller's operating state. The device described herein can be a server, PC, PAD, mobile phone, etc.
[0059] This application also provides a computer program product, which, when executed on a data processing device, is suitable for executing an initialization program with the following steps: setting up a power-saving memory space for each controller, the power-saving memory space including a memory root object and a memory management module, the memory root object being used to store the controller's startup initialization information and configuration information, the memory management module including an object description area, a data root object area, and a data object area; dividing the data root object area and the data object area into at least one memory segment, each memory segment corresponding to a physical memory address, the data root object area including a valid bitmap for recording the validity of the controller; using the object description area to store description information of the memory segments in the data root object area and the data object area, with each object description corresponding to one memory segment; and adjusting the all-flash array according to the controller's operating state.
[0060] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0061] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0062] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0063] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0064] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.
[0065] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.
[0066] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.
[0067] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0068] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.
Claims
1. A method for managing the power-saving memory of an all-flash array, wherein the all-flash array comprises multiple controllers, characterized in that, The method includes: A power-saving memory space is set for each controller. The power-saving memory space includes a memory root object and a memory management module. The memory root object is used to store the controller's startup initialization information and configuration information. The memory management module includes an object description area, a data root object area, and a data object area. The data root object area and the data object area are each divided into at least one memory segment, and each memory segment corresponds to a physical memory address. The data root object area includes a valid bitmap for recording the validity of the controller. The object description area is used to store the description information of the memory segments in the data root object area and the data object area, and each object description corresponds to one memory segment; The all-flash array is adjusted according to the working status of the controller.
2. The management method according to claim 1, characterized in that, The step of adjusting the all-flash array according to the operating state of the controller includes: When all controllers are in normal working condition, key information is synchronously written to the data root object area of the corresponding controller, and the valid bitmap of the corresponding controller is in a valid state. When a controller acts as the master controller of the all-flash array, grant that controller permission to modify the object description area of all other controllers. When all controllers fail simultaneously, the marked states of the valid bitmaps in the data root object area are all invalid, and the all-flash array is in an incompatible state.
3. The management method according to claim 2, characterized in that, The step of adjusting the all-flash array according to the working state of the controller further includes: When any controller restarts after a failure, the failed controller initiates a critical information read request to other valid controllers in the cluster. The critical information includes data root object area metadata, object mapping relationships, and transaction logs. The effective controller transmits the key information to the faulty controller via a high-speed data synchronization channel in a combination of incremental synchronization and verification. The fault controller uses a double hash check algorithm to verify the integrity of key information, and at the same time uses a hierarchical index reconstruction mechanism to restore the object index and complete the alignment construction of the root object area of the full data.
4. The management method according to claim 3, characterized in that, The alignment construction includes: The memory management module counts the memory segments within the expansion area and sends a set of memory unit IDs to the memory proxy module. The memory proxy module then downgrades the memory units in the set of memory unit IDs. The memory management module polls the memory segments of each controller expansion area to release empty memory units, and then aligns the empty memory units.
5. The management method according to claim 1, characterized in that, This management approach also includes: Each controller stores the object description area of other controllers, and the object description areas are isolated from each other through a hardware-level memory isolation mechanism. The memory isolation mechanism adopts dual protection of page table-level access control and hardware access monitoring. When the memory management module is migrated, each controller uses incremental copy and description area mapping redirection technology to copy the valid area related to memory management in the object description area of the former master controller to the object description area of the new master controller. After the copy is completed, the new master controller marks the object description area of the former master controller as historical read-only, while the object description area of the new master controller is marked as writable.
6. The management method according to claim 1, characterized in that, The description information of each memory segment in the object description area includes at least: the region identifier to which the memory segment belongs, the physical memory start address corresponding to the memory segment, the usage status of the memory segment, and the capacity information of the memory segment; The region identifier of the memory segment includes the memory unit ID, verification information, status, reserved identifier, and number of replicas.
7. The management method according to claim 1, characterized in that, The data object area includes all memory segments that can be allocated to business modules for each controller and a memory segment occupancy bitmap. The memory segment occupancy bitmap is used to record the usage of all memory segments in the current controller.
8. The management method according to claim 1, characterized in that, This management approach also includes: Adjust the number of memory segments and the size of each memory segment in the data root object area according to user needs.
9. A management device for a power-saving memory array of an all-flash array, wherein the all-flash array comprises multiple controllers, characterized in that, The device includes: The first processing module is used to set up a power-saving memory space for each controller. The power-saving memory space includes a memory root object and a memory management module. The memory root object is used to store the controller's startup initialization information and configuration information. The memory management module includes an object description area, a data root object area, and a data object area. The second processing module is used to divide the data root object area and the data object area into at least one memory segment, each memory segment corresponding to a physical memory address. The data root object area includes a valid bitmap for recording the validity of the controller. The third processing module is used to store the description information of the data root object area and the memory segment in the data object area using the object description area, and each object description corresponds to a memory segment. The fourth processing module is used to adjust the all-flash array according to the working state of the controller.
10. A machine-readable storage medium storing instructions thereon, characterized in that, This instruction is used to cause the machine to execute the management method of the all-flash array power-saving memory as described in any one of claims 1-8 of this application.