Test method, device and equipment of SPD hub chip and medium

Abstract

The invention relates to an SPD hub chip testing method and device, equipment and a storage medium. The method comprises the steps that if it is determined that a to-be-tested SPD hub chip is placed in a replaceable limiting frame of a test seat and communication connection is established with an upper computer, target environment parameters are set, the to-be-tested SPD hub chip is initialized, the upper computer is in communication connection with the test seat, preset test data are written into an EEPROM of the SPD hub chip based on the target environment parameters, then read-back comparison is carried out, and the to-be-tested SPD hub chip is initialized; the static verification data is used for judging the static storage reliability of the to-be-tested SPD hub chip in the current environment, executing continuous read-write operation on the to-be-tested SPD hub chip to obtain a dynamic pressure test data set, and generating a test result of the to-be-tested SPD hub chip based on the static verification data and the dynamic pressure test data set.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a testing method, apparatus, device and storage medium for an SPD hub chip. Background Technology

[0002] The SPD hub chip manages Serial Presence Detection (SPD) information access for multiple memory modules. Its integrated EEPROM needs to reliably store configuration data under various environmental conditions. Currently, the industry generally relies on expensive ATE (Automatic Test Equipment) to verify the reliability of SPD hub chips. While this method can complete the test, the high cost of ATE platform hardware and software makes it difficult to deploy on a large scale in production lines or small laboratories. Furthermore, traditional testing is mostly conducted in conventional environments, lacking simulation of actual operating conditions in other environments, and thus failing to accurately assess the chip's data retention capability and communication stability in real-world usage environments.

[0003] Therefore, providing a technical solution that can accurately evaluate the data retention capability and communication stability of a chip in a real-world usage environment has become a pressing technical problem for those skilled in the art. It should be noted that the information disclosed in the background section above is only for enhancing the understanding of the background of this disclosure and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In view of the above, this application provides a testing method, apparatus, device and storage medium for an SPD hub chip, the purpose of which is to solve the above-mentioned technical problems.

[0005] Firstly, this application provides a testing method for an SPD hub chip, the method comprising:

[0006] If it is determined that the SPD hub chip under test is placed in the replaceable limit frame of the test socket and a communication connection is established with the host computer, the target environment parameters are set and the SPD hub chip under test is initialized, wherein the host computer is in communication connection with the test socket;

[0007] Based on the target environment parameters, preset test data is written into the EEPROM of the SPD hub chip and then read back for comparison to generate static verification data. The static verification data is used to determine the static storage reliability of the SPD hub chip under test in the current environment.

[0008] Perform continuous read and write operations on the SPD hub chip under test to obtain a dynamic stress test dataset;

[0009] Based on the static verification data and the dynamic stress test dataset, the test results of the SPD hub chip under test are generated.

[0010] Secondly, this application provides a testing apparatus for an SPD hub chip, which includes a module for performing the above-described testing method for the SPD hub chip.

[0011] Thirdly, this application provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0012] Memory, used to store computer programs;

[0013] When the processor executes a program stored in the memory, it implements the steps of the testing method for the SPD hub chip described in any embodiment of the first aspect.

[0014] Fourthly, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the testing method for an SPD hub chip as described in any embodiment of the first aspect.

[0015] The technical solutions provided in this application have the following advantages compared with the prior art:

[0016] This application constructs a low-cost testing platform, applies target environmental parameters to the SPD hub chip under test within a replaceable limit frame, and combines static write-readback verification with dynamic continuous read-write stress testing to evaluate its static storage reliability and dynamic communication robustness under real-world operating conditions. It does not rely on ATE equipment, has low hardware costs, and can be mass-produced. By fusing static verification data and dynamic stress test datasets to generate comprehensive test results, it improves test coverage and solves the problems of high cost and weak test environment simulation capabilities in existing technologies, providing a practical solution for the reliability verification of SPD hub chips. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating a preferred embodiment of the testing method for the SPD hub chip in this application;

[0020] Figure 2 This is a schematic diagram of a preferred embodiment of the testing apparatus for the SPD hub chip of this application;

[0021] Figure 3 This is a schematic diagram of a preferred embodiment of the electronic device of this application;

[0022] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0024] It should be noted that the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0025] Reference Figure 1 The diagram shown is a flowchart illustrating an embodiment of the testing method for the SPD hub chip of this application. This method is executed by an electronic device, which can be implemented by a software system and / or a hardware system. The testing method for the SPD hub chip includes:

[0026] Step S10: If it is determined that the SPD hub chip under test is placed in the replaceable limit frame of the test socket and a communication connection is established with the host computer, set the target environment parameters and initialize the SPD hub chip under test, wherein the host computer is in communication connection with the test socket.

[0027] Step S20: Based on the target environment parameters, write preset test data into the EEPROM of the SPD hub chip and then perform a readback comparison to generate static verification data. The static verification data is used to determine the static storage reliability of the SPD hub chip under test in the current environment.

[0028] Step S30: Perform continuous read and write operations on the SPD hub chip under test to obtain a dynamic stress test dataset;

[0029] Step S40: Based on the static verification data and the dynamic stress test dataset, generate the test results for the SPDhub chip under test.

[0030] Because the SPD hub (Serial Presence Detect Hub) chip integrates a small-capacity EEPROM for caching or configuration, its data retention capability and communication stability under harsh environments such as high temperature, high humidity, or long-term operation directly affect whether the entire device can correctly identify memory parameters and start stably. Traditional methods for verifying SPD hub chips rely on expensive ATE (Automatic Test Equipment) platforms, which are costly and lack the ability to simulate real-world environmental stresses. Therefore, this application embodiment comprehensively evaluates the chip's reliability under both static storage and dynamic operation dimensions by constructing a controllable environment and automated read / write processes.

[0031] The SPD hub chip under test is accurately installed in the replaceable limiting frame of the test socket. This limiting frame can be flexibly replaced according to the chip package form to ensure reliable electrical contact. A stable I2C communication connection is established between the SPD hub chip and the host computer through the interface circuit built into the test socket. The host computer interacts with the test socket for command exchange and data acquisition via a serial bus. Based on this, the host computer sends target environmental parameters (such as 85% RH relative humidity and 1.2V supply voltage) to the environmental simulation unit in the test socket. After the environmental parameters stabilize, an initialization operation is performed on the SPD hub chip, including sending a reset command and erasing its internal EEPROM, placing it in a known empty state to provide baseline conditions for subsequent conformance verification.

[0032] Based on the pre-defined environmental parameters, the host computer generates a test data packet containing a random number sequence and a preset pattern (such as all 0s, all 1s, or incrementing bytes), and writes it completely into the specified address range of the EEPROM of the SPD hub chip under test via the I2C interface. After writing, a readback operation is immediately initiated to read data from the same address, and the readback result is compared byte-by-byte with the original test data packet. If discrepancies are found, the abnormal location and value are recorded. The comparison result, timestamp, and environmental parameters are integrated to form static verification data. This static verification data is used to determine whether the SPD hub chip has reliable static data storage capabilities under the current environmental parameters, i.e., whether its EEPROM can accurately retain the written content for a long period without frequent operational interference.

[0033] To evaluate the robustness of the chip under high-frequency access scenarios in real-world use, the host computer performed continuous I2C read and write operations on the SPD hub chip under test while maintaining the same environmental parameters. For example, it executed 1000 "write-readback" commands at 10ms intervals, covering different address regions. During this process, the response status, data consistency, communication latency, and any abnormal events such as bus lock-up were recorded in real time for each operation. Finally, all records were structured to form a dynamic stress test dataset. This dataset reflects the communication stability and anti-interference capability of the SPD hub chip under continuous load, compensating for timing-sensitive defects that cannot be detected by a single static test.

[0034] The host computer performs a comprehensive analysis of the generated static verification data and dynamic stress test dataset. If there are no inconsistencies in the static verification data and no communication failures or error rates exceeding a preset threshold (e.g., ≤3 errors) occur in the dynamic stress test dataset, the SPD hub chip under test is deemed to have passed reliability verification under the current environmental parameters, and a test result indicating success is generated. Otherwise, a test result indicating failure is generated. By integrating static and dynamic data, the reliability level of the SPD hub chip in the actual deployment environment can be more comprehensively and realistically reflected.

[0035] In one embodiment, initializing the SPD hub chip under test includes:

[0036] Send a configuration command to the SPD hub chip under test to enable the SPD hub chip under test to enter the ready mode;

[0037] Perform a full address erase operation on the EEPROM inside the SPD hub chip to put the SPD hub chip under test into an initial empty state.

[0038] The host computer sends a specific configuration command (e.g., a reset command) to the SPD hub chip under test, which is placed in the replaceable limit frame, via the I2C interface of the test socket. This command triggers the chip's internal state machine to switch to ready mode, ensuring that its I2C controller is in an active state that can respond to external read and write requests, thus avoiding subsequent communication failures due to the chip being in a low-power, sleep, or uninitialized state. After confirming that the chip has entered ready mode, the host computer immediately performs a full-address range erase operation on its internally integrated EEPROM, that is, uniformly writes all programmable memory cells to a preset initial value (such as 0xFF or 0x00), thereby clearing any residual historical data or factory default configurations, and normalizing the storage state of the SPD hub chip under test to a known initial empty state. This initial empty state provides a deterministic benchmark for subsequent writing of preset test data.

[0039] In one embodiment, the step of writing preset test data into the EEPROM of the SPD hub chip based on the target environment parameters and then performing a readback comparison to generate static verification data includes:

[0040] A test data packet containing random numbers and a preset pattern sequence is generated based on the target environment parameters. The test data packet is written to the EEPROM of the SPDhub chip under test and the timestamp of the write operation is recorded.

[0041] After the write operation is completed, data in the corresponding address range is read from the EEPROM, and the read result is compared byte by byte with the test data packet to obtain the comparison result;

[0042] Based on the comparison results and the timestamp, static verification data is generated.

[0043] The host computer dynamically generates a test data packet based on the currently set and stable target environment parameters. The data packet integrates two typical data patterns: one part is a pseudo-random number sequence (used to cover unstructured data scenarios), and the other part is a preset pattern sequence (such as all 0x00, all 0xFF, incrementing bytes 0x00~0xFF, etc., used to detect fixed faults in specific addresses or bit lines). Subsequently, the host computer writes the test data packet completely into the specified address range of the EEPROM inside the SPD hub chip under test through the I2C interface, and simultaneously records the timestamp of this write operation to mark the exact time of data writing, which is convenient for subsequent traceability and association with the environmental status.

[0044] After the write operation is confirmed, the host computer immediately initiates a readback operation to read data from the EEPROM within the same address range as the write operation, obtaining the read result. This read result is then compared byte-by-byte with the original test data packet to verify the consistency of the values. If any byte mismatch is found, the address offset, expected value, and actual value of that byte are recorded, forming a detailed comparison result.

[0045] The host computer integrates the above comparison results with the corresponding timestamps and associates them with the current target environment parameters to generate a complete static verification data record. This static verification data not only reflects the data retention capability of the SPD hub chip under test in a specific environment, but also supports time-series alignment analysis of the data in the subsequent dynamic testing phase because it contains timestamps, thus realizing a refined evaluation of the static storage reliability of the SPD hub chip.

[0046] Further, the step of reading data from the corresponding address range from the EEPROM and comparing the reading result with the test data packet byte by byte to obtain the comparison result includes:

[0047] Send a read command to the SPD hub chip under test to determine the same address range as the write operation;

[0048] The readback data stored in the EEPROM is obtained according to the address range;

[0049] The readback data is compared byte by byte with the corresponding data in the original test data packet to determine the number of mismatched bytes and the address offset of the mismatched bytes.

[0050] A structured comparison result is generated based on the number of mismatched bytes and the address offset.

[0051] The host computer initiates a standard EEPROM read command to the SPD hub chip under test via the I2C interface, explicitly specifying the starting address and length of the read. This address range strictly corresponds to the address range used when writing preset test data, ensuring that the read and write operations are performed in the exact same storage area and avoiding misjudgments due to address misalignment. The SPD hub chip under test responds to the read command, returning the complete data stored in its internal EEPROM within the specified address range. The host computer receives and caches this data as readback data.

[0052] The host computer reads back the data byte by byte and compares it one by one with the bytes at the same offset position in the original test data packet. For each byte position, if the read value does not match the expected value, the address offset of that byte (i.e., the offset relative to the starting address) and the specific difference are recorded. After the comparison is completed, the number of all mismatched bytes is counted, and a list of their corresponding address offsets is compiled.

[0053] Based on the number of mismatched bytes and their address offset information, the host computer generates a structured comparison result. If the number of mismatches is zero, the comparison result is marked as consistent; if there are one or more mismatched bytes, the comparison result is marked as abnormal and includes error count, error address list, and expected and actual values ​​of each byte in a structured format (such as JSON or binary log). This structured comparison result is not only used for the current static verification, but can also be used as input data for subsequent failure analysis or yield statistics.

[0054] In one embodiment, performing continuous read / write operations on the SPD hub chip under test to obtain a dynamic stress test dataset includes:

[0055] According to the preset frequency and address sequence, continuously write and read back commands are sent to the EEPROM of the SPD hub chip under test.

[0056] After each read / write operation is completed, the communication response status, data consistency results, and operation time are recorded in real time.

[0057] The communication response status, data consistency results, and operation time are cached as raw stress logs in chronological order.

[0058] Based on the raw stress logs, abnormal events, time-series fluctuations, and error rate metrics are extracted to generate a dynamic stress test dataset.

[0059] Under stable environmental parameters, the host computer initiates continuous I2C write and read commands to the EEPROM of the SPD hub chip under test according to the preset test strategy. The preset frequency is set to execute a complete read / write cycle every 10 milliseconds, and the address sequence covers multiple areas of the EEPROM to simulate random access behavior to different storage locations in the actual system, thereby applying continuous and diverse operational pressure to the chip's I2C controller and internal storage units.

[0060] After each read / write operation is completed, the host computer immediately collects and records three key indicators in real time: first, the communication response status (including whether an ACK is received, whether there is a bus timeout or NACK error); second, the data consistency result (i.e., whether the read-back data matches the just-written data byte by byte); and third, the operation time (the time interval from sending the command to receiving a complete response, used to evaluate timing stability). These indicators reflect the chip's instantaneous behavior under high-frequency operation.

[0061] The host computer caches the above three indicators, along with the operation sequence number and timestamp, in chronological order into the local storage, generating a complete original stress log. This log is indexed by the time axis, providing the original basis for subsequent analysis.

[0062] After completing a preset number of continuous read / write cycles (e.g., 1000 times), the host computer performs structured processing on the raw stress log, extracting all abnormal events (such as communication failures and data inconsistencies), timing fluctuations (such as outliers where operation time deviates significantly from the mean), and overall error rate indicators (such as the percentage of error counts to total operation counts). Based on this information, a dynamic stress test dataset is generated. This dataset is not only used to determine the functional robustness of the SPD hub chip under continuous load, but also serves as a quantitative basis for evaluating its long-term operational reliability.

[0063] In one embodiment, generating the test results for the SPD hub chip under test based on the static verification data and the dynamic stress test dataset includes:

[0064] Based on the static verification data, determine whether the SPD hub chip under test has a data retention error;

[0065] If not, evaluate whether the SPD hub chip under test experiences communication abnormalities during continuous read / write operations based on the dynamic stress test dataset;

[0066] If not, generate a test result indicating that the characterization test passed; if yes, generate a test result indicating that the characterization test failed.

[0067] The host computer parses the static verification data and checks whether it contains byte inconsistency records caused by EEPROM data retention failure. If such errors exist, the SPD hub chip under test is directly determined to be unreliable in static storage under the current environmental parameters, without further judgment, and a test result indicating that the characterization test failed is generated. If no data retention errors are found in the static verification data, the dynamic stress test dataset is further analyzed to determine whether I2C communication anomalies (such as bus timeouts or NACK responses) or data consistency errors accumulate to a preset threshold during continuous read and write operations. If no anomalies are triggered in the dynamic test phase, a test result indicating that the characterization test passed is generated. Conversely, if any valid anomaly event exists in the dynamic stress test dataset, a test result indicating that the test failed is generated.

[0068] In one embodiment, the method further includes:

[0069] The test results are associated with the identifier of the SPD hub chip under test and stored in a preset path.

[0070] After generating the test results for the SPD hub chip under test, the host computer obtains the chip's identification information. This identification information can originate from a laser marking code on the chip itself (such as a serial number read by a barcode scanner) or the factory ID read from the chip's internal registers during the test initialization phase. The host computer encapsulates this identification along with the corresponding test results (including static verification data, dynamic stress test datasets, judgment conclusions, and associated environmental parameters) into a structured record. This record is saved to a preset path on a local storage device or network server according to a preset data format (such as JSON, CSV, or database table entries), enabling the test results of the SPD hub chip under test to be quickly queried.

[0071] Reference Figure 2 The diagram shown is a functional module schematic of the testing device 100 for the SPD hub chip of this application.

[0072] The testing device 100 for the SPD hub chip described in this application is installed in an electronic device. Depending on the functions implemented, the testing device 100 for the SPD hub chip includes a determination module 110, a first testing module 120, a second testing module 130, and a generation module 140. These modules can also be referred to as units, which are a series of computer program segments that can be executed by the processor of an electronic device and perform a fixed function, and are stored in the memory of the electronic device.

[0073] In this embodiment, the functions of each module / unit are as follows:

[0074] Determining module 110: When it is determined that the SPD hub chip under test is placed in the replaceable limiting frame of the test socket and a communication connection is established with the host computer, setting target environmental parameters and initializing the SPD hub chip under test, wherein the host computer is in communication connection with the test socket;

[0075] First test module 120: Based on the target environment parameters, write preset test data into the EEPROM of the SPD hub chip and then perform readback comparison to generate static verification data, wherein the static verification data is used to determine the static storage reliability of the SPD hub chip under test in the current environment.

[0076] The second test module 130 is used to perform continuous read and write operations on the SPD hub chip under test to obtain a dynamic stress test dataset.

[0077] Generation module 140: Used to generate test results for the SPD hub chip under test based on the static verification data and the dynamic stress test dataset.

[0078] The specific implementation of the testing device for the SPD hub chip in this application is largely the same as the specific implementation of the testing method for the SPD hub chip described above, and will not be repeated here.

[0079] Reference Figure 3 The diagram shown is a schematic representation of a preferred embodiment of the electronic device of this application.

[0080] The electronic device includes a processor 111, a communication interface 112, a memory 113, and a communication bus 114, wherein the processor 111, the communication interface 112, and the memory 113 communicate with each other through the communication bus 114.

[0081] Memory 113 is used to store computer programs, such as test programs for the SPD hub chip;

[0082] In some embodiments, the processor 111 may be a central processing unit (CPU), controller, microcontroller, microprocessor, or other data processing chip. The processor 111 is typically used to control the overall operation of the electronic device, such as performing data interaction or communication-related control and processing. In this embodiment, the processor 111 is used to run program code stored in the memory 113 or process data.

[0083] The communication interface 112 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The communication interface 112 may also be used to establish a communication connection between the electronic device and other electronic devices.

[0084] The memory 113 includes at least one type of readable storage medium, including flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 113 may be an internal storage unit of the electronic device, such as the hard disk or memory of the electronic device. In other embodiments, the memory 113 may also be an external storage device of the electronic device, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc. of the electronic device. Of course, the memory 113 may include both internal storage units and external storage devices of the electronic device. In this embodiment, the memory 113 is typically used to store the operating system and various computer programs installed on the electronic device, such as the program code of the test program for the SPD hub chip. In addition, the memory 113 may also be used to temporarily store various types of data that have been output or will be output.

[0085] Figure 3 Only an electronic device with components 111-114 is shown; however, it should be understood that it is not required to implement all of the components shown, and more or fewer components may be implemented instead.

[0086] In one embodiment of this application, the processor 111, when executing a program stored in the memory 113, implements the testing method for the SPD hub chip provided in any of the foregoing method embodiments, including:

[0087] If it is determined that the SPD hub chip under test is placed in the replaceable limit frame of the test socket and a communication connection is established with the host computer, the target environment parameters are set and the SPD hub chip under test is initialized, wherein the host computer is in communication connection with the test socket;

[0088] Based on the target environment parameters, preset test data is written into the EEPROM of the SPD hub chip and then read back for comparison to generate static verification data. The static verification data is used to determine the static storage reliability of the SPD hub chip under test in the current environment.

[0089] Perform continuous read and write operations on the SPD hub chip under test to obtain a dynamic stress test dataset;

[0090] Based on the static verification data and the dynamic stress test dataset, the test results of the SPD hub chip under test are generated.

[0091] For a detailed explanation of the above steps, please refer to the above. Figure 1 A flowchart illustrating an embodiment of a test method for an SPD hub chip.

[0092] Furthermore, this application also proposes a computer-readable storage medium that is both non-volatile and volatile. This computer-readable storage medium is any one or any combination of several of the following: hard disk, multimedia card, SD card, flash memory card, SMC, read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, etc. The computer-readable storage medium includes a data storage area and a program storage area. The program storage area stores a test program for the SPD hub chip. When the test program for the SPD hub chip is executed by the processor, it performs the following operations:

[0093] If it is determined that the SPD hub chip under test is placed in the replaceable limit frame of the test socket and a communication connection is established with the host computer, the target environment parameters are set and the SPD hub chip under test is initialized, wherein the host computer is in communication connection with the test socket;

[0094] Based on the target environment parameters, preset test data is written into the EEPROM of the SPD hub chip and then read back for comparison to generate static verification data. The static verification data is used to determine the static storage reliability of the SPD hub chip under test in the current environment.

[0095] Perform continuous read and write operations on the SPD hub chip under test to obtain a dynamic stress test dataset;

[0096] Based on the static verification data and the dynamic stress test dataset, the test results of the SPD hub chip under test are generated.

[0097] The specific implementation of the computer-readable storage medium in this application is largely the same as the specific implementation of the test method for the SPD hub chip described above, and will not be repeated here.

[0098] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, apparatus, article, or method. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0099] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware simulation platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0100] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A testing method for an SPD hub chip, characterized in that, The method includes: If it is determined that the SPD hub chip under test is placed in the replaceable limit frame of the test socket and a communication connection is established with the host computer, the target environment parameters are set and the SPD hub chip under test is initialized, wherein the host computer is in communication connection with the test socket; Based on the target environment parameters, preset test data is written into the EEPROM of the SPD hub chip and then read back for comparison to generate static verification data. The static verification data is used to determine the static storage reliability of the SPD hub chip under test in the current environment. Perform continuous read and write operations on the SPD hub chip under test to obtain a dynamic stress test dataset; Based on the static verification data and the dynamic stress test dataset, the test results of the SPD hub chip under test are generated.

2. The testing method for the SPD hub chip as described in claim 1, characterized in that, The initialization of the SPD hub chip under test includes: Send a configuration command to the SPD hub chip under test to enable the SPD hub chip under test to enter the ready mode; Perform a full address erase operation on the EEPROM inside the SPD hub chip to put the SPD hub chip under test into an initial empty state.

3. The testing method for the SPD hub chip as described in claim 1, characterized in that, The process of writing preset test data into the EEPROM of the SPD hub chip based on the target environment parameters, followed by readback and comparison to generate static verification data, includes: A test data packet containing random numbers and a preset pattern sequence is generated based on the target environment parameters. The test data packet is written to the EEPROM of the SPD hub chip under test and the timestamp of the write operation is recorded. After the write operation is completed, data in the corresponding address range is read from the EEPROM, and the read result is compared byte by byte with the test data packet to obtain the comparison result; Based on the comparison results and the timestamp, static verification data is generated.

4. The testing method for the SPD hub chip as described in claim 3, characterized in that, The step of reading data from the corresponding address range from the EEPROM and comparing the read result with the test data packet byte by byte to obtain the comparison result includes: Send a read command to the SPD hub chip under test to determine the same address range as the write operation; The readback data stored in the EEPROM is obtained according to the address range; The readback data is compared byte by byte with the corresponding data in the original test data packet to determine the number of mismatched bytes and the address offset of the mismatched bytes. A structured comparison result is generated based on the number of mismatched bytes and the address offset.

5. The testing method for the SPD hub chip as described in claim 1, characterized in that, The step of performing continuous read and write operations on the SPD hub chip under test to obtain a dynamic stress test dataset includes: According to the preset frequency and address sequence, continuously write and read back commands are sent to the EEPROM of the SPD hub chip under test. After each read / write operation is completed, the communication response status, data consistency results, and operation time are recorded in real time. The communication response status, data consistency results, and operation time are cached as raw stress logs in chronological order. Based on the raw stress logs, abnormal events, time-series fluctuations, and error rate metrics are extracted to generate a dynamic stress test dataset.

6. The testing method for the SPD hub chip as described in claim 5, characterized in that, The step of generating test results for the SPD hub chip under test based on the static verification data and the dynamic stress test dataset includes: Based on the static verification data, determine whether the SPD hub chip under test has a data retention error; If not, evaluate whether the SPD hub chip under test experiences communication abnormalities during continuous read / write operations based on the dynamic stress test dataset; If not, generate a test result indicating that the characterization test passed; if yes, generate a test result indicating that the characterization test failed.

7. The testing method for the SPD hub chip as described in claim 1, characterized in that, The method further includes: The test results are associated with the identifier of the SPD hub chip under test and stored in a preset path.

8. A testing device for an SPD hub chip, characterized in that, The apparatus includes a module that performs a test method for the SPD hub chip as described in any one of claims 1 to 7.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the test method for the SPDhub chip according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the testing method for the SPD hub chip as described in any one of claims 1 to 7.

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