Prefetch request processing method and device, electronic equipment and readable storage medium

Abstract

The invention discloses a prefetching request processing method and device, equipment and a medium. The method comprises the following steps: firstly, initiating a prefetching request to an external memory according to a storage read pointer, distributing a first prefetching request identifier for the prefetching request in a prefetching request identifier resource pool, and updating state information of the prefetching request in response to a target event to represent validity of prefetching data requested by the prefetching request. And determining corresponding state information in the resource pool according to a second prefetching request identifier carried by the prefetching data. And finally, determining whether the prefetched data is valid or not according to the state information, and executing cache writing operation on the valid prefetched data. The state of each prefetch request is uniquely identified and tracked in the whole process through the prefetch request identifier, the state information and the unique identifier, and the cache writing operation is controlled according to the validity information when the prefetch data is returned, so that invalid data is identified and discarded, cache pollution is avoided, only valid data is saved in the cache, the invalid data is prevented from occupying the cache space, and the cache efficiency is improved. And the cache utilization rate is improved.

Description

Technical Field

[0001] This application belongs to the field of computer architecture, and specifically relates to a method for processing prefetch requests, a device for processing prefetch requests, an electronic device, and a readable storage medium. Background Technology

[0002] In the field of computer architecture, especially in the design of high-performance GPUs (Central Processing Units) / CPUs (Graphics Processing Units), instruction or data prefetching is a key technology for hiding memory access latency and improving processor performance. The basic idea is to predict the processor's future access needs and prefetch data from slow external memory (such as main memory or low-level cache) into high-speed cache.

[0003] The traditional prefetch process is typically as follows: the prefetch controller initiates a prefetch request based on the program counter or address stream sequence; when the external memory returns prefetched data, the cache controller writes the returned data to the cache location pointed to by the cache write pointer and advances the write pointer.

[0004] However, this traditional prefetching method has the following inherent defects when dealing with complex modern computing workloads: lack of management of prefetch requests; after a prefetch request is issued but before the prefetched data is returned, the request may become invalid due to reasons such as branch misprediction or dynamic updates of code segments; invalid data is also written to the cache, resulting in low cache operating efficiency. Summary of the Invention

[0005] The purpose of this application is to provide a method for processing prefetch requests, a device for processing prefetch requests, an electronic device, and a readable storage medium, which can solve the problem of lack of management of prefetch requests, where the request becomes invalid after it is issued but before the prefetched data is returned, and the invalidated data is also written to the cache, resulting in low cache operating efficiency.

[0006] To solve the above-mentioned technical problems, this application is implemented as follows: In a first aspect, embodiments of this application provide a method for processing prefetch requests, the method comprising: A prefetch request is initiated to the external memory according to the address indicated by the storage read pointer, and a first prefetch request identifier is allocated for the prefetch request in the prefetch request identifier resource pool; In response to a detected target event, the status information of the prefetch request is updated; the status information is used to characterize the validity of the prefetch data requested by the prefetch request. Based on the second prefetch request identifier carried in the prefetch data returned by the external memory, a first prefetch request identifier that matches the second prefetch request identifier is queried in the prefetch request identifier resource pool, and the corresponding status information is determined based on the query result; Based on the status information, determine whether the prefetched data is valid, and perform a write operation to the cache for valid prefetched data.

[0007] Secondly, embodiments of this application provide a prefetch request processing apparatus, the apparatus comprising: The request initiation module is used to initiate a prefetch request to the external memory according to the address indicated by the storage read pointer, and to allocate a first prefetch request identifier for the prefetch request in the prefetch request identifier resource pool; An information update module is used to update the status information of the prefetch request in response to a detected target event; the status information is used to characterize the validity of the prefetch data requested by the prefetch request. The status determination module is used to query the prefetch request identifier that matches the second prefetch request identifier in the prefetch request identifier resource pool based on the second prefetch request identifier carried in the prefetch data returned by the external memory, and determine the corresponding status information based on the query result. The write control module is used to determine whether the prefetched data is valid based on the status information, and to perform a write cache operation on the valid prefetched data.

[0008] Thirdly, embodiments of this application provide an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method described in the first aspect.

[0009] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0010] According to the embodiments of this application, a prefetch request is first initiated to the external memory based on the address indicated by the storage read pointer, and a first prefetch request identifier is allocated for the prefetch request in the prefetch request identifier resource pool. In response to a detected target event, the status information of the prefetch request is updated; the status information characterizes the validity of the prefetched data requested by the prefetch request. Based on the second prefetch request identifier carried in the prefetched data returned by the external memory, a first prefetch request identifier matching the second prefetch request identifier is queried in the prefetch request identifier resource pool, and the corresponding status information is determined based on the query result. Based on the status information, it is determined whether the prefetched data is valid, and a write cache operation is performed for valid prefetched data. In this scheme, the status of each prefetch request is uniquely identified and tracked throughout the process through the prefetch request identifier and status information in the prefetch request identifier resource pool. This allows for control of the write cache operation based on the status information when prefetched data is returned, thereby dynamically identifying and discarding invalid data, avoiding cache pollution, ensuring that only valid data is stored in the cache, preventing invalid data from occupying cache space, and improving cache utilization. Attached Figure Description

[0011] Figure 1 This is a flowchart illustrating the steps of a prefetch request processing method provided in an embodiment of this application; Figure 2 This is a schematic diagram of a circular cache; Figure 3 This is a diagram illustrating the prefetch request identifier resource pool; Figure 4 This is a schematic diagram of the memory storage structure; Figure 5 This is a schematic diagram of the response mechanism for updating the write pointer. Figure 6 This is a schematic diagram of the skip read response mechanism; Figure 7 This is a flowchart of the prefetch data processing. Figure 8 This is a flowchart of the read request processing in the decoding module; Figure 9 This is a flowchart illustrating the steps of a prefetch request processing method provided in an embodiment of this application; Figure 10 This is a flowchart illustrating the process of prefetching requests; Figure 11 This is a structural block diagram of an embodiment of a prefetch request processing apparatus provided in another embodiment of the present invention; Figure 12 This is a structural block diagram of an electronic device for processing prefetch requests, according to an exemplary embodiment. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0013] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0014] The prefetch request processing method provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0015] External memory is a storage device located outside the processor core, used to store data and program instructions. Common external memory includes hard disk drives (HDDs), solid-state drives (SSDs), dynamic random access memory (DRAM), read-only memory (ROM), and non-volatile memory (such as NAND flash memory).

[0016] External memory refers to a relatively slower, larger storage tier located outside the internal cache, and it serves as the data source for prefetching operations. Data is fetched from external memory in advance and populated into a faster, smaller internal cache for high-speed access by processor cores (such as decoding units).

[0017] External memory can be either a traditional linear address space or a ring address space.

[0018] For example, processor instructions can be stored in a ring-shaped external memory, where the address space is logically contiguous, forming a circular region. Successive accesses to the instruction stream are mapped to this ring-shaped space.

[0019] A memory pointer points to the address of a specific data item in external memory, with finer granularity, typically measured in bytes or words (e.g., pointing to an instruction or a data word). In instruction prefetching or data access, memory pointers are used to identify the current or next location to be accessed.

[0020] The memory read pointer is an address pointer that points to the source address of the next instruction to be fetched from external memory. The memory read pointer can increment incrementally according to instruction word granularity (e.g., 32-bit / 64-bit), wrapping back to the beginning when it reaches the end of the circular space in external memory. Specifically, this can be driven by the instruction fetch logic, which moves the memory read pointer forward incrementally based on the instruction consumption rate.

[0021] The storage write pointer indicates the address of the instruction data to be written to or updated in external memory next. In scenarios where instructions can be dynamically loaded / modified (such as code segment replacement, remote loading, and streaming execution), the storage write pointer is moved forward by external control logic to fill or replace instructions in external memory. For linear address spaces, the storage write pointer monotonically increases at the instruction word granularity (e.g., 32-bit / 64-bit). When it reaches the end of the space defined by system configuration (e.g., the upper limit of the process address space), it can request more virtual memory resources from the operating system. For circular address spaces, the storage write pointer can increment incrementally at the instruction word granularity (e.g., 32-bit / 64-bit). When it reaches the end of the circular space in external memory, it wraps back to the beginning.

[0022] In other words, the memory read pointer identifies the location of the latest instruction that has been consumed by the instruction fetch unit, while the memory write pointer indicates the address where a new instruction will be written. The address difference between the two defines the number of valid instructions within the external memory ring. To ensure reliability, the movement of the memory write pointer must be constrained by a pointer management mechanism to prevent it from exceeding the memory read pointer, thereby avoiding overwriting valid instructions that have not yet been consumed.

[0023] Reference Figure 1 The diagram illustrates a flowchart of a prefetch request processing method provided in an embodiment of this application, which may specifically include the following steps: Step 101: Initiate a prefetch request to the external memory according to the address indicated by the storage read pointer, and allocate a first prefetch request identifier for the prefetch request in the prefetch request identifier resource pool.

[0024] In this embodiment, the prefetch request is generated by the prefetch logic based on the current position of the memory read pointer. Its purpose is to retrieve data (such as instructions) from external memory in advance, thereby reducing the processor's (CPU, GPU, etc.) waiting time. For example, when the memory read pointer points to address A, the prefetch logic may generate a prefetch request requesting a certain amount of data starting from address A.

[0025] In this embodiment, the prefetch request identifier resource pool is used to assign a unique first prefetch request identifier to each prefetch request and record the status information of the prefetch request. This resource pool acts as a management center, using unique identifiers to track and manage each prefetch request. For example, when a prefetch request is generated, the resource pool assigns it a unique number and records the relevant status information of the request, such as the cache start position.

[0026] In this embodiment, the status information recorded in the prefetch request identifier resource pool refers to the relevant status during the processing of the prefetch request, such as validity information. The status information is used to characterize the validity of the prefetched data requested by the prefetch request and can be used to determine whether the prefetched data is valid.

[0027] In this embodiment, the prefetch logic is a hardware module integrated inside the processor, which is configured to perform all operations of prefetch address generation, prefetch request identifier allocation, status information management, and initiating prefetch requests to external memory.

[0028] In this embodiment, the prefetch logic generates one or more prefetch requests based on the current position of the storage read pointer. A unique first prefetch request identifier is assigned to each prefetch request in the prefetch request identifier resource pool, and the status information of the prefetch request is recorded. For example, if the storage read pointer currently points to address A, the prefetch logic generates a prefetch request based on this address, assigns an identifier ID1 to the request in the resource pool, and records the status information.

[0029] Step 102: In response to the detected target event, update the status information of the prefetch request; the status information is used to characterize the validity of the prefetch data requested by the prefetch request.

[0030] In the embodiments of this application, the target event refers to an event that causes previously prefetched data to become invalid or partially invalid, such as an update event of the storage write pointer, a jump event, etc. Specifically, it can include any applicable event, and the embodiments of this application do not limit it.

[0031] In this embodiment, the system needs to locate the affected prefetch request in the prefetch request identifier resource pool based on the event information carried by the target event. This process can typically be achieved by matching key parameters in the target event with key parameters in the status information recorded by each prefetch request in the resource pool. Specific association mechanisms may include, but are not limited to: First, address range matching: The status information of each prefetch request records the start address and length (or end address) of the requested data in external memory. This defines its address range. When a target event occurs, such as a memory write pointer update or a program counter jump, the event carries specific address information (e.g., the address overwritten by new data, or the target address of the program jump). The system compares the address information of the target event with the address ranges of all in-use prefetch requests in the resource pool. If the address of the target event falls within the address range of a prefetch request, the prefetch request is determined to be the target request (i.e., the prefetch request whose status information needs to be updated).

[0032] Second, identifier-based matching: In some implementations, the target event itself may directly or indirectly carry the identifier (ID) of the specific prefetch request it affects. For example, when a write operation confirmation causes a piece of prefetched data to become invalid, the generated event notification may contain the prefetch request ID corresponding to that piece of data. Based on this ID, the system can directly query the resource pool to locate and update the status information of the corresponding prefetch request.

[0033] In this embodiment, the state information is updated in response to a target event. Specific operations may include: marking the state as invalid; if the target event indicates that the prefetched data corresponding to the prefetch request is completely useless, the system will skip writing these data to avoid invalid data polluting the cache; adjusting the range of valid data; if only part of the prefetched data is invalid (e.g., the program jump only crosses the first half of the prefetched data interval), the system will shrink the valid interval, retaining the still valuable parts.

[0034] For example, in a GPU instruction stream scenario, if a subsequent program update overwrites the original instructions in external memory, the content prefetched based on the old data becomes invalid, and its state information will be updated to invalid.

[0035] Step 103: Based on the second prefetch request identifier carried in the prefetch data returned by the external memory, query the prefetch request identifier resource pool to find the first prefetch request identifier that matches the second prefetch request identifier, and determine the corresponding status information based on the query result.

[0036] In this embodiment, when the external memory returns prefetched data, the prefetched data carries a second prefetch request identifier. The control logic searches for a matching first prefetch request identifier in the prefetch request identifier resource pool based on this second prefetch request identifier. If a matching first prefetch request identifier is found, the status information corresponding to the first prefetch request identifier is obtained.

[0037] For example, the prefetch data returned by the external memory carries a second prefetch request identifier ID1. The control logic finds the corresponding first prefetch request identifier in the resource pool through ID1, and then obtains the status information corresponding to the first prefetch request identifier, thereby knowing the validity of the prefetch data.

[0038] In this embodiment, status information can be used to determine whether prefetched data should be written to the cache. For example, parameters such as a validity flag, a valid start position, and a valid end position are used. These parameters collectively define the legal write range for the prefetched data. For instance, if a prefetch request's cache start position is line 0, and the valid range is from line 0 to line 7, then any data falling within this range will be considered valid and can be written to the cache. Specifically, any applicable status information can be included, and this embodiment does not impose any limitations on this.

[0039] Step 104: Based on the status information, determine whether the prefetched data is valid, and perform a write operation to the cache for valid prefetched data.

[0040] In this embodiment of the application, the write cache operation is the process of storing prefetched data into the cache according to certain rules and order.

[0041] Specifically, status information is used to characterize whether prefetched data is valid, and its fundamental function is to prevent the system from using outdated or invalid data.

[0042] In this embodiment, the write operation of prefetched data to the cache is controlled based on status information. Specifically, any applicable control may be included, and this embodiment does not impose any limitations on this.

[0043] For example, based on the status information, if the prefetched data is valid, then a write operation to the cache is performed.

[0044] For example, if the prefetched data fails based on the status information, the write-to-cache operation is skipped.

[0045] For example, based on the status information, if some prefetched data is invalid, the invalid part is skipped, and the valid prefetched data is written to the cache.

[0046] According to the embodiments of this application, a prefetch request is first initiated to the external memory based on the address indicated by the storage read pointer. A first prefetch request identifier is allocated to the prefetch request in the prefetch request identifier resource pool. In response to a detected target event, the status information of the prefetch request is updated; the status information characterizes the validity of the prefetched data requested by the prefetch request. Then, based on the second prefetch request identifier carried in the prefetched data returned by the external memory, a first prefetch request identifier matching the second prefetch request identifier is queried in the prefetch request identifier resource pool. The corresponding status information is determined based on the query result. Finally, based on the status information, it is determined whether the prefetched data is valid, and a write cache operation is performed on the valid prefetched data. In this scheme, the status of each prefetch request is uniquely identified and tracked throughout the process by using the prefetch request identifier and status information in the prefetch request identifier resource pool. This allows for control of the write cache operation based on the status information when the prefetched data is returned, thereby dynamically identifying and discarding invalid data, avoiding cache pollution, ensuring that only valid data is stored in the cache, preventing invalid data from occupying cache space, and improving cache utilization.

[0047] It should be noted that there is no strict order between steps 101 and 102 above; they can be executed independently or concurrently. For example, after initiating a prefetch request, subsequent prefetch requests can be initiated before the status information corresponding to that prefetch request is updated; at the same time, the status of the relevant prefetch requests can be updated in response to the target event during or after initiating a prefetch request.

[0048] In one optional embodiment of this application, the status information further includes: validity information and a cache start position; the validity information is used to characterize the validity of the prefetched data requested by the prefetch request, and the cache start position is used to characterize the position where the prefetched data begins to be written in the cache. A specific implementation of determining whether the prefetched data is valid based on the status information and performing a write-to-cache operation on valid prefetched data may include: determining whether the prefetched data is valid or invalid based on the validity information; and for valid prefetched data, performing the write-to-cache operation in a circular cache based on the cache start position and the return sequence number carried by the prefetched data.

[0049] Status information includes validity information. Based on the validity information, prefetched data is classified as valid or invalid. Valid data indicates that it is still needed by the processor and should be written to the cache; invalid data indicates that it is no longer needed due to external events (such as write pointer updates) and should be discarded.

[0050] For example, the validity of the prefetched data can be determined based on a validity flag. Another example is determining the validity of the prefetched data based on a valid start position and a valid end position. Specifically, any applicable implementation method can be included, and the embodiments of this application do not limit this.

[0051] A circular cache is an internal cache that uses a circular buffer structure. It has address wraparound characteristics, reduces boundary processing overhead, and enables efficient "fetch-store-use" loop flow.

[0052] Circular caches, based on their circular mechanism where the first and last pointers are connected, achieve efficient reuse of cache space, thus fundamentally avoiding refresh and blocking when the cache is full. This feature enables them to efficiently handle a large number of consecutive instruction fetch requests common in multi-threaded programs, effectively improving instruction prefetch throughput and reducing access latency by reducing cache replacement operations.

[0053] The cache employs a linear circular cache structure, designed based on the sequential execution of GPU instructions and the minimal frequency of duplicate accesses. In this structure, the storage location of the prefetched data returned by each prefetch request within the circular cache is predetermined. Data validity is managed through the movement of the cache read pointer: when the read pointer moves past a cache line, it indicates that the data has expired, and its occupied space can be immediately overwritten by a new prefetch request. This mechanism eliminates the need to store lengthy external memory address tags for each cache line and avoids complex cache hit / miss logic, thus greatly simplifying hardware design and improving processing efficiency while meeting the linear access requirements of the GPU instruction stream.

[0054] The circular cache internally uses two independently managed pointers: the Cache Read Pointer (CRP), which marks the position in the cache of the next instruction to be sent to the decoding unit. The Cache Read Pointer is driven by the core execution unit's instruction fetch requests, incrementing sequentially at the cache behavior granularity, and wrapping around after reaching the end of the buffer. The Cache Write Pointer (CWP) marks the position in the cache where the next prefetch request will be written, even if it hasn't been issued yet. The Cache Write Pointer is advanced by the prefetch module when a prefetch request is initiated, and it also increments in a circular fashion.

[0055] For example, such as Figure 2 The diagram shows a circular cache. The circular cache is the internal storage structure of the prefetch module. This circular cache is an instruction cache using a circular buffer structure, containing N+1 cache lines (indices 0 to N). Cache index: The physical address index of the cache. Valid flag (0 / 1): Indicates whether the cache line stores valid instruction data. Cache line: The space actually storing the prefetched instruction data. The cache read pointer points to the cache line with cache index M, and the cache write pointer points to the cache line with cache index N.

[0056] The cache write pointer advance speed is decoupled from the cache read pointer speed, depending on the external storage access latency and prefetching strategy. The two pointers move independently within the circular space, maintaining a certain fill depth to preserve cache slack, thus preventing both empty cache reads and overwriting unused data.

[0057] For example, the region pointed to by the cache write pointer is used to load newly prefetched instructions; the cache write pointer advances after an instruction is written. The cache read pointer, on the other hand, moves as the decoding unit needs it, reading the instructions required by the corresponding thread group from the cache.

[0058] Because cache lines are coarse-grained (e.g., 64 bytes) while storage pointers are fine-grained (e.g., 4 bytes), when a storage pointer points to the middle of a cache line (e.g., the 32nd byte of the cache line), only part of the cache line may be valid (i.e., only the area pointed to by the pointer is currently needed), while the rest may be invalid or unused.

[0059] The cache start position indicates the position where prefetched data begins to be written to the cache. Validity information is used to determine whether the prefetched data is valid, thereby deciding whether to write it to the cache.

[0060] For example, such as Figure 3 The diagram shows a prefetch request identifier resource pool. The prefetch request identifier resource pool is the internal storage structure of the prefetch module. Identifier (0-K): A unique identifier for each prefetch request, i.e., the first prefetch request identifier. Instruction cache start position: The starting position for writing this prefetch request in the circular cache.

[0061] The prefetched data also carries a return sequence number. The return sequence number is the sequential number in which the prefetched data is stored in the cache. It is used to identify the order in which the data is returned, especially in cases where the data may be returned out of order, helping the control logic to correctly place the data in the correct location in the cache.

[0062] For example, if the return sequence number of the prefetched data is 2 and the cache start position in the corresponding status information is X, then the write position of the prefetched data is X+2 (assuming that each return sequence number corresponds to a fixed data unit length).

[0063] In practical implementation, when external memory returns a piece of prefetched data, the control logic (such as a cache controller) extracts the second prefetch request identifier and return sequence number carried in the prefetched data. Using the second prefetch request identifier as an index, it queries the prefetch request identifier resource pool to obtain the status information of the prefetch request, including validity information. Based on the validity information, it decides whether to perform the write: if valid, proceed to the next step; if invalid, skip the write.

[0064] Writes are performed only on valid data, ensuring the cache is filled with only the necessary data and improving utilization. The write position is calculated using the cache start position and the return sequence number, supporting out-of-order return scenarios.

[0065] Based on the cache start position and the return sequence number carried by the prefetched data, calculate its target write position in the circular cache; the calculation must ensure that when the target write position exceeds the end of the circular cache, it wraps back to the start position of the circular cache.

[0066] The calculation first adds the cache start position to the return sequence number to obtain an initial linear address. Then, this linear address is moduloed by the total cache length. This ensures that the write position represented by the calculated result always falls within the effective address range of the circular cache. When the initial linear address exceeds the end of the cache, the modulo operation wraps it back to the beginning of the cache, thus achieving circular reuse of addresses. For example, the write position can be calculated using the formula rtn_offset = (cache start position + return sequence number) % total cache length. The returned prefetched data is then written to the rtn_offset position in the cache.

[0067] The update of the cache write pointer is decoupled from the data write operation; it is pre-progressed when the prefetch request is initiated, rather than being driven by the data return write operation. After data is successfully written to the cache, only the validity state of the corresponding cache line is updated.

[0068] By utilizing the return sequence number and cache start position information carried by the prefetched data, the control logic can accurately calculate the predetermined write position of the out-of-order prefetched data in the cache, ensuring correct data storage, avoiding data misalignment, and guaranteeing data consistency.

[0069] By using the cache start position and the return sequence number carried by the prefetched data in combination, complete decoupling of the external address space and the internal cache space is achieved. The system no longer needs to maintain a fixed mapping relationship between external storage addresses and internal cache addresses. When data returns from external memory, its write position in the circular cache can be determined simply by calculating the offset of the return sequence number relative to the cache start position, completely unaffected by changes in external memory addresses.

[0070] The storage pointer corresponds to the large circular space of external memory, operating at the instruction word granularity, and is responsible for determining the data read source address. The cache pointer corresponds to the small circular buffer inside the memory, operating at the cache line granularity, and is responsible for managing the filling and consumption of the internal cache. This design bridges the two levels of storage spaces through prefetch logic, achieving a truly decoupled architecture. Pointer separation completely decouples the cache write pointer's advance speed from the cache read pointer's, allowing for independent adjustments based on external storage access latency and prefetch strategy, laying the foundation for handling multiple concurrent requests and out-of-order returns.

[0071] For example, such as Figure 4 The diagram shows a schematic of the memory storage structure. The left side is the pointer storage area, dedicated to storing pointer variables from external memory, physically separated from the instruction data area on the right. The storage address is a fixed storage location (e.g., PA, PB) allocated by the system for each pointer. The stored data is the actual value of the pointer. The PA address stores the instruction read pointer, and the PB address stores the instruction write pointer, reflecting the partitioned management concept of pointer data and instruction data. The right side is the circular instruction storage area, using a circular buffer structure to store the actual program instruction flow. The storage address is the linear address space of the instruction data. The stored data is the actual instruction code. When the address reaches the end, it wraps back to the beginning, achieving circular reuse. By storing critical pointers (PA, PB) as ordinary data in a separate memory area, a decoupled design is achieved, where the stored pointers only focus on the location of external memory reads and writes. This pointer separation completely decouples the advance speed of the cache write pointer from the cache read pointer.

[0072] This mechanism fully leverages the address wraparound characteristic of the circular cache, ensuring that the correct cache location can be accurately located regardless of the order in which data is returned. The cache start position serves as the logical starting point for the prefetch request within the circular cache, and together with the return sequence number, forms the location coordinates, effectively supporting the correct writing of data in out-of-order return scenarios.

[0073] Based on validity checks and precise location calculations, prefetch accuracy is significantly improved, ensuring that only valid data is stored in the cache. Secondly, leveraging the pipelining characteristics of a circular structure reduces boundary check overhead, forming a highly efficient pipelining of prefetching, writing, and fetching, thus improving overall access efficiency. Finally, through a pointer-decoupled architecture, it supports concurrent multi-request operations, out-of-order returns, and efficient operation in multi-threaded environments, overcoming the performance bottleneck of traditional FIFO (First In First Out) structures. These advantages work together to enable this application to maintain a high-speed, correct instruction stream supply in complex memory access scenarios, significantly optimizing processor data access performance.

[0074] In one optional embodiment of this application, the validity information includes a validity flag. A specific implementation of determining whether the prefetched data is valid or invalid based on the validity information may include: determining that the prefetched data is invalid based on the validity flag. Correspondingly, it may also include: performing a write rejection operation on the invalid prefetched data.

[0075] The validity flag indicates whether the entire prefetch request is valid. It can be a Boolean status value recorded in the prefetch request identifier resource pool. When the validity flag is "true", it indicates that the data corresponding to the request is still needed; when it is "false", it indicates that the entire request has failed. The validity flag provides a holistic judgment; once marked as invalid, all prefetched data returned by the prefetch request will be discarded.

[0076] For example, such as Figure 3 As shown, the valid flag (0 / 1) indicates whether the prefetch request is valid or invalid.

[0077] A no-fetch request is a prefetch request that is no longer needed due to an external event, such as a memory write pointer update or a decoder read request jump.

[0078] Rejecting a write operation is the final control action performed based on a failure decision. In essence, the cache control logic masks the write enable signal for the prefetched data, preventing it from entering the circular buffer and potentially triggering a discard operation.

[0079] If the validity flag is valid, the prefetch request is valid, meaning the prefetched data may be fully or partially valid. If the validity flag is invalid, the prefetch request is invalid, meaning all prefetched data is invalid.

[0080] When prefetched data is returned, the control logic queries the resource pool for a valid flag based on the second prefetch request identifier carried in the prefetched data. If the valid flag is "true", the request is considered valid. If the valid flag is "false", the request is considered invalid. For invalid requests, the control logic bypasses the normal write process and directly enters the data discarding stage, performing a write rejection operation.

[0081] For example, when a write pointer update or a read request jump from the decoding module unit invalidates the prefetched data, the control logic changes the validity flag of the corresponding prefetch request from a valid state (e.g., 1) to an invalid state (e.g., 0). When the external memory returns prefetched data, the control logic checks the validity flag corresponding to the second prefetch request identifier carried by the data. If the validity flag indicates that the request has expired, the control logic will not write the prefetched data to the cache, performing a write rejection operation, thereby avoiding cache pollution and waste.

[0082] This mechanism effectively solves the problem in existing technologies where prefetched data may become invalid due to changes in external conditions, but is still written to the cache, leading to cache pollution and reduced utilization. By promptly skipping the writing of invalid prefetched data, cache utilization and the overall performance of the prefetch module are improved.

[0083] In one optional embodiment of this application, the validity information includes a valid start position and a valid end position. A specific implementation of determining whether the prefetched data is valid or invalid based on the validity information may further include: determining the write position of the prefetched data based on the cache start position and the return sequence number; determining whether the prefetched data is valid or invalid based on the matching result between the write position of the prefetched data and the valid interval; wherein the valid interval is determined based on the valid start position and the valid end position. Correspondingly, it may also include: if the write position falls outside the interval from the valid start position to the valid end position, then a write rejection operation is performed.

[0084] The valid start position and valid end position are two key position values ​​recorded in the prefetch request identifier resource pool. Together, they define the valid range corresponding to the prefetch request in the internal cache. The valid start position indicates the starting cache position of valid data, and the valid end position indicates the ending position.

[0085] For example, such as Figure 3 As shown, the valid start position and valid end position define the valid range in the prefetch request identifier resource pool.

[0086] The valid range is not fixed and will be dynamically adjusted according to external events. Unlike the overall judgment of the valid flag, the valid start / end position provides fine-grained control and can handle complex scenarios where cache lines are partially valid and partially invalid.

[0087] The write position refers to the specific location where the prefetched data will be written to the circular buffer, which is calculated using the buffer start position and the return sequence number.

[0088] By comparing the position to be written with the valid start and end positions, it is determined whether the prefetched data returned for this transaction is still valid.

[0089] Check if rtn_offset satisfies: valid start position ≤ rtn_offset ≤ valid end position. If satisfied, the data is valid, and the write operation continues. If not satisfied, the data is invalid, and the write operation is rejected.

[0090] Because cache lines are coarse-grained (e.g., 64 bytes) while storage pointers are fine-grained (e.g., 4 bytes), when a storage pointer points to the middle of a cache line (e.g., the 32nd byte of the cache line), only part of the cache line may be valid (i.e., only the area pointed to by the pointer is currently needed), while the rest may be invalid or unused.

[0091] By managing the effective start and end positions with fine precision, the system addresses the management challenges arising from cache line granularity potentially being coarser than storage pointer granularity. A partial skip mechanism avoids the overhead of writing invalid data to the cache and subsequent processing, ensuring the most efficient use of cache space and improving cache efficiency. Support for complex scenarios with "partially valid, partially invalid" caches has been added, resolving the technical challenges caused by granularity mismatch in high-bandwidth systems. This adapts to the complexities of out-of-order and cross-line returns in storage systems, improving system robustness and instruction flow continuity.

[0092] In one optional embodiment of this application, the target event includes a storage write pointer update event. A specific method for updating the prefetch request status information in response to the detected target event may include: detecting the storage write pointer update event; determining a target prefetch request identifier in the prefetch request identifier resource pool whose valid interval includes the storage write pointer before the update, and target status information corresponding to the target prefetch request identifier; wherein the target status information includes target validity information; and updating the validity flag or valid end position in the target validity information according to the valid start position and valid end position in the target validity information.

[0093] A write pointer update event refers to a system event in which the location of the write pointer in external memory changes. Triggering conditions include external control logic operations such as dynamic loading of code segments, streaming execution, and write pointer forwarding. Write pointer updates may cause prefetch requests that have been issued but not yet returned to become invalid.

[0094] The write pointer before update refers to the external memory write position before the write pointer update event occurs.

[0095] The valid interval is a closed interval [valid start position, valid end position]. When the valid start position equals the valid end position, there is still one valid cache line.

[0096] In the prefetch request identifier resource pool, the prefetch request identifier whose valid range includes the storage write pointer before the update is denoted as the target prefetch request identifier. The target prefetch request identifier can be determined by comparing the storage write pointer before the update with the valid range of each prefetch request.

[0097] The target prefetch request identifier includes target validity information in the target status information, such as valid start position, valid end position, and validity flags. The validity information of the target prefetch request is dynamically adjusted based on the valid start and end positions.

[0098] Specifically, the storage write pointer is moved forward by external control logic, and the processing flow is triggered immediately upon detecting a change in the storage write pointer. It iterates through all in-use prefetch request identifiers in the resource pool, comparing the storage write pointer before the update with the valid range of each prefetch request. It then finds the target prefetch request identifier corresponding to the valid range containing the storage write pointer before the update.

[0099] An update strategy is selected based on the relationship between the valid start position and the valid end position to update the valid flag or valid end position in the target validity information.

[0100] For example, if the valid start position in the target validity information is equal to the valid end position, the value of the valid flag in the target validity information is changed to invalid.

[0101] For example, if the valid start position in the target validity information is not equal to the valid end position, the value of the valid end position in the target validity information is reduced by one.

[0102] By establishing a complete storage write pointer update response mechanism, the cache consistency and efficiency issues caused by the lack of dynamic invalidation processing in existing technologies are resolved. Timely invalidation of overwritten data avoids invalid data writes, ensures data consistency, improves bus bandwidth utilization, and enhances overall performance and cache efficiency.

[0103] In one optional embodiment of this application, a specific implementation of updating the validity flag in the target validity information based on the valid start position and valid end position in the target validity information may include: if the valid start position in the target validity information is equal to the valid end position, changing the value of the validity flag in the target validity information to invalid.

[0104] When the valid start position is equal to the valid end position, it means that the valid range of the target prefetch request contains only one cache line.

[0105] Change the validity flag of the record corresponding to the target prefetch request in the prefetch request identifier resource pool from "valid" to "invalid". Once the validity flag is set to invalid, all subsequent prefetch data for that target prefetch request will be discarded.

[0106] Specifically, upon receiving an update event for the storage write pointer, the system first compares the valid start position and valid end position in the target validity information. If the valid start position in the target validity information equals the valid end position, the value of the validity flag in the target validity information is changed to invalid.

[0107] For example, the storage write pointer might be updated due to external control logic, potentially pointing to a new location and overwriting a cached line containing prefetched data that was previously requested but not yet returned. Prefetch request ID17 initially has the following states: valid start position = 80, valid end position = 80, meaning it contains one valid cached line (line 80). When the storage write pointer is updated, the previous storage write pointer falls within the valid range [80, 80] of ID17. Since the valid start position of this prefetch request record is equal to the valid end position, and the updated storage write pointer invalidates this line (line 80), it is directly invalidated (the valid flag is changed to invalid). The system detects 80 == 80 and changes the value of the valid flag in the target status information to invalid. After this, any returned prefetched data carrying ID17 will be discarded.

[0108] By detecting when valid start and end positions are equal and performing complete invalidation, system resources occupied by completely invalidated requests are quickly released, improving resource utilization. Even in scenarios with dynamic updates to external storage or invalid requests, the cache maintains data consistency with external storage. This avoids further processing of invalid data, improving overall system performance.

[0109] In one optional embodiment of this application, a specific implementation of updating the valid end position in the target validity information based on the valid start position and valid end position in the target validity information may include: if the valid start position in the target validity information is not equal to the valid end position, subtracting a preset value from the value of the valid end position in the target validity information; and subtracting a preset value from the cache write pointer.

[0110] The valid interval is a closed interval. When the valid start position is not equal to the valid end position, it means that the valid interval of the prefetch request contains multiple cache lines (at least two). For example, the valid interval [100, 105] means that cache lines 100, 101, 102, 103, 104, and 105 are all valid.

[0111] Upon receiving a write pointer update event, the valid start position and valid end position in the target validity information are compared. If the valid start position in the target validity information is not equal to the valid end position, the value of the valid end position is reduced by a preset number of units (usually one cache line granularity, i.e., the preset value is 1). This is equivalent to backing the end boundary of the valid interval back by a preset number of units in the starting direction, excluding the portion covered by the previous storage write pointer. Furthermore, the cache write pointer position is backed back by a preset number of units to ensure that the cache write pointer is consistent with the actual end position of the valid interval.

[0112] For example, such as Figure 5The diagram illustrates the response mechanism for updating the memory write pointer. The system detects that the memory write pointer has moved from its original position (A2) to a new position (B2*). The affected prefetch request (identifier A) is identified, requesting the start position (A0) of identifier A. Since the valid start position (A1) of the requested identifier A is not equal to the valid end position (A2), the value of the valid end position (A2) of the requested identifier A is decremented by one, and the value is moved to the adjusted valid end position (A2*) of the requested identifier A. The newly allocated start position (A2) of identifier B coincides with the valid start position, and the adjusted valid end position (B2*) of the requested identifier B is the same as the new position of the memory write pointer.

[0113] For example, suppose the initial state of prefetch request ID18 is: valid start position = 200, valid end position = 207 (valid range of 8 cache lines). Cache write pointer = 208 (pointing to the next writable position). When a storage write pointer update event occurs, the storage write pointer before the update falls exactly within the valid range [200, 207] of ID18. The system detects that the valid start position (200) ≠ the valid end position (207), and executes: the valid end position is reduced from 207 to 206, and the cache write pointer is reduced from 208 to 207. At this time, the valid range becomes [200, 206], and the cache write pointer remains synchronized with the valid end position.

[0114] By precisely backing up the boundaries, the system excludes portions of memory that have been overwritten by the previous write pointer, preventing new data from overwriting valid data that has not yet been consumed. Only the truly needed instructions are retained, reducing cache pollution. After the valid range shrinks, the system can reissue prefetch requests based on the new write pointer to fill the updated area.

[0115] In one optional embodiment of this application, the target event includes a jump event. In a specific way of updating the state information of the prefetch request in response to the detected target event, it may include: obtaining a read request to read data from the circular cache; and updating the valid flag or valid start position of the prefetch request affected by the jump event based on the read request that caused the jump event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier.

[0116] A read request refers to a request by the decoding unit to read data (such as instructions) from its internal circular buffer. Normally, the process proceeds sequentially, but jumps may occur due to branching (including branch prediction errors), exception handling, etc.

[0117] In use, prefetch request identifiers refer to all prefetch request identifiers that are currently active (not yet completed) in the prefetch request identifier resource pool.

[0118] The system acquires read requests and detects instances of read request skipping. Specifically, it continuously monitors the sequence of read request addresses issued by the decoding unit, detects address discontinuities, and identifies skipping events when an address range is jumped.

[0119] Then, identify the prefetch requests affected by the jump event. Iterate through all in-use identifiers in the prefetch request identifier resource pool, comparing the addresses before and after the jump with the valid range (the range between the valid start and end positions) of each identifier. Identify prefetch requests whose valid range is partially or completely covered by the jump.

[0120] Finally, perform a validity update. The update strategy is selected based on the relationship between the jump range and the valid interval. For example, for complete skipping: set the valid flag to invalid. Another example is partial skipping: adjust the valid starting position.

[0121] For example, one scenario is: the valid range of the prefetch request identifier ID33 is [75, 85]. The decoder module's read request jumps directly from address 80 to address 90. Address 90 is outside the valid range [75, 85], meaning the entire valid range [75, 85] of the request has been skipped. The system sets the validity flag of ID33 directly to "invalid". All subsequent return data for this request will be discarded, and its identifier will be reclaimed. Another scenario is: the valid range of the prefetch request identifier ID33 is [75, 85]. The decoder module's read request jumps directly from address 80 to address 83. This jump is a partial skip. Address 83 still falls within the valid range [75, 85], so data within the range [75, 82] has been consumed or skipped, but data within the range [83, 85] may still be valid. Since it is triggered by a read request jump, the system updates the valid starting position of ID33 from 75 to the target address 83 of the jump. The new valid range becomes [83, 85].

[0122] By establishing a read request skip detection and response mechanism, skipped data can be discarded in a timely manner, improving the efficiency of cache space utilization and preventing skipped prefetched data from continuing to occupy cache space and transmission bandwidth. This can significantly improve the performance and efficiency of the system in dynamic execution environments, especially when dealing with complex scenarios such as branch prediction errors.

[0123] In one optional embodiment of this application, a specific implementation of updating the valid flag of the prefetch request affected by the jump event based on the read request that caused the jump event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier, may further include: determining the prefetch request that was completely skipped based on the read request that caused the jump event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier; and changing the value of the valid flag corresponding to the completely skipped prefetch request to invalid.

[0124] A prefetch request that is completely skipped means that the entire valid range of the prefetch request (from the valid start position to the valid end position) is completely before the new address range after the read request jumps, that is, all the data in the prefetch request has not been used and is no longer needed.

[0125] The specific criterion is that the new address after the read request jump is greater than or equal to the valid end position of the prefetch request plus one.

[0126] The validity flag of prefetch requests that will be completely skipped will be set to invalid. Once invalidated, any subsequent prefetch data returned by these prefetch requests will be automatically discarded.

[0127] By implementing a fast discard mechanism specifically designed for scenarios where data is completely skipped, the read request skipping handling system has been improved, reducing the overhead of processing invalid data and improving overall system performance.

[0128] In one optional embodiment of this application, a specific implementation of updating the valid start position of the prefetch request affected by the jump event based on the read request that triggered the jump event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier, may further include: determining the partially skipped prefetch request and the updated valid start position based on the read request that triggered the jump event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier; changing the value of the valid start position corresponding to the partially skipped prefetch request to the updated valid start position; and updating the cache read pointer based on the read request that triggered the jump event.

[0129] A partially skipped prefetch request refers to a read request where the skip event only affects a portion of the prefetch request's data. In other words, the valid range of the prefetch request is divided into valid and invalid parts by the skip address. Specifically, the skip address of the read request falls between the valid start and valid end positions of the prefetch request.

[0130] The updated valid starting position refers to the valid data starting boundary that needs to be re-established after a partial skip event occurs. It is usually set to the new address position after the read request skips.

[0131] After a read request jumps, the read pointer position of the circular cache needs to be updated synchronously to reflect the latest read position. This is a critical operation to ensure cache state consistency.

[0132] For example, such as Figure 6 The diagram illustrates the skip read response mechanism. It lists cache pointers (cache read pointer and cache write pointer) and some status information. Arrows precisely point to specific locations in the circular cache on the right, clearly showing the correspondence between each status pointer and a physical cache line. The cache read pointer points to a specific line in the circular cache (e.g., sequence number M), which is the starting point of the current instruction stream. The cache write pointer points to a specific line in the circular cache (e.g., sequence number N). The pointer group related to request identifier A (prefetch request identifier) ​​demonstrates the state adjustment process. The starting position of request identifier A is the original starting write position of prefetch request A. The original valid starting position of request identifier A (before adjustment) is the valid data start boundary of identifier A before the skip event occurs. The adjusted valid starting position of request identifier A is the new valid boundary dynamically calculated by the system after the read request skips. The valid ending position of request identifier A is the valid data ending boundary of identifier A. The pointer group for request identifier B is used for comparison and display, including the starting position, valid starting position, and valid ending position, to demonstrate the state management of multiple concurrent prefetch requests. The read request from the decoding module jumps (e.g., jumps directly from address A0 to A1*), causing the valid range of the original request identifier A to be partially skipped. The valid starting position of identifier A is adjusted from its original position to the adjusted position, and the cache read pointer is updated to the new position after the jump.

[0133] By implementing a refined boundary adjustment mechanism for partially skipped scenarios, the read request skipping processing system has been improved, solving the problem of precise management when some data becomes invalid, retaining the still valid data, and maximizing the utilization efficiency of cache space.

[0134] In one optional embodiment of this application, the status information further includes: a count of data that has not yet been returned, and may also include: updating the count of data that has not yet been returned whenever the external memory returns prefetched data.

[0135] The count of data not yet returned is a value recorded in the prefetch request identifier resource pool, representing the number of cached lines in the prefetch request that have not yet been returned from external storage. This count is a dynamically decreasing value, initially equal to the total number of cached lines in the prefetch request, and gradually decreases as data is returned. For example, as... Figure 3As shown, the counter records the number of data items that have not yet been returned for this prefetch request.

[0136] Each time prefetched data is returned, regardless of whether the prefetched data is valid, the count of data that has not yet been returned is decremented by 1 to ensure that the count accurately reflects the completion status of the prefetch request.

[0137] When initiating a prefetch request, set an initial counter value based on the prefetch length. For example, if prefetching 8 cache lines, set the initial counter value to 8.

[0138] The data return event serves as the sole trigger for the count update. The update operation and the data validity check are executed in parallel without interfering with each other.

[0139] By introducing a data counting and update mechanism for data that has not yet been returned, accurate tracking of the prefetch request status is achieved, solving the problem of lack of global state management in existing technologies and providing a basic guarantee for efficient resource management and system concurrency.

[0140] In one optional embodiment of this application, it may further include: when the count of data that has not yet been returned is reduced to zero, releasing the first prefetch request identifier back to the prefetch request identifier resource pool.

[0141] The "count of data not yet returned" recorded in the prefetch request identifier resource pool reaches a zero value after multiple updates.

[0142] A count of zero indicates that all data corresponding to the prefetch request has been returned from external memory (regardless of whether it is valid), and the request lifecycle has ended.

[0143] The first prefetch request that has completed its lifecycle is marked as available, so that it can be reassigned to a new prefetch request.

[0144] For example, such as Figure 7The flowchart shown illustrates the prefetch data processing procedure. External memory returns a data packet containing: data content: the actual instruction data; identifier: the request ID corresponding to the prefetch request identifier resource pool; sequence number: the sequential position of the data in the prefetch request. The valid flag corresponding to this identifier is queried in the prefetch request identifier resource pool. If the prefetch data is invalid, it is discarded, and the counter is decremented. If the value becomes zero after decrementing, the identifier is returned to the prefetch request identifier resource pool. If the prefetch data is valid, the returned sequence number is compared with the range from the valid start position to the valid end position. If the range does not contain the returned sequence number, the data is discarded, and the counter is decremented. If the value becomes zero after decrementing, the identifier is returned to the prefetch request identifier resource pool. If the range contains the returned sequence number, the returned prefetch data is read and filled into the row indicated by the ring instruction cache start position + returned sequence number in the prefetch request identifier resource pool. If this sum exceeds the number of rows in the ring cache, the total number of rows needs to be subtracted to achieve ring address wraparound. The counter is decremented. If the value becomes zero after decrementing by one, the identifier is returned to the prefetch request identifier resource pool. For example... Figure 8 The flowchart shown illustrates the read request processing of the decoding module. The system continuously monitors the instruction read requests from the decoding unit. It ensures that the requested data has been successfully prefetched from external memory and written to the cache. If the data is not yet valid, the system waits until the prefetch is complete. Valid instruction data from the cache is sent to the decoding unit for execution; upon completion of the read, the cache read pointer may be updated.

[0145] By implementing an automatic resource recycling mechanism based on a count of zero, the efficient recycling of prefetch request identifiers is achieved, solving the problems of extensive resource management and limited concurrency capabilities in existing technologies.

[0146] like Figure 9 The flowchart illustrating a prefetch request processing method, in an optional embodiment of this application, includes, in a specific implementation where a prefetch request is initiated to the external memory based on the address pointed to by the storage read pointer, and a first prefetch request identifier is allocated to the prefetch request in the prefetch request identifier resource pool, the following steps may be included: Step 201: Based on the storage read pointer, determine that the address space to be prefetched is a contiguous cache line.

[0147] Step 202: Based on the address pointed to by the storage read pointer, generate a burst prefetch request for retrieving multiple consecutive cache lines at once, and allocate an available first prefetch request identifier for the burst prefetch request in the prefetch request identifier resource pool.

[0148] Step 203: Send the burst prefetch request to the external memory.

[0149] A burst prefetch transmission optimization mechanism has been added to the above-mentioned basic prefetch management framework, specifically for performance optimization in scenarios involving continuous address access.

[0150] Because program access often exhibits spatial locality, there are frequent prefetching requirements for contiguous address blocks. Contiguous cache lines refer to multiple cache lines that are physically adjacent in the address space.

[0151] Multiple consecutive cache line prefetch requests are combined into a single large-scale transfer request, known as a burst prefetch request. Burst prefetch requests are used to fetch multiple consecutive cache lines at once, allowing multiple consecutive data units to be transferred within a single bus transaction, reducing transaction overhead.

[0152] There may be multiple cache lines between the storage read pointer and the storage write pointer. If only one cache line needs to be prefetched, then burst prefetching is not necessary. If multiple consecutive cache lines need to be prefetched, then instead of prefetching line by line, a single prefetch request should be initiated for the consecutive cache lines that need to be prefetched. In other words, multiple consecutive prefetch requests are optimized into a single burst prefetch request, enabling the reading of multiple lines at once.

[0153] When it is confirmed that there are consecutive cache lines that need to be prefetched, a burst prefetch request is generated directly, and its parameters (such as starting address and burst length) are set accurately.

[0154] Assign a single identifier to burst prefetch requests, that is, allocate an available first prefetch request identifier in the prefetch request identifier resource pool and record the merged status information.

[0155] For example, the storage read pointer points to position 100, and the storage write pointer points to position 120. The prefetch module determines that the address space [100, 115] is the contiguous cache lines that need to be prefetched. The system generates a burst prefetch request with a burst length of 15 lines and allocates an identifier ID 50 in the resource pool. Status information is recorded: start position = 100, valid start = 100, valid end = 114, count = 15. This burst request is proactively initiated by the prefetch module, ahead of the actual needs of the decoding unit.

[0156] Burst transmissions reduce bus transactions and improve bandwidth utilization, fully leveraging storage system performance. Merging requests reduces transaction overhead, lowers latency, and improves system response speed. Intelligent detection and merging mechanisms enable pipelining of prefetching, writing, and fetching operations.

[0157] In one optional embodiment of this application, a specific implementation of generating a burst prefetch request for retrieving multiple consecutive cache lines at once based on the address pointed to by the storage read pointer may include: determining the cache free capacity based on the cache read pointer and the cache write pointer; when the cache free capacity reaches a preset threshold, selecting the minimum value among the cache free capacity, the maximum burst length of the data bus, and the upper limit of the amount of data to be prefetched in the external memory as the burst length; modifying the cache write pointer to the value after increasing the burst length; and generating the burst prefetch request based on the address pointed to by the storage read pointer and the burst length.

[0158] Cache free capacity refers to the number of currently available cache lines, reflecting the available space in the cache. Cache free capacity can be calculated based on the relative positions of the cache read pointer (CRP) and cache write pointer (CWP), taking into account the wraparound characteristics of a circular cache.

[0159] The preset threshold is a threshold value set by the system. Its main purpose is to accumulate sufficient buffer free capacity to ensure that burst transmissions with significant benefits can be initiated, thereby avoiding low bandwidth utilization caused by frequent small-scale prefetching.

[0160] The maximum burst length of the data bus refers to the maximum amount of data (in buffer lines) that the data bus hardware can carry in a single transmission transaction. This is a physical limitation of the system, designed to prevent requests exceeding the bus's capacity, which could lead to transmission errors or reduced efficiency.

[0161] The upper limit of the amount of data to be prefetched refers to the maximum length of a continuous data block available for prefetching in the external memory. Specifically, it is the number of rows from the beginning of the data that has not yet been prefetched in the external memory to the row where the write pointer is located.

[0162] The minimum value among the available cache capacity, the maximum burst length of the data bus, and the upper limit of the amount of data to be prefetched in the external memory is selected as the burst length. This ensures that the final burst length will not exceed the limit in any dimension, which is a guarantee of the safety of the decision.

[0163] Advance the cache write pointer; the new CWP = original CWP + burst length. Record status information in the prefetch request identifier resource pool and initialize the count of data that has not yet been returned to the burst length.

[0164] The starting position of this prefetch is determined by the address pointed to by the memory read pointer, and then the number of cache lines to be fetched consecutively is determined by combining this with the calculated burst length. Based on these two key parameters, the system (prefetch logic) can assemble and generate a complete transfer instruction that requests external memory to return multiple consecutive cache lines of data at once.

[0165] For example, the system calculates that the current free cache capacity is 10 lines, and the preset threshold is 8 lines. Since 10 is greater than 8, the trigger condition is met. The system parameters are queried: the maximum burst length of the data bus is 8 lines, and the maximum amount of data to be prefetched from external memory is 15 lines. The minimum value is selected from the free cache capacity (10), the maximum burst length of the data bus (8), and the maximum amount of data to be prefetched (15), resulting in a burst length of 8 lines. Assume the original cache write pointer = 100, and the new pointer = 100 + 8 = 108. The initial value of the count of data not yet returned in the status information is set to the burst length, i.e., the initial count = 8. Thus, a burst prefetch request of length 8 is generated, and the system status is updated synchronously.

[0166] By employing a minimum-value decision based on triple constraints, overall flushing or blocking due to a full buffer is avoided, ensuring that all prefetch operations are performed within the system's safe capacity. It intelligently selects the maximum allowable burst length under the current environment, reducing bus transactions, improving bandwidth utilization, and fully leveraging hardware performance.

[0167] For example, such as Figure 10 The diagram illustrates the prefetch request processing flow. The signal from the decoding module serves as a unified event trigger entry point. A parallel dual-path approach is used: the left path is dedicated to handling memory write pointer update events, and the right path is dedicated to handling read request skip events. The process begins by checking the memory write pointer update from the decoding module, verifying that the valid range includes the memory write pointer prefetch request identifier. If its valid start position equals its valid end position, the valid flag is changed to 0; otherwise, the valid end position is decremented by 1, and the cache write pointer is decremented by 1. Next, the process checks the read requests from the decoding module, verifying the valid address range of each prefetch request identifier. If the request completely skips the request, the valid flag is changed to 0. If the preceding part is skipped, the valid start position is modified. The new cache free capacity is calculated based on the updated cache read / write pointers. If the free capacity exceeds a preset threshold, prefetch rule checks are performed. This ensures that burst transmissions are only initiated when there is sufficient cache space, preventing overflow. A smaller value is selected from the following as the burst length for read requests: the free capacity of the circular cache, the maximum burst length of the data bus, and the number of rows from the start of the unprefetched data to the row containing the write pointer. The prefetch request identifier resource pool records the start position, valid start position, and valid end position corresponding to the burst prefetch request. The initial value of the counter is the burst length, and the valid bit (valid flag) is 1. The cache write pointer is modified to increase the burst length value. If the sum exceeds the number of cache lines, the number of lines is subtracted.

[0168] It should be noted that the prefetch request processing method provided in this application embodiment can be executed by a prefetch request processing device, or a control module in the prefetch request processing device for executing the method of loading the prefetch request. This application embodiment uses the method of loading the prefetch request executed by a prefetch request processing device as an example to illustrate the prefetch request processing method provided in this application embodiment.

[0169] Reference Figure 11 The diagram illustrates a structural block diagram of a prefetch request processing apparatus embodiment provided in another embodiment of the present invention, which may specifically include: The request initiation module 301 is configured to initiate a prefetch request to the external memory according to the address indicated by the memory read pointer, and allocate a first prefetch request identifier for the prefetch request in the prefetch request identifier resource pool. The information update module 302 is used to update the status information of the prefetch request in response to the detected target event; the status information is used to characterize the validity of the prefetch data requested by the prefetch request. The status determination module 303 is used to query the prefetch request identifier that matches the second prefetch request identifier in the prefetch request identifier resource pool based on the second prefetch request identifier carried in the prefetch data returned by the external memory, and determine the corresponding status information based on the query result. The write control module 304 is used to determine whether the prefetched data is valid based on the status information, and to perform a write cache operation on the valid prefetched data.

[0170] Optionally, the status information includes: validity information and cache start position; the validity information is used to characterize the validity of the prefetched data requested by the prefetch request, and the cache start position is used to characterize the position where the prefetched data begins to be written into the cache; the write control module includes: The validity determination submodule is used to determine whether the prefetched data is valid or invalid based on the validity information. The write submodule is used to perform the write cache operation in the circular cache based on the cache start position and the return sequence number carried by the prefetch data if the prefetch data is valid.

[0171] Optionally, the validity information includes: a validity flag, and the validity determination submodule includes: A request determination unit is configured to determine that the prefetched data is invalid based on the validity flag. The device further includes: The first write rejection module is used to perform a write rejection operation on the invalid prefetched data.

[0172] Optionally, the validity information includes: a valid start position and a valid end position, and the validity determination submodule further includes: A position determination unit is used to determine the write position of the prefetched data based on the cache start position and the return sequence number; The validity determination unit is used to determine whether the prefetched data is valid or invalid based on the matching result between the writing position of the prefetched data and the valid interval; wherein, the valid interval is determined based on the valid start position and the valid end position; The device further includes: The second write rejection module is used to perform a write rejection operation if the position to be written falls outside the range from the valid start position to the valid end position.

[0173] Optionally, the target event includes an update event for storing the write pointer, and the request initiation module includes: The update detection submodule is used to detect update events of the storage write pointer; The information determination submodule is used to determine the target prefetch request identifier in the prefetch request identifier resource pool, which contains the storage write pointer before the update in the valid range, and the target status information corresponding to the target prefetch request identifier; wherein, the target status information includes target validity information; The first update submodule is used to update the valid flag or valid end position in the target validity information according to the valid start position and valid end position in the target validity information.

[0174] Optionally, the first update submodule includes: The first modification unit is used to change the value of the valid flag in the target validity information to invalid if the valid start position in the target validity information is equal to the valid end position.

[0175] Optionally, the first update submodule includes: The second modification unit is used to subtract a preset value from the value of the valid end position in the target validity information if the valid start position in the target validity information is not equal to the valid end position. The first pointer update unit is used to decrement the cache write pointer by a preset value.

[0176] Optionally, the target event includes a jump event, and the request initiation module includes: The read request acquisition submodule is used to acquire read requests for reading data from the circular cache; The second update submodule is used to update the valid flag or valid start position of the prefetch request affected by the jump event based on the read request that has experienced a jump event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier.

[0177] Optionally, the second update submodule further includes: The first request determination unit is used to determine the prefetch request that was completely skipped based on the read request that has a skip event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier. The third modification unit is used to change the value of the valid flag corresponding to the prefetch request that was completely skipped to invalid.

[0178] Optionally, the second update submodule further includes: The second request determination unit is used to determine the partially skipped prefetch request and the updated valid start position based on the read request that has a skipped event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier. The fourth modification unit is used to change the value of the valid start position corresponding to the partially skipped prefetch request to the updated valid start position; The second pointer update unit is used to update the cache read pointer based on the read request that has triggered a jump event.

[0179] Optionally, the status information further includes: a count of data that has not yet been returned; the device further includes: The count update module is used to update the count of data that has not yet been returned whenever the external memory returns prefetched data.

[0180] Optionally, the device further includes: The release module is used to release the first prefetch request identifier back to the prefetch request identifier resource pool when the count of data that has not yet been returned is reduced to zero.

[0181] Optionally, the request initiation module includes: The contiguous row determination submodule is used to determine, based on the storage read pointer, the address space to be prefetched as contiguous cache rows; The burst request generation submodule is used to generate a burst prefetch request for retrieving multiple consecutive cache lines at once based on the address pointed to by the storage read pointer, and to allocate an available first prefetch request identifier for the burst prefetch request in the prefetch request identifier resource pool. The request initiation submodule is used to send the burst prefetch request to the external memory.

[0182] Optionally, the burst request generation submodule includes: The capacity determination unit is used to determine the available cache capacity based on the cache read pointer and cache write pointer; The length determination unit is used to select the minimum value among the cache free capacity, the maximum burst length of the data bus, and the upper limit of the amount of data to be prefetched in the external memory as the burst length when the cache free capacity reaches a preset threshold. A pointer modification unit is used to modify the cache write pointer to a value increased by the burst length; The request generation unit is used to generate the burst prefetch request based on the address pointed to by the storage read pointer and the burst length.

[0183] According to the embodiments of this application, a prefetch request is first initiated to the external memory based on the address indicated by the storage read pointer. A first prefetch request identifier is allocated to the prefetch request in the prefetch request identifier resource pool. In response to a detected target event, the status information of the prefetch request is updated; the status information characterizes the validity of the prefetched data requested by the prefetch request. Then, based on the second prefetch request identifier carried in the prefetched data returned by the external memory, a first prefetch request identifier matching the second prefetch request identifier is queried in the prefetch request identifier resource pool. The corresponding status information is determined based on the query result. Finally, based on the status information, it is determined whether the prefetched data is valid, and a write cache operation is performed on the valid prefetched data. In this scheme, the status of each prefetch request is uniquely identified and tracked throughout the process by using the prefetch request identifier and status information in the prefetch request identifier resource pool. This allows for control of the write cache operation based on the status information when the prefetched data is returned, thereby dynamically identifying and discarding invalid data, avoiding cache pollution, ensuring that only valid data is stored in the cache, preventing invalid data from occupying cache space, and improving cache utilization.

[0184] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0185] Figure 12 This is a structural block diagram illustrating an electronic device 700 for processing prefetch requests according to an exemplary embodiment. For example, the electronic device 700 may be an in-vehicle computer, a computer, a digital broadcasting terminal, a messaging device, a game console, a medical device, a fitness device, etc.

[0186] Reference Figure 12The electronic device 700 may include one or more of the following components: a processing component 702, a memory 704, a power supply component 706, a multimedia component 708, an audio component 710, an input / output (I / O) interface 712, a sensor component 714, and a communication component 716.

[0187] Processing component 702 typically controls the overall operation of electronic device 700, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 702 may include one or more processors 720 to execute instructions to complete all or part of the steps of the methods described above. Furthermore, processing component 702 may include one or more modules to facilitate interaction between processing component 702 and other components. For example, processing component 702 may include a multimedia module to facilitate interaction between multimedia component 708 and processing component 702.

[0188] Memory 704 is configured to store various types of data to support the operation of device 700. Examples of this data include instructions for any application or method operating on electronic device 700, contact data, phonebook data, messages, pictures, videos, etc. Memory 704 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0189] Power supply component 706 provides power to various components of electronic device 700. Power supply component 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 700.

[0190] Multimedia component 708 includes a screen that provides an output interface between the electronic device 700 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 708 includes a front-facing camera and / or a rear-facing camera. When the electronic device 700 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0191] Audio component 710 is configured to output and / or input audio signals. For example, audio component 710 includes a microphone (MIC) configured to receive external audio signals when electronic device 700 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 704 or transmitted via communication component 716. In some embodiments, audio component 710 also includes a speaker for outputting audio signals.

[0192] I / O interface 712 provides an interface between processing component 702 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0193] Sensor assembly 714 includes one or more sensors for providing state assessments of various aspects of electronic device 700. For example, sensor assembly 714 may detect the on / off state of device 700, the relative positioning of components such as the display and keypad of electronic device 700, changes in position of electronic device 700 or a component of electronic device 700, the presence or absence of user contact with electronic device 700, orientation or acceleration / deceleration of electronic device 700, and temperature changes of electronic device 700. Sensor assembly 714 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 714 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 714 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0194] Communication component 716 is configured to facilitate wired or wireless communication between electronic device 700 and other devices. Electronic device 700 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 716 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 716 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0195] In an exemplary embodiment, the electronic device 700 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0196] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 704 including instructions, which can be executed by a processor 720 of an electronic device 700 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0197] A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a terminal's processor, enables the terminal to perform a prefetch request processing method, the method comprising: A prefetch request is initiated to the external memory according to the address indicated by the storage read pointer, and a first prefetch request identifier is allocated for the prefetch request in the prefetch request identifier resource pool; In response to a detected target event, the status information of the prefetch request is updated; the status information is used to characterize the validity of the prefetch data requested by the prefetch request. Based on the second prefetch request identifier carried in the prefetch data returned by the external memory, a first prefetch request identifier that matches the second prefetch request identifier is queried in the prefetch request identifier resource pool, and the corresponding status information is determined based on the query result; Based on the status information, determine whether the prefetched data is valid, and perform a write operation to the cache for valid prefetched data.

[0198] Optionally, the status information includes: validity information and cache start position; the validity information is used to characterize the validity of the prefetch data requested by the prefetch request, and the cache start position is used to characterize the position where the prefetch data begins to be written in the cache; The step of determining whether the prefetched data is valid based on the status information, and performing a write-to-cache operation on the valid prefetched data, includes: Based on the validity information, determine whether the prefetched data is valid or invalid; For valid prefetched data, the write cache operation is performed in the circular cache according to the cache start position and the return sequence number carried by the prefetched data.

[0199] Optionally, the validity information includes: a valid start position and a valid end position, and determining whether the prefetched data is valid or invalid based on the validity information further includes: The write position of the prefetched data is determined based on the cache start position and the return sequence number; Based on the matching result between the write position of the prefetched data and the valid interval, the prefetched data is determined to be valid or invalid; wherein, the valid interval is determined based on the valid start position and the valid end position; The method further includes: If the position to be written falls outside the range from the valid start position to the valid end position, a write rejection operation is performed.

[0200] Optionally, the target event includes an update event for storing the write pointer, and updating the state information of the prefetch request in response to the detected target event includes: Detect update events of the storage write pointer; In the prefetch request identifier resource pool, the effective range includes the target prefetch request identifier containing the storage write pointer before the update, and the target status information corresponding to the target prefetch request identifier; wherein, the target status information includes target validity information; Based on the valid start position and valid end position in the target validity information, the valid flag or valid end position in the target validity information is updated.

[0201] Optionally, updating the validity flag in the target validity information based on the valid start position and valid end position in the target validity information includes: If the valid start position in the target validity information is equal to the valid end position, the value of the valid flag in the target validity information is changed to invalid.

[0202] Optionally, updating the valid end position in the target validity information based on the valid start position and valid end position in the target validity information includes: If the valid start position in the target validity information is not equal to the valid end position, subtract a preset value from the value of the valid end position in the target validity information. Decrease the cache write pointer by the preset value.

[0203] Optionally, the target event includes a jump event, and updating the state information of the prefetch request in response to the detected target event includes: Obtain a read request to read data from the circular cache; Based on the read request that caused the jump event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier, the valid flag or valid start position of the prefetch request affected by the jump event is updated.

[0204] Optionally, updating the valid flag of the prefetch request affected by the jump event based on the read request that caused the jump event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start and valid end positions corresponding to the in-use prefetch request identifier, further includes: Based on the read request that caused the skip event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier, determine the prefetch request that was completely skipped. Change the value of the valid flag corresponding to the prefetch request that was completely skipped to invalid.

[0205] Optionally, updating the valid start position of the prefetch request affected by the jump event based on the read request that caused the jump event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier, further includes: Based on the read request that caused the skip event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier, determine the prefetch request that was partially skipped, and update the valid start position. Change the value of the valid start position corresponding to the partially skipped prefetch request to the updated valid start position; Update the cache read pointer based on the read request that triggered the jump event.

[0206] Optionally, the status information further includes: a count of data that has not yet been returned; the method further includes: Whenever the external memory returns prefetched data, the count of data that has not yet returned is updated.

[0207] Optionally, the method further includes: When the count of data that has not yet been returned is reduced to zero, the first prefetch request identifier is released back to the prefetch request identifier resource pool.

[0208] Optionally, the step of initiating a prefetch request to the external memory according to the address indicated by the storage read pointer, and allocating a first prefetch request identifier for the prefetch request in the prefetch request identifier resource pool, includes: Based on the storage read pointer, the address space that needs to be prefetched is determined to be a contiguous cache line; Based on the address pointed to by the storage read pointer, a burst prefetch request is generated to retrieve multiple consecutive cache lines at once, and an available first prefetch request identifier is allocated for the burst prefetch request in the prefetch request identifier resource pool. The burst prefetch request is sent to the external memory.

[0209] Optionally, generating a burst prefetch request for retrieving multiple consecutive cache lines at once, based on the address pointed to by the storage read pointer, includes: Determine the available cache capacity based on the cache read pointer and cache write pointer; When the cache free capacity reaches a preset threshold, the minimum value among the cache free capacity, the maximum burst length of the data bus, and the upper limit of the amount of data to be prefetched in the external memory is selected as the burst length. Modify the cache write pointer to the value after increasing the burst length; The burst prefetch request is generated based on the address pointed to by the storage read pointer and the burst length.

[0210] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0211] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0212] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0213] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0214] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0215] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0216] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0217] The foregoing has provided a detailed description of a prefetch request processing method, a prefetch request processing apparatus, an electronic device, and a readable storage medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for processing prefetch requests, characterized in that, The method includes: A prefetch request is initiated to the external memory according to the address indicated by the storage read pointer, and a first prefetch request identifier is allocated for the prefetch request in the prefetch request identifier resource pool; In response to a detected target event, the status information of the prefetch request is updated; the status information is used to characterize the validity of the prefetch data requested by the prefetch request. Based on the second prefetch request identifier carried in the prefetch data returned by the external memory, a first prefetch request identifier that matches the second prefetch request identifier is queried in the prefetch request identifier resource pool, and the corresponding status information is determined based on the query result; Based on the status information, determine whether the prefetched data is valid, and perform a write operation to the cache for valid prefetched data.

2. The method according to claim 1, characterized in that, The status information includes: validity information and cache start position; the validity information is used to characterize the validity of the prefetch data requested by the prefetch request, and the cache start position is used to characterize the position where the prefetch data begins to be written in the cache; The step of determining whether the prefetched data is valid based on the status information, and performing a write-to-cache operation on the valid prefetched data, includes: Based on the validity information, determine whether the prefetched data is valid or invalid; For valid prefetched data, the write cache operation is performed in the circular cache according to the cache start position and the return sequence number carried by the prefetched data.

3. The method according to claim 2, characterized in that, The validity information includes: a valid start position and a valid end position. Determining whether the prefetched data is valid or invalid based on the validity information further includes: The write position of the prefetched data is determined based on the cache start position and the return sequence number; Based on the matching result between the write position of the prefetched data and the valid interval, the prefetched data is determined to be valid or invalid; wherein, the valid interval is determined based on the valid start position and the valid end position; The method further includes: If the position to be written falls outside the range from the valid start position to the valid end position, a write rejection operation is performed.

4. The method according to claim 3, characterized in that, The target event includes an update event for storing the write pointer, and the step of updating the state information of the prefetch request in response to the detected target event includes: Detect update events of the storage write pointer; In the prefetch request identifier resource pool, the effective range includes the target prefetch request identifier containing the storage write pointer before the update, and the target status information corresponding to the target prefetch request identifier; wherein, the target status information includes target validity information; Based on the valid start position and valid end position in the target validity information, the valid flag or valid end position in the target validity information is updated.

5. The method according to claim 4, characterized in that, The step of updating the validity flag in the target validity information based on the valid start position and valid end position in the target validity information includes: If the valid start position in the target validity information is equal to the valid end position, the value of the valid flag in the target validity information is changed to invalid.

6. The method according to claim 4, characterized in that, The step of updating the valid end position in the target validity information based on the valid start position and valid end position in the target validity information includes: If the valid start position in the target validity information is not equal to the valid end position, subtract a preset value from the value of the valid end position in the target validity information. Decrement the cache write pointer by the preset value.

7. The method according to claim 3, characterized in that, The target event includes a jump event, and the step of updating the state information of the prefetch request in response to the detected target event includes: Obtain a read request to read data from the circular cache; Based on the read request that caused the jump event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier, the valid flag or valid start position of the prefetch request affected by the jump event is updated.

8. The method according to claim 7, characterized in that, The step of updating the valid flag of the prefetch request affected by the jump event based on the read request that caused the jump event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier, further includes: Based on the read request that caused the skip event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier, determine the prefetch request that was completely skipped. Change the value of the valid flag corresponding to the prefetch request that was completely skipped to invalid.

9. The method according to claim 7, characterized in that, The step of updating the valid start position of the prefetch request affected by the jump event based on the read request that triggered the jump event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier, further includes: Based on the read request that caused the skip event, the in-use prefetch request identifier in the prefetch request identifier resource pool, and the valid start position and valid end position corresponding to the in-use prefetch request identifier, determine the prefetch request that was partially skipped, and update the valid start position. Change the value of the valid start position corresponding to the partially skipped prefetch request to the updated valid start position; Update the cache read pointer based on the read request that triggered the jump event.

10. The method according to any one of claims 1-9, characterized in that, The status information also includes: a count of data that has not yet been returned; the method further includes: Whenever the external memory returns prefetched data, the count of data that has not yet returned is updated.

11. The method according to claim 10, characterized in that, The method further includes: When the count of data that has not yet been returned is reduced to zero, the first prefetch request identifier is released back to the prefetch request identifier resource pool.

12. The method according to any one of claims 1-9, characterized in that, The step of initiating a prefetch request to external memory based on the address indicated by the storage read pointer, and allocating a first prefetch request identifier for the prefetch request in the prefetch request identifier resource pool, includes: Based on the storage read pointer, the address space that needs to be prefetched is determined to be a contiguous cache line; Based on the address pointed to by the storage read pointer, a burst prefetch request is generated to retrieve multiple consecutive cache lines at once, and an available first prefetch request identifier is allocated for the burst prefetch request in the prefetch request identifier resource pool. The burst prefetch request is sent to the external memory.

13. The method according to claim 12, characterized in that, The step of generating a burst prefetch request for retrieving multiple consecutive cache lines at once, based on the address pointed to by the storage read pointer, includes: Determine the available cache capacity based on the cache read pointer and cache write pointer; When the cache free capacity reaches a preset threshold, the minimum value among the cache free capacity, the maximum burst length of the data bus, and the upper limit of the amount of data to be prefetched in the external memory is selected as the burst length. Modify the cache write pointer to the value after increasing the burst length; The burst prefetch request is generated based on the address pointed to by the storage read pointer and the burst length.

14. A prefetch request processing apparatus, characterized in that, The device includes: The request initiation module is used to initiate a prefetch request to the external memory according to the address indicated by the storage read pointer, and to allocate a first prefetch request identifier for the prefetch request in the prefetch request identifier resource pool; An information update module is used to update the status information of the prefetch request in response to a detected target event; the status information is used to characterize the validity of the prefetch data requested by the prefetch request. The status determination module is used to query the prefetch request identifier that matches the second prefetch request identifier in the prefetch request identifier resource pool based on the second prefetch request identifier carried in the prefetch data returned by the external memory, and determine the corresponding status information based on the query result. The write control module is used to determine whether the prefetched data is valid based on the status information, and to perform a write cache operation on the valid prefetched data.

15. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the prefetch request processing method as described in any one of claims 1-13.

16. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the prefetch request processing method as described in any one of claims 1-13.

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