Cache missing request processing method and missing state keeping register

Abstract

The embodiment of the invention discloses a cache missing request processing method and a missing state keeping register. A cache missing request management mode based on a linked list is combined with a cache missing request management mode based on class first-in first-out, and identification information is introduced to represent the entry state of a corresponding entry in the linked list, so that an entry which needs to be released currently is selected based on the identification information; according to the embodiment of the invention, on the premise of ensuring that the cache line missing requests for the same cache address are processed prior to the cache block missing requests, the cache missing requests are sequentially processed as much as possible according to the arrival sequence, and meanwhile, the area overhead caused by processing the cache missing requests is reduced.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically, to a cached missing request processing method and a missing status holding register. Background Technology

[0002] The Miss Status Holding Register (MSHR) is a hardware structure used to record and manage cache miss requests, which can support concurrent miss handling and data backfill coordination in non-blocking caches.

[0003] When handling cache miss requests, existing miss status registers typically represent each cache miss request with a separate entry, storing these entries in a linked list. Then, they release each entry in the linked list, batch processing the cache miss requests represented by each released entry. This cache miss request handling method cannot ensure that cacheline misses for the same cache address are processed before sector misses, thus failing to guarantee that cache miss requests are processed sequentially based on their arrival order. Furthermore, to ensure that cacheline misses for the same cache address are processed before sector misses, existing miss status registers need to compare the cache address of the entry representing a sector miss with the cache addresses of all stored entries when releasing the entry representing a sector miss, resulting in significant area overhead. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a cache miss request processing method and a miss status holding register, so as to ensure that cache line miss requests for the same cache address are processed before cache block miss requests, and that each cache miss request is processed in the order of arrival as much as possible, while reducing the area overhead caused by processing cache miss requests.

[0005] In a first aspect, embodiments of the present invention aim to provide a method for handling cached missing requests, the method comprising: Starting with the entry with the earliest storage time, the system traverses multiple entries in storage time order to determine the target entry. These multiple entries are stored in a linked list, with each linked list containing a first entry and a corresponding second entry. The first entry represents a cache block miss request, and the second entry represents a cache line miss request. Each first entry has corresponding first identifier information, which indicates whether all second entries corresponding to the first entry have been released. The target entry is the first entry encountered that satisfies the execution conditions. The execution conditions include the entry being either the second entry or the entry being the first entry whose corresponding second entries have been released as indicated by the first identifier information. Generate request execution instruction information corresponding to the target entry to instruct the execution of the cache missing request corresponding to the target entry.

[0006] Secondly, embodiments of the present invention aim to provide a cache missing request processing apparatus, the apparatus comprising: The target entry determination unit is used to traverse multiple stored entries in storage time order, starting from the entry with the earliest storage time, to determine the target entry. The multiple entries are stored in a linked list, with each linked list including a first entry and a corresponding second entry. The first entry represents a cache block miss request, and the second entry represents a cache line miss request. Each first entry has corresponding first identifier information, which indicates whether all second entries corresponding to the first entry have been released. The target entry is the first entry encountered that satisfies the execution condition, which includes the entry being either the second entry or the entry being the first entry whose corresponding second entries have been released as indicated by the first identifier information. An execution instruction information generation unit is used to generate request execution instruction information corresponding to the target entry, so as to instruct the execution of the cache missing request corresponding to the target entry.

[0007] Thirdly, embodiments of the present invention aim to provide a missing state holding register, configured in a cache, the missing state holding register comprising: Entry storage, used for storing entries; An address comparator is used to compare the cache addresses of the entries stored in the entry memory; A controller for performing the methods described in the first aspect.

[0008] Fourthly, embodiments of the present invention aim to provide a cache, the cache comprising: The caching interface is used to receive multiple data access requests to memory. The hit test unit is used to determine whether each data access request hits the corresponding cache, so as to generate a cache miss request; Missing state holding register as described in the third aspect.

[0009] Fifthly, embodiments of the present invention aim to provide a computer system, the system comprising: The cache as described in the fourth aspect; A computing engine is used to generate data access requests and send the data access requests to the cache.

[0010] In this embodiment of the invention, the earliest stored entry is used as the starting point for traversal. Multiple stored entries are traversed in chronological order to determine the target entry. Then, request execution instruction information corresponding to the target entry is generated to instruct the execution of the cache miss request corresponding to the target entry. Multiple entries are stored in a linked list, with each linked list including a first entry and a corresponding second entry. The first entry represents a cache block miss request, and the second entry represents a cache line miss request. Each first entry has corresponding first identifier information, indicating whether all second entries corresponding to the first entry have been released. The target entry is the first entry encountered that satisfies the execution conditions. The execution conditions include the entry being a second entry or the entry being a first entry whose first identifier indicates that all corresponding second entries have been released. Therefore, by combining a linked list-based cache miss request management method with a class-first-in-first-out cache miss request management method, and introducing identification information to characterize the entry status of the corresponding entries in the linked list, and selecting the entry that needs to be released based on the identification information, this embodiment of the invention can ensure that cache line miss requests for the same cache address are processed before cache block miss requests, while ensuring that each cache miss request is processed in the order of arrival, and at the same time reducing the area overhead caused by processing cache miss requests. Attached Figure Description

[0011] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a schematic diagram illustrating the triggering process of a cache miss request according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the entry storage of the missing state holding register according to an embodiment of the present invention; Figure 3 This is a flowchart of the cache missing request handling method in an embodiment of the present invention; Figure 4 This is a schematic diagram of the entry storage of the missing state holding register according to an embodiment of the present invention; Figure 5This is a schematic diagram of the entry storage of the missing state holding register according to an embodiment of the present invention; Figure 6 This is a flowchart of the entry determination method according to an embodiment of the present invention; Figures 7 to 11 This is a schematic diagram of the entry release process according to an embodiment of the present invention; Figure 12 This is a schematic diagram of a cache missing request processing device according to an embodiment of the present invention; Figure 13 This is a schematic diagram of a missing state holding register according to an embodiment of the present invention; Figure 14 This is a schematic diagram of a high-speed cache according to an embodiment of the present invention; Figure 15 This is a schematic diagram of a computer system according to an embodiment of the present invention. Detailed Implementation

[0012] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0013] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0014] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0015] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0016] The solutions described in this specification and embodiments, if involving the processing of personal information, will be processed only on the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be processed within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

[0017] A cache is a high-speed memory integrated within a processor chip. It is used to temporarily store frequently accessed instructions or data, thereby reducing the number of accesses to high-latency main memory or peripherals and significantly improving overall system performance.

[0018] Currently, to allow for finer-grained data management and replacement, thereby improving spatial locality utilization efficiency and reducing bandwidth overhead, in relevant-level caches, such as last-level caches (LLC), a cache line can be divided into multiple (e.g., two) fixed-size sectors. Correspondingly, this multi-sector partitioning of a cache line allows a missed access to the same cache line to trigger two different types of cache miss requests. Specifically, when accessing a cache line, the program can first access any one sector within the cache line, and then access the other sectors. A missed access to the first sector and subsequent consecutive missed accesses to that sector can trigger a cache line miss request. Furthermore, after triggering a cache line miss request, a missed access to other sectors, or a missed access to the first sector after missing accesses to other sectors, can trigger a cache block miss request. A cache line miss request can be used to instruct the cache to internally allocate a cache line and request the required missed data from memory. A cache block miss request can be used to indicate that the cache is requesting the missing data from memory. It's important to note that, in order to pre-allocate cache lines in the cache and ensure that cache block miss requests can be processed correctly, cache line miss requests for the same cache line typically need to be processed before cache block miss requests.

[0019] To achieve the above conditions, in related technologies, when processing cache miss requests, the miss status register typically represents each cache miss request with a corresponding entry. Then, for cache miss requests (whether cache line miss requests or cache block miss requests) that represent multiple entries for the same cache line, the miss status register can store them in the form of a linked list. Furthermore, when it is necessary to release internal entries, the miss status register can release each entry included in the linked list on a per-list basis, thereby batch processing the cache miss requests represented by each released entry.

[0020] Figure 1 This is a schematic diagram illustrating the triggering process of a cache miss request according to an embodiment of the present invention. Figure 1As shown, the cache line includes Sector 1 and Sector 2. When accessing this cache line, the program can first access Sector 1 and then Sector 2. The initial miss on Sector 1 and subsequent consecutive misses on Sector 1 can trigger cache line miss request A and cache line miss request B, respectively. Furthermore, after triggering a cache line miss request, a miss on Sector 2 and a miss on Sector 1 after a miss on Sector 2 can trigger cache block miss requests C, D, and E, respectively. For cache miss requests A, B, C, D, and E, the miss status register can represent them as entries a, b, c, d, and e, respectively. Moreover, since cache miss requests A, B, C, D, and E target the same cache line, the miss status register can store entries a, b, c, d, and e in a linked list.

[0021] Figure 2 This is a schematic diagram illustrating the storage of entries in the missing state holding register according to an embodiment of the present invention. It is intended to illustrate that... Figure 2 The content shown can be specifically... Figure 1 The diagram illustrates the storage of entries a, b, c, d, and e in the missing state holding register. Entries a and b can represent cache line missing requests. Entries c, d, and e can represent cache block missing requests. For ease of distinction, Figure 2 In this context, entries a and b, representing cache line miss requests, and entries c, d, and e, representing cache block miss requests, are represented by squares filled with different colors. For example... Figure 2 As shown, entries a, b, c, d, and e can be stored in the missing status register as a linked list. It's important to note that the entries stored in the missing status register are typically arranged in order of storage time (which can also be understood as the time the entry was created, or the time the missing status register received the cache missing request represented by the entry). Therefore, for multiple entries representing the same cache missing request for the same cache line, although stored as a linked list, their storage positions in the missing status register are not contiguous (for example, there are corresponding numbers of entries from other linked lists between entries a and c, and between entries c and b).

[0022] For ease of understanding, Figure 2Taking the linked list containing entries a, b, c, d, and e as an example, in related technologies, when the missing status holding register releases internal entries, it releases entries a, b, c, d, and e sequentially in the linked list, on a list-by-list basis, to batch process the cache miss requests represented by each released entry. This ensures that cache line miss requests A and B for the same cache line are processed before cache block miss requests C, D, and E. However, while this cache miss request processing method in related technologies ensures that cache line miss requests for the same cache address are processed before cache block miss requests, it cannot ensure that cache miss requests are processed sequentially according to their arrival order. For example, if entry x is stored earlier than entries b, c, d, and e, but the linked list containing entries b, c, d, and e is released before the linked list containing entry x, the cache miss requests represented by entries b, c, d, and e will be processed before the cache miss request represented by entry x. This out-of-order cache miss request processing is detrimental to the execution efficiency of upstream processes. Meanwhile, to ensure that cache line miss requests for the same cache address are processed before cache block miss requests, this cache miss request handling method in related technologies requires comparing the request address of an entry representing a cache block miss request with the request addresses of all stored entries when releasing the entry, which also leads to significant area overhead. For example, when releasing entry c representing a cache block miss request, the miss status holding register needs to compare the request address of entry c with the request addresses of all stored entries to determine whether its corresponding cache line miss requests have all been processed.

[0023] Therefore, in view of the above-mentioned problems existing in related technologies, the present invention provides a cache miss request processing method and a miss status holding register, so as to ensure that cache line miss requests for the same cache address are processed before cache block miss requests, and that each cache miss request is processed in the order of arrival as much as possible, while reducing the area overhead caused by processing cache miss requests.

[0024] Figure 3 This is a flowchart of a cached missing request handling method according to an embodiment of the present invention. It is intended to illustrate that... Figure 3 The execution body of the cache missing request handling method shown can be a missing status holding register. This is achieved by executing, as... Figure 3The cache miss request handling method described herein combines a linked list-based cache miss request management approach with a class-first-in-first-out (FIFO) cache miss request management approach. It introduces identification information to characterize the entry status of the corresponding entries in the linked list, allowing the selection of the entry to be released based on this identification information. This ensures that cache line miss requests for the same cache address are processed before cache block miss requests, while also minimizing the area overhead associated with handling cache miss requests. For example... Figure 3 As shown, the cache missing request handling method may specifically include the following steps: Step S100: Using the entry with the earliest storage time as the starting point for traversal, traverse the multiple stored entries in order of storage time to determine the target entry.

[0025] Specifically, the missing status holding register can use the earliest stored entry as the traversal starting point and traverse multiple stored entries in chronological order to determine the target entry. These multiple entries can be stored in a linked list. The same linked list can include a first entry and a corresponding second entry; the first entry can represent a cache block missing request, and the second entry can represent a cache line missing request. Further, in this embodiment, each first entry can have corresponding first identifier information, which can be used to indicate whether all second entries corresponding to the first entry have been released. The target entry can be the determined entry that currently needs to be released. Specifically, the target entry can be the first entry encountered that satisfies the execution conditions. The execution conditions can include the entry being a second entry or the entry being a first entry whose first identifier information indicates that all corresponding second entries have been released.

[0026] Optionally, as one implementation, the first identification information can be embedded as information content within the entry information corresponding to the entry itself. Alternatively, as another implementation, the first identification information can be stored in a separate dedicated hardware memory; this application does not limit its specific implementation. Furthermore, as a representation method, the information content of the first identification information can be set to include corresponding binary characters or binary strings to represent whether all second entries corresponding to the first entry have been released. Indicatively, the information content of the first identification information can be set to include binary characters "0" or "1". Wherein, a binary character "0" in the first identification information can be used to represent that not all second entries corresponding to the first entry have been released. A binary character "1" in the first identification information can be used to represent that all second entries corresponding to the first entry have been released.

[0027] Optionally, in this embodiment of the invention, the entries inside the missing status holding register are typically arranged in order of storage time, and the missing status holding register may be configured with a read pointer pointing to the entry with the earliest storage time. As one implementation, in step S100, the missing status holding register can determine the entry with the earliest storage time among multiple entries based on the read pointer. Furthermore, the missing status holding register can use the entry with the earliest storage time as the traversal starting point and traverse the multiple stored entries in order of storage location. During the traversal process, the missing status holding register can determine the first second entry encountered or the first entry whose corresponding second entries are all released based on the first identifier information as the target entry. It should be noted that in practical applications, to facilitate the confirmation of the entry with the latest storage time, the missing status holding register may be configured with a write pointer pointing to the entry with the latest storage time; this application does not impose any limitations on this.

[0028] Figure 4 This is a schematic diagram illustrating the entry storage of the missing state holding register according to an embodiment of the present invention. Figure 4 As shown, the multiple entries stored in the missing status holding register may include entries b, c, d, e, j, k, and l. Entries b, c, d, and e may belong to one linked list, while entries j, k, and l may belong to another linked list. Furthermore, as entries representing cache block missing requests, entries c, d, e, k, and l may each have corresponding first identifier information. It is worth noting that, here, since the corresponding entry j has not been released, the first identifier information of entries k and l of entry j can represent that each of the second entries corresponding to the first entry has not been fully released. Similarly, since the corresponding entry b has not been released, the first identifier information of entries c, d, and e of entry b can represent that each of the second entries corresponding to the first entry has not been fully released.

[0029] In this scenario, when the target entry needs to be determined, the missing status holding register can first determine the earliest stored entry *c* from among the stored entries based on the read pointer *Rptr*. Then, after determining the earliest stored entry *c*, the missing status holding register can use entry *c* as the starting point for traversal and begin traversing the stored entries in order of their storage location. Specifically, for entry *c*, since the first identifier information of entry *c* indicates that all the corresponding second entries have not been released, the missing status holding register can continue traversing to entry *l*. For entry *l*, since the first identifier information of entry *l* indicates that all the corresponding second entries have not been released, the missing status holding register can continue traversing to entry *j*. For entry *j*, since entry *j* is the second entry representing a cache line missing request, the missing status holding register can identify it as the target entry and end the traversal.

[0030] Figure 5 This is a schematic diagram illustrating the entry storage of the missing state holding register according to an embodiment of the present invention. Figure 5 As shown, the missing status holding register can store multiple entries, including entries b, c, d, e, k, and l. Entries b, c, d, and e can belong to one linked list, while entries k and l can belong to another linked list. Furthermore, as entries representing cache block missing requests, entries c, d, e, k, and l can each have corresponding first identifier information. It is worth noting that, since all second entries in their respective linked lists have been released, the first identifier information of entries k and l can indicate that all second entries corresponding to the first entry have been released. Since the corresponding entry b has not been released, the first identifier information of entries c, d, and e can indicate that not all second entries corresponding to the first entry have been released.

[0031] In this scenario, when it is necessary to determine the target entry, the missing status holding register can first determine the earliest stored entry *c* from the stored entries based on the read pointer *Rptr*. Then, after determining the earliest stored entry *c*, the missing status holding register can use entry *c* as the starting point and begin traversing the stored entries in order of their storage locations. For entry *c*, since the first identifier information of entry *c* indicates that all the corresponding second entries have not been released, the missing status holding register can continue traversing until it reaches entry *l*. For entry *l*, since entry *l* is the first entry whose first identifier information indicates that all the corresponding second entries have been released, the missing status holding register can determine it as the target entry and end the traversal.

[0032] Optionally, in this embodiment of the invention, the missing status holding register can only further migrate the missed data in the cache line from memory or the corresponding level cache to the target level cache after the cache line has been read or written to memory or the corresponding level cache. Based on this, to ensure that cache miss requests can be processed only after the cache line has been read or written to memory or the corresponding level cache, the entry representing a cache miss request (whether it's a cache line miss request or a cache block miss request) needs to be released only after the corresponding waiting data arrives. As one implementation method, in addition to the first identification information, each entry can also have corresponding second identification information. The second identification information can be used to indicate whether the waiting data corresponding to the entry has been returned. Correspondingly, the execution condition can also include the second identification information of the entry used to indicate that the waiting data corresponding to the entry has been returned. Specifically, when determining the target entry, whether the corresponding first entry or the corresponding second entry is determined as the target entry, the missing status holding register needs to ensure that the second identification information of the determined target entry indicates that the waiting data corresponding to the entry has been returned.

[0033] Optionally, similar to the first identification information, as one implementation, the second identification information can be embedded as information content within the entry information corresponding to the entry itself. Alternatively, as another implementation, the second identification information can be stored in a separate dedicated hardware memory; this application does not limit its specific implementation. Furthermore, as a representation method, the information content of the second identification information can be set to include corresponding binary characters or binary strings to represent whether the waiting data corresponding to the entry has been returned. Indicatively, the information content of the second identification information can be set to include binary characters "0" or "1". Wherein, the information content of the second identification information being the binary character "0" can be used to represent that the waiting data corresponding to the entry has not yet been returned. The information content of the second identification information being the binary character "1" can be used to represent that the waiting data corresponding to the entry has been returned.

[0034] Optionally, in this embodiment of the invention, cache miss requests can have different request operation types, such as read operations, write operations, and atomic operations. For atomic operations, a cache line undergoing an atomic operation cannot be simultaneously subjected to other operations. That is, when a cache line is undergoing an atomic operation, for that cache line, only cache miss requests of consecutive atomic operation types can be processed; other types of cache miss requests need to be paused. Therefore, to ensure that other types of cache miss requests can be paused when a cache line is undergoing an atomic operation, as an implementation method, in addition to the first and second identification information, each entry can also have corresponding third identification information. The third identification information can be used to indicate whether there is an incomplete prior atomic operation entry in the linked list where the entry is located. Correspondingly, the execution condition can also include the third identification information of the entry indicating that there is no incomplete prior atomic operation entry in the linked list where the entry is located, or that there is an incomplete prior atomic operation entry in the linked list where the entry is located, but the entry is an atomic operation entry adjacent to the prior atomic operation entry. Specifically, when determining the target entry, whether the corresponding first entry or the corresponding second entry is determined as the target entry, the missing state holding register must ensure that there is no prior atomic operation entry that is not yet completed in the linked list where the third identification information characterizes the target entry, or ensure that there is a prior atomic operation entry that is not yet completed in the linked list where the third identification information characterizes the target entry, but the entry is an atomic operation entry adjacent to the prior atomic operation entry.

[0035] Optionally, similar to the first and second identification information, as one implementation, the third identification information can be embedded as information content within the entry information corresponding to the entry itself. Alternatively, as another implementation, the third identification information can be stored in a separate dedicated hardware memory; this application does not limit its specific implementation. Furthermore, as a representation method, the information content of the third identification information can be set to include corresponding binary characters or binary strings to represent whether there are any incomplete prior atomic operation entries in the linked list where the entry is located. Schematic, the information content of the third identification information can be set to include binary characters "0" or "1". Wherein, the information content of the third identification information being the binary character "0" can be used to represent that there are no incomplete prior atomic operation entries in the linked list where the entry is located. The information content of the third identification information being the binary character "1" can be used to represent that there are incomplete prior atomic operation entries in the linked list where the entry is located.

[0036] It should be noted that the types of identification information given above are merely for illustration. In actual applications, depending on the needs of feature support, additional identification information and corresponding execution conditions may be introduced for each item, and this application does not impose any restrictions on this.

[0037] Step S200: Generate request execution instruction information corresponding to the target entry to instruct the execution of the cache missing request corresponding to the target entry.

[0038] Specifically, after the target entry is determined, the missing status holding register can generate request execution instruction information corresponding to the target entry. This request execution instruction information can be sent to the corresponding hardware unit (such as cache controller, memory controller, interconnect network interface, and load / store module, which can be determined according to the data migration object involved in the target cache missing request) to instruct the hardware unit to execute the cache missing request corresponding to the target entry.

[0039] It should be noted that, in order to ensure that the hardware unit correctly executes the cache miss request, the request execution instruction information may include relevant information such as the cache address targeted by the request, the target level cache address, the identifier of the request triggering object, the request operation type, and the data migration path. This application does not limit the specific content included in the request execution instruction information.

[0040] It should be noted that, in this embodiment of the invention, for entries representing cache miss requests of types other than atomic operations, the miss status holding register can remove the entry from its linked list after the entry is released. However, for entries representing cache miss requests of atomic operation type, the miss status holding register can temporarily retain the entry in its linked list after the entry is released, until the cache miss request it represents is processed.

[0041] Figure 6 This is a flowchart of an entry determination method according to an embodiment of the present invention. It is intended to illustrate that by executing... Figure 6 The entry determination method described herein allows a missing status holding register to receive cache missing requests, determine the corresponding entry for each received cache missing request, and add the entry to the appropriate linked list for storage. For example... Figure 6 As shown, the item determination method may specifically include the following steps: Step S310: Receive the target cache missing request.

[0042] Specifically, the missing status holding register can target cache miss requests. This application does not limit the scope of any cache miss request that can be triggered by the target cache miss request. Furthermore, it should be noted that in this embodiment of the invention, cache miss requests can be triggered by any running program or execution thread, and this application does not specifically limit this.

[0043] Step S320: Determine the target cache address corresponding to the target cache missing request.

[0044] Specifically, upon receiving a target cache miss request, the miss status holding register can determine the target cache address to which the target cache miss request is directed. The target cache address is the specific cache line to which the target cache miss request is directed.

[0045] Step S330: Determine the corresponding target linked list from multiple linked lists based on the target cache address.

[0046] Specifically, after determining the target cache address corresponding to the target cache missing request, the missing status holding register can determine the corresponding target linked list from multiple linked lists based on the target cache address.

[0047] Step S340: Create a target entry in the target linked list to represent the target cache missing request.

[0048] Specifically, after determining the corresponding target list, the missing status holding register can create a target entry in the target list to represent the target cache missing request.

[0049] Optionally, after creating a target entry, if a target cache missing request is detected as a cache block missing request, the missing status holding register can also update the corresponding first identification information for the target entry.

[0050] Further optionally, in this embodiment of the invention, to improve efficiency, the missing state holding register can use the first identification information of the preceding entry in the linked list where the target entry is located to update the corresponding first identification information for the target entry. Specifically, when updating the corresponding first identification information for the target entry, the missing state holding register can detect whether the target entry is the first entry in the target linked list. Furthermore, if the target entry is detected as the first entry in the target linked list, the missing state holding register can determine the release status of the second entry in the target linked list and update the corresponding first identification information for the target entry based on the release status of the second entry in the target linked list. If the target entry is detected as not being the first entry in the target linked list, the missing state holding register can update the corresponding first identification information for the target entry based on the first identification information corresponding to the preceding first entry in the target linked list (the entry state represented by the first identification information of the target entry is the same as the entry state represented by the first identification information of the preceding first entry). The release status of the second entry in the target linked list can be determined by the missing state holding register comparing the cache address corresponding to the target entry with the cache addresses of all stored entries. Therefore, by using the first identifier information of the preceding entries in the linked list where the target entry is located to update the corresponding first identifier information for the target entry, the embodiments of the present invention can reduce the number of cache address comparisons, thereby improving efficiency.

[0051] Optionally, in this embodiment of the invention, when each entry has corresponding second identification information, after the target entry is created, the missing status holding register can also update the corresponding second identification information for the target entry.

[0052] Optionally, in this embodiment of the invention, to improve efficiency, the missing status holding register can also utilize the second identification information of the preceding entry in the linked list where the target entry is located to update the corresponding second identification information of the target entry. Specifically, when updating the corresponding second identification information of the target entry, the missing status holding register can detect whether the target entry is the first entry in the target linked list and whether the target entry is the first second entry in the target linked list. Furthermore, if the target entry is detected as the second entry but not the first second entry in the target linked list, the missing status holding register can update the corresponding second identification information of the target entry according to the second identification information of the preceding second entry in the target linked list (the entry state represented by the second identification information of the target entry is the same as the entry state represented by the second identification information of the preceding second entry). If the target entry is detected as the first entry and the first entry in the target linked list, the missing status holding register can query the corresponding waiting data return status of the target entry and update the corresponding second identification information of the target entry according to the corresponding waiting data return status of the target entry. If the target entry is detected as the first entry but not the first entry in the target linked list, the missing state holding register can update the corresponding second identifier information of the target entry based on the second identifier information corresponding to the first entry in the target linked list (the entry state represented by the second identifier information of the target entry is the same as the entry state represented by the second identifier information of the first entry). Therefore, by utilizing the second identifier information of the first entry in the linked list to update the corresponding second identifier information of the target entry, this embodiment of the invention can reduce the number of data query waits, thereby improving efficiency.

[0053] Optionally, in this embodiment of the invention, when each entry has corresponding third identification information, after the target entry is created, the missing status holding register can also update the corresponding third identification information for the target entry.

[0054] Optionally, in this embodiment of the invention, to improve efficiency, the missing state holding register can also utilize the third identification information of the prior entries in the linked list where the target entry is located to update the corresponding third identification information of the target entry. Specifically, if a prior entry is detected in the target linked list and the prior entry is not a released entry, the missing state holding register can update the corresponding third identification information of the target entry based on the third identification information corresponding to the prior entry in the target linked list (the entry state represented by the third identification information of the target entry is the same as the entry state represented by the third identification information of the prior entry). If a prior entry is detected in the target linked list and the prior entry is a released entry (i.e., indicating that there is a prior atomic operation entry that is not yet completed in the linked list where the target entry is located), the missing state holding register can directly update the corresponding third identification information of the target entry. If a prior entry is detected in the target linked list (i.e., indicating that there is a prior atomic operation entry that is not yet completed in the linked list where the target entry is located), the missing state holding register can directly update the corresponding third identification information of the target entry.

[0055] Optionally, in this embodiment of the invention, as a method of updating identification information, the first identification information, the second identification information, and the third identification information can be directly updated after detecting a change in the entry status of the corresponding entry. Alternatively, as an update method, the first identification information, the second identification information, and the third identification information of each entry can be updated based on the current entry status of each entry after being traversed and selected; this application does not impose any limitations on this.

[0056] To facilitate understanding, specific examples will be used to illustrate this below.

[0057] Figures 7 to 10 This is a schematic diagram illustrating the entry release process according to an embodiment of the present invention. It is intended to be explained that... Figures 7 to 10 The entry release process shown can specifically be the process of releasing multiple existing entries without adding any new entries. For example... Figure 7As shown, assume that the missing state holding register stores multiple entries, including entries b, c, j, k, and l. Entries b and c can belong to one linked list, while entries j, k, and l can belong to another linked list. In this state, to determine the target entry to be released, the missing state holding register can traverse the multiple stored entries in chronological order, starting with the earliest stored entry c, to identify entry b as the target entry and release it. During the traversal, entries c, l, and k are not selected as target entries because the corresponding second entries indicated by the first identifier information have not all been released. Entry j is not selected as a target entry because the waiting data corresponding to the entry indicated by the second identifier information has not been returned. It should be noted that because entry b represents a cached missing request of atomic operation type, entry b is not removed from its linked list after being released.

[0058] Furthermore, after entry b is released and the waiting data corresponding to entry j is returned, the entry storage diagram of the missing state holding register can be shown as follows: Figure 8 As shown. In this state, to determine the target entry that needs to be released, the missing state holding register can use the earliest stored entry c as the traversal starting point, and traverse the stored entries in chronological order to identify entry j as the target entry and release it. During the traversal, entry c is not selected as the target entry because the third identifier indicates that the linked list containing the entry contains incomplete prior atomic operation entries and that it is not an atomic operation entry adjacent to entry b. Entry l is not selected as the target entry because the first identifier indicates that the corresponding second entries have not all been released.

[0059] Furthermore, after entry j is released and the cache miss request represented by entry b is processed, the entry storage diagram of the miss state holding register can be as follows: Figure 9 As shown. In this state, to determine the target entry that needs to be released, the missing state holding register can use the earliest stored entry c as the starting point for traversal, and traverse the multiple stored entries in the order of storage time to determine entry c as the target entry and release the target entry.

[0060] Furthermore, after entry c is released, the entry storage diagram of the missing state holding register can be shown as follows: Figure 10 As shown. In this state, to determine the target entry that needs to be released, the missing state holding register can use the entry l with the earliest storage time as the traversal starting point, and traverse the multiple stored entries in the order of storage time to determine entry l as the target entry, and then release the target entry.

[0061] Furthermore, after entry l is released, the entry storage diagram of the missing state holding register can be shown as follows: Figure 11 As shown. In this state, to determine the target entry that needs to be released, the missing state holding register can use the earliest stored entry k as the starting point for traversal, and traverse the multiple stored entries in the order of storage time to determine entry k as the target entry, and then release the target entry.

[0062] Therefore, embodiments of the present invention can ensure that cache line missing requests for the same cache address are processed before cache block missing requests, and that each cache missing request is processed in the order of arrival.

[0063] In this embodiment of the invention, the earliest stored entry is used as the starting point for traversal. Multiple stored entries are traversed in chronological order to determine the target entry. Then, request execution instruction information corresponding to the target entry is generated to instruct the execution of the cache miss request corresponding to the target entry. Multiple entries are stored in a linked list, with each linked list including a first entry and a corresponding second entry. The first entry represents a cache block miss request, and the second entry represents a cache line miss request. Each first entry has corresponding first identifier information, indicating whether all second entries corresponding to the first entry have been released. The target entry is the first entry encountered that satisfies the execution conditions. The execution conditions include the entry being a second entry or the entry being a first entry whose first identifier indicates that all corresponding second entries have been released. Therefore, by combining a linked list-based cache miss request management method with a class-first-in-first-out cache miss request management method, and introducing identification information to characterize the entry status of the corresponding entries in the linked list, and selecting the entry that needs to be released based on the identification information, this embodiment of the invention can ensure that cache line miss requests for the same cache address are processed before cache block miss requests, while ensuring that each cache miss request is processed in the order of arrival, and at the same time reducing the area overhead caused by processing cache miss requests.

[0064] Figure 12 This is a schematic diagram of a cache miss request processing device according to an embodiment of the present invention. Figure 12 As shown, the cache missing request processing device of this embodiment includes a target entry determination unit 121 and an execution instruction information generation unit 122.

[0065] Specifically, the target entry determination unit 121 is used to traverse multiple stored entries in the order of storage time, starting from the entry with the earliest storage time, to determine the target entry. The multiple entries are stored in the form of a linked list, and the same linked list includes a first entry and a corresponding second entry. The first entry is used to represent a cache block missing request, and the second entry is used to represent a cache line missing request. Each first entry has corresponding first identification information, which is used to represent whether each second entry corresponding to the first entry has been released. The target entry is the first entry that meets the execution conditions during traversal. The execution conditions include the entry being the second entry or the entry being the first entry whose corresponding second entries have been released as indicated by the first identification information.

[0066] The execution instruction information generation unit 122 is used to generate request execution instruction information corresponding to the target entry, so as to instruct the execution of the cache missing request corresponding to the target entry.

[0067] In this embodiment of the invention, the earliest stored entry is used as the starting point for traversal. Multiple stored entries are traversed in chronological order to determine the target entry. Then, request execution instruction information corresponding to the target entry is generated to instruct the execution of the cache miss request corresponding to the target entry. Multiple entries are stored in a linked list, with each linked list including a first entry and a corresponding second entry. The first entry represents a cache block miss request, and the second entry represents a cache line miss request. Each first entry has corresponding first identifier information, indicating whether all second entries corresponding to the first entry have been released. The target entry is the first entry encountered that satisfies the execution conditions. The execution conditions include the entry being a second entry or the entry being a first entry whose first identifier indicates that all corresponding second entries have been released. Therefore, by combining a linked list-based cache miss request management method with a class-first-in-first-out cache miss request management method, and introducing identification information to characterize the entry status of the corresponding entries in the linked list, and selecting the entry that needs to be released based on the identification information, this embodiment of the invention can ensure that cache line miss requests for the same cache address are processed before cache block miss requests, while ensuring that each cache miss request is processed in the order of arrival, and at the same time reducing the area overhead caused by processing cache miss requests.

[0068] Figure 13 This is a schematic diagram of a missing state holding register according to an embodiment of the present invention. Figure 13As shown, the missing status holding register 13 may include an entry memory 131, an address comparator 132, and a controller 133. The entry memory 131 may be a hardware storage resource located within the missing status holding register, used for storing entries. The address comparator 132 may be used to compare the cache addresses of the entries stored in the entry memory 131. The controller 132 may be a logic execution module located within the missing status holding register, serving as the execution body for the cache miss request processing method in the above embodiments. In this embodiment of the invention, by having the controller 132 execute the cache miss request processing method, this embodiment of the invention can ensure that cache line miss requests for the same cache address are processed before cache block miss requests, thereby processing cache miss requests as sequentially as possible in the order of arrival, while reducing the area overhead caused by processing cache miss requests.

[0069] Figure 14 This is a schematic diagram of a high-speed cache according to an embodiment of the present invention. Figure 14 As shown, the cache 14 may include a cache interface 141, a hit test unit 142, and a miss status holding register 143. The cache interface 141 can be used to receive multiple data memory access requests sent by an external computing engine. The hit test unit 142 can be used to determine whether each data memory access request hits the corresponding cache, thereby generating a cache miss request. The miss status holding register 143 can be a hardware structure for recording and managing cache miss requests. In this embodiment of the invention, the miss status holding register can ensure that cache line miss requests for the same cache address are processed before cache block miss requests, thereby ensuring that cache miss requests are processed sequentially as much as possible in the order of arrival, while reducing the area overhead caused by processing cache miss requests.

[0070] Figure 15 This is a schematic diagram of a computer system according to an embodiment of the present invention. Figure 15 As shown, the computer system 15 may include a computing engine 151 and a cache 152. The computing engine 151 can generate data access requests and send them to the cache 152. It is worth noting that the computing engine 151 can serve as an execution carrier for a program or computing task. Specifically, the data access request can be generated by the computing engine 151 during program or computing task execution, based on the program execution status or computing execution requirements. The cache 152 can internally store cached data (including program instructions or computing resources, etc., which are not limited in this application). The cache 152 can provide data access services to the computing engine 151. In this embodiment of the invention, when a data access request misses cached data, the cache 152 can further provide the computing engine 151 with a migration service for the missed data.

[0071] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for handling cached missing requests, characterized in that, The method includes: Starting with the entry with the earliest storage time, the system traverses multiple entries in storage time order to determine the target entry. These multiple entries are stored in a linked list, with each linked list containing a first entry and a corresponding second entry. The first entry represents a cache block miss request, and the second entry represents a cache line miss request. Each first entry has corresponding first identifier information, which indicates whether all second entries corresponding to the first entry have been released. The target entry is the first entry encountered that satisfies the execution conditions. The execution conditions include the entry being either the second entry or the entry being the first entry whose corresponding second entries have been released as indicated by the first identifier information. Generate request execution instruction information corresponding to the target entry to instruct the execution of the cache missing request corresponding to the target entry.

2. The method according to claim 1, characterized in that, The cache miss requests corresponding to each entry in the same linked list are for the same cache address; The method further includes: Receive a target cache missing request; Determine the target cache address corresponding to the target cache missing request; The corresponding target linked list is determined from multiple linked lists based on the target cache address; Create a target entry in the target linked list to represent the target cache missing request.

3. The method according to claim 2, characterized in that, After creating a target entry in the target linked list to represent the target cache missing request, the method further includes: In response to detecting that the target cache missing request is a cache block missing request, the corresponding first identification information for the target entry is updated.

4. The method according to claim 2, characterized in that, The step of updating the first identifier information corresponding to the target entry includes: In response to detecting that the target entry is the first entry in the target linked list, the release status of the second entry in the target linked list is determined, and the corresponding first identifier information of the target entry is updated according to the release status of the second entry in the target linked list; In response to detecting that the target entry is not the first entry in the target linked list, the first identifier information corresponding to the target entry is updated according to the first identifier information corresponding to the first entry in the target linked list.

5. The method according to claim 2, characterized in that, Each of the aforementioned entries also has corresponding second identification information, which is used to indicate whether the waiting data corresponding to the entry has been returned. The execution condition also includes the second identification information of the entry, which is used to indicate that the waiting data corresponding to the entry has been returned.

6. The method according to claim 5, characterized in that, After creating a target entry in the target linked list to represent the target cache missing request, the method further includes: Update the corresponding second identifier information for the target entry.

7. The method according to claim 6, characterized in that, The step of updating the second identifier information corresponding to the target entry includes: In response to detecting that the target entry is the second entry but not the first second entry in the target list, the second identification information corresponding to the target entry is updated according to the second identification information corresponding to the earlier second entry in the target list; In response to detecting that the target entry is the first entry and the first entry in the target linked list, the corresponding waiting data return status of the target entry is queried, and the corresponding second identifier information of the target entry is updated according to the corresponding waiting data return status of the target entry. In response to detecting that the target entry is the first entry but not the first entry in the target linked list, the second identifier information corresponding to the target entry is updated according to the second identifier information corresponding to the first entry in the target linked list.

8. The method according to claim 2, characterized in that, Each entry also has corresponding third identification information, which is used to indicate whether there is an incomplete prior atomic operation entry in the linked list where the entry is located. The prior atomic operation entry is a prior entry that indicates a cache miss request of the atomic operation type. The execution condition also includes the third identification information of the entry used to indicate that there is no incomplete prior atomic operation entry in the linked list where the entry is located, or that there is an incomplete prior atomic operation entry in the linked list where the entry is located, but the entry is an atomic operation entry adjacent to the prior atomic operation entry.

9. The method according to claim 8, characterized in that, After creating a target entry in the target linked list to represent the target cache missing request, the method further includes: Update the corresponding third identifier information for the target entry.

10. The method according to claim 1, characterized in that, The stored entries are arranged in order of storage time; The process of traversing multiple stored entries in chronological order, starting with the earliest stored entry, to determine the target entry includes: The earliest stored entry is determined from the plurality of entries based on a read pointer, wherein the read pointer is configured to point to the earliest stored entry among the plurality of entries; Starting with the entry with the earliest storage time, the multiple entries are traversed in order of their storage location to determine the target entry.

11. A cache miss request processing apparatus, characterized in that, The device includes: The target entry determination unit is used to traverse multiple stored entries in storage time order, starting from the entry with the earliest storage time, to determine the target entry. The multiple entries are stored in a linked list, with each linked list including a first entry and a corresponding second entry. The first entry represents a cache block miss request, and the second entry represents a cache line miss request. Each first entry has corresponding first identifier information, which indicates whether all second entries corresponding to the first entry have been released. The target entry is the first entry encountered that satisfies the execution condition, which includes the entry being either the second entry or the entry being the first entry whose corresponding second entries have been released as indicated by the first identifier information. An execution instruction information generation unit is used to generate request execution instruction information corresponding to the target entry, so as to instruct the execution of the cache missing request corresponding to the target entry.

12. A missing state holding register, configured in a cache, characterized in that, The missing state holding register includes: Entry storage, used for storing entries; An address comparator is used to compare the cache addresses of the entries stored in the entry memory; A controller for performing the method as described in any one of claims 1-10.

13. A cache, characterized in that, The cache includes: The caching interface is used to receive multiple data access requests to memory. The hit test unit is used to determine whether each data access request hits the corresponding cache, so as to generate a cache miss request; The missing state holding register as described in claim 12.

14. A computer system, characterized in that, The system includes: The cache as described in claim 13; A computing engine is used to generate data access requests and send the data access requests to the cache.

Images