Epitaxial wafer defect position offset compensation method and device and electronic equipment

Abstract

The invention discloses an offset compensation method and device for a defect position of an epitaxial wafer and electronic equipment, and belongs to the technical field of semiconductors. The method comprises the following steps: acquiring a pre-alignment parameter and first defect position information of a first epitaxial wafer; based on an epitaxial wafer defect sample set, an offset compensation model is determined, and the epitaxial wafer defect sample set comprises sample pre-alignment parameters, sample defect position information and defect position sample labels; and obtaining target defect position information of the first epitaxial wafer based on the pre-alignment parameter, the first defect position information and the offset compensation model. According to the method, a function relationship among a pre-alignment parameter, an original defect coordinate and an actual defect coordinate is accurately learned through an offset compensation model, and the defect position offset of the epitaxial wafer is accurately compensated, so that a reliable position mapping relationship between the defect of the epitaxial wafer and devices such as a chip can be constructed; and the accuracy of subsequent yield analysis and the precision of process control are effectively improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method, apparatus and electronic device for offset compensation of the position of defects in epitaxial wafers. Background Technology

[0002] During epitaxial wafer growth, defects are inevitably generated due to various factors such as growth conditions, material properties, and process parameters. After the epitaxial process, an epitaxial metrology machine can be used to inspect the quality of the epitaxial wafer, identify defects on the wafer, and record the coordinates and dimensions of these defects for subsequent yield analysis and process control.

[0003] Currently, when epitaxial metrology equipment detects defects in epitaxial wafers, it relies solely on mechanical alignment devices for coordinate alignment. This results in a significant offset between the detected defect location and the actual physical location of the defect, affecting subsequent yield analysis and process control. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. To this end, the present invention proposes a method, apparatus, and electronic device for offset compensation of epitaxial wafer defect positions, which can accurately compensate for the offset of epitaxial wafer defect positions.

[0005] In a first aspect, this application provides a method for offset compensation of the location of defects in an epitaxial wafer, the method comprising: Obtain the pre-alignment parameters and the location information of the first defect of the first epitaxial wafer; Based on the epitaxial wafer defect sample set, an offset compensation model is determined, wherein the epitaxial wafer defect sample set includes sample pre-alignment parameters, sample defect location information, and defect location sample labels; Based on the pre-alignment parameters, the first defect location information, and the offset compensation model, the target defect location information of the first epitaxial wafer is obtained.

[0006] According to the method for offset compensation of epitaxial wafer defect positions in this application, the pre-alignment parameters of the first epitaxial wafer and the first defect position information are input into the offset compensation model. The offset compensation model is used to offset the defect coordinates to obtain the target defect position information output by the offset compensation model. The offset compensation model is used to accurately learn the functional relationship between the pre-alignment parameters, the original defect coordinates and the actual defect coordinates, and to accurately compensate for the offset of the epitaxial wafer defect position. This helps to build a reliable position mapping relationship between epitaxial wafer defects and devices such as chips, and effectively improves the accuracy of subsequent yield analysis and the precision of process control.

[0007] According to one embodiment of this application, the sample pre-alignment parameters and the sample defect location information are test data of a sample epitaxial wafer that has not undergone zero-layer lithography; The defect location sample label is the test data of the sample epitaxial wafer that has completed zero-layer lithography.

[0008] According to one embodiment of this application, determining the offset compensation model based on the epitaxial wafer defect sample set includes: Based on the sample pre-alignment parameters, the sample defect location information, and the offset compensation model to be trained, the predicted defect location of the sample is obtained. Based on the predicted defect location from the samples and the sample labels at the defect location, the model loss function is determined; Based on the model loss function, the model parameters of the offset compensation model are updated to obtain the trained offset compensation model.

[0009] According to one embodiment of this application, updating the model parameters of the offset compensation model based on the model loss function includes: Based on the model loss function, an adaptive moment estimation optimizer is used to iteratively update the model parameters.

[0010] According to one embodiment of this application, the offset compensation model includes an input layer, a residual network structure, and an output layer connected in sequence, wherein the residual network structure includes a preset number of residual blocks connected in sequence.

[0011] Secondly, this application provides an offset compensation device for the location of defects in an epitaxial wafer, the device comprising: The acquisition module is used to acquire the pre-alignment parameters and the location information of the first defect of the first epitaxial wafer; The first processing module is used to determine the offset compensation model based on the epitaxial wafer defect sample set, wherein the epitaxial wafer defect sample set includes sample pre-alignment parameters, sample defect location information, and defect location sample labels. The second processing module is used to obtain the target defect location information of the first epitaxial wafer based on the pre-alignment parameters, the first defect location information, and the offset compensation model.

[0012] According to the epitaxial wafer defect position offset compensation device of this application, by inputting the pre-alignment parameters of the first epitaxial wafer and the first defect position information into the offset compensation model, the offset compensation model is used to offset the defect coordinates to obtain the target defect position information output by the offset compensation model. The offset compensation model accurately learns the functional relationship between the pre-alignment parameters, the original defect coordinates and the actual defect coordinates, and accurately compensates for the offset of the epitaxial wafer defect position. This helps to build a reliable position mapping relationship between epitaxial wafer defects and devices such as chips, and effectively improves the accuracy of subsequent yield analysis and the precision of process control.

[0013] According to one embodiment of this application, the sample pre-alignment parameters and the sample defect location information are test data of a sample epitaxial wafer that has not undergone zero-layer lithography; The defect location sample label is the test data of the sample epitaxial wafer that has completed zero-layer lithography.

[0014] Thirdly, this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method for offset compensation of epitaxial wafer defect positions as described in the first aspect above.

[0015] Fourthly, this application provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the offset compensation method for the epitaxial wafer defect location as described in the first aspect above.

[0016] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the method for offset compensation of epitaxial wafer defect locations as described in the first aspect above.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a flowchart illustrating the method for offset compensation of epitaxial wafer defect locations provided in an embodiment of this application; Figure 2 This is a schematic diagram of the training process of the offset compensation model provided in the embodiments of this application; Figure 3 This is a schematic diagram of the offset compensation model provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure of the residual block provided in an embodiment of this application; Figure 5 This is a schematic diagram of the data flow of the offset compensation model provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of the offset compensation device for the epitaxial wafer defect position provided in the embodiments of this application; Figure 7 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0020] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0021] The following description, in conjunction with the accompanying drawings, details the method for offset compensation of epitaxial wafer defect locations, the device for offset compensation of epitaxial wafer defect locations, the electronic device, and the readable storage medium provided in this application, through specific embodiments and application scenarios.

[0022] Current measuring instruments rely solely on mechanical alignment devices for coordinate alignment when inspecting defects in epitaxial wafers. This results in a significant offset (up to 500 micrometers) between the detected defect location and the actual physical location of the defect, affecting subsequent yield analysis and process control.

[0023] If the coordinate offset of epitaxial wafer defects is not compensated, the positional mapping relationship between epitaxial wafer defects and chips may be incorrect, thus affecting the accuracy of ink dots when the chips are shipped.

[0024] In related technologies, there are generally two methods to compensate for the coordinate offset of epitaxial wafer defects: Firstly, fixed parameters such as translation and rotation values ​​are calculated based on historical offset data, and these fixed parameters are used to compensate for the coordinates of detected defects. However, the deviation values ​​of each wafer are different during mechanical alignment, and the accuracy of compensation by using fixed parameters is poor.

[0025] Secondly, the size of epitaxial wafer defects can be expanded, such as expanding the size of particulate defects of about 0.1 micrometers (μm) to 1 μm. Based on the expanded result, a positional mapping relationship between epitaxial wafer defects and chips can be constructed. However, after the size is expanded, defects that originally belong to one chip may be incorrectly associated with other chips by the system, causing the chips to be misjudged as defective and resulting in over-killing of defects.

[0026] This application provides a method for offset compensation of epitaxial wafer defect positions, which can accurately compensate for the offset of epitaxial wafer defect positions, help to build a reliable positional mapping relationship between epitaxial wafer defects and devices such as chips, and effectively improve the accuracy of subsequent yield analysis and the precision of process control.

[0027] The method for offset compensation of epitaxial wafer defect location provided in this application embodiment can be executed by an electronic device or a functional module or entity in an electronic device that can implement the method for offset compensation of epitaxial wafer defect location. The electronic devices mentioned in this application embodiment include, but are not limited to, computers, industrial control computers and servers. The following uses an electronic device as the execution subject to illustrate the method for offset compensation of epitaxial wafer defect location provided in this application embodiment.

[0028] like Figure 1 As shown, the offset compensation method for the defect position of the epitaxial wafer includes steps 110, 120 and 130.

[0029] Step 110: Obtain the pre-alignment parameters and the location information of the first defect of the first epitaxial wafer.

[0030] The first epitaxial wafer is the epitaxial wafer to be offset compensated.

[0031] It is understandable that an epitaxial wafer refers to a wafer on a substrate that has a semiconductor thin film (i.e., an epitaxial layer) fabricated through an epitaxial growth process. The first epitaxial wafer is a wafer that has completed the epitaxial growth process, but may not have been patterned yet.

[0032] In practice, after the epitaxial growth process is completed, the first epitaxial wafer can be sent to an epitaxial measurement machine. The epitaxial measurement machine measures parameters such as the thickness, uniformity, and electrical properties of the epitaxial layer in the first epitaxial wafer, and identifies various defects on the first epitaxial wafer, such as stacking misalignment, pits, and particulate contamination.

[0033] In this embodiment, the pre-alignment parameters of the first epitaxial wafer can refer to the positioning data measured by the pre-aligner before the first epitaxial wafer enters the measurement area of ​​the epitaxial metrology machine, which is used to accurately locate the center position and crystal orientation.

[0034] In practice, pre-alignment parameters may include the center coordinates of the epitaxial wafer, wafer radius, flat edge length, and flat edge angle.

[0035] It is understandable that the first defect location information may include the defect coordinates, defect size and defect type of each defect on the first epitaxial wafer, which can be measured by an epitaxial measurement machine.

[0036] In this embodiment, the coordinate system of the epitaxial wafer can be defined according to the pre-alignment parameters. The defect coordinates are the numerical values ​​representing the position of the defect in the coordinate system. For example, the defect coordinates of each defect on the first epitaxial wafer can be determined with the center of the first epitaxial wafer as the origin.

[0037] Step 120: Determine the offset compensation model based on the epitaxial wafer defect sample set.

[0038] It is understandable that the offset compensation model is trained based on a set of epitaxial wafer defect samples.

[0039] It should be noted that the epitaxial wafer defect sample set includes the original location data of epitaxial wafer defects and their corresponding offsets. By training the offset compensation model using the epitaxial wafer defect sample set, the offset compensation model can learn how to predict the offset-compensated location information based on the input original location information.

[0040] In this embodiment, the epitaxial wafer defect sample set includes sample pre-alignment parameters, sample defect location information, and defect location sample labels.

[0041] It is understandable that the epitaxial wafer defect sample set may include historical measurement data from the inspection of one or more sample epitaxial wafers.

[0042] Among them, the sample pre-alignment parameters can refer to the positioning data measured by the pre-aligner before the sample epitaxial wafer enters the measurement area of ​​the epitaxial measurement machine, which is used to accurately locate the center position and crystal orientation.

[0043] The defect location information of the sample can be obtained by measuring the epitaxial wafer of the sample using an epitaxial measurement machine. The defect location information includes information such as defect coordinates, defect size and defect type.

[0044] It is understandable that the sample defect location information corresponds to the sample pre-alignment parameters. The coordinate system of the sample epitaxial wafer is defined according to the sample pre-alignment parameters, and the defect coordinates of the sample defect location information are the numerical values ​​representing the defect location in this coordinate system.

[0045] It should be noted that the defect coordinates of the sample defect location information refer to the original defect coordinates of the sample epitaxial wafer measured by the epitaxial measurement machine, while the defect location sample label refers to the actual defect coordinates of the sample epitaxial wafer.

[0046] In this embodiment, the epitaxial wafer defect sample set includes sample pre-alignment parameters, sample defect location information, and defect location sample labels. The offset compensation model trained using the epitaxial wafer defect sample set accurately learns the functional relationship between the pre-alignment parameters, the original defect coordinates, and the actual defect coordinates, and can accurately compensate for the offset of the epitaxial wafer defect position.

[0047] Step 130: Based on the pre-alignment parameters, the first defect location information, and the offset compensation model, obtain the target defect location information of the first epitaxial wafer.

[0048] In this step, the pre-alignment parameters of the first epitaxial wafer and the first defect location information are input into the offset compensation model. The offset compensation model is used to perform offset compensation, and the target defect location information of the first epitaxial wafer output by the offset compensation model is obtained. A reliable positional mapping relationship between the epitaxial wafer defect and devices such as chips can be constructed through the target defect location information.

[0049] In this embodiment, the target defect location information may include the defect coordinates after offset compensation of each defect on the first epitaxial wafer, and the target defect location information may also include information such as defect size and defect type.

[0050] It should be noted that the offset compensation model is used to compensate for the offset of the defect coordinates and will not affect the defect type or defect size.

[0051] The following is a specific example.

[0052] Obtain the pre-alignment parameters and first defect location information of the first epitaxial wafer. The first epitaxial wafer has three defects A, B, and C. Using the center of the first epitaxial wafer as the origin, determine the defect coordinates of each defect. The defect coordinates of defects A, B, and C in the first defect location information are respectively (X... A1 Y A1 ), (X) B1 Y B1 ), (X) C1 Y C1 ).

[0053] The pre-alignment parameters and the location information of the first epitaxial wafer are input into the offset compensation model for offset compensation. The target defect location information of the first epitaxial wafer is obtained from the offset compensation model output. The defect coordinates of defects A, B, and C in the target defect location information are respectively (X... A2 Y A2 ), (X) B2 Y B2 ), (X) C2 Y C2 ).

[0054] In this embodiment, the functional relationship between the pre-alignment parameters, the original defect coordinates, and the actual defect coordinates is accurately learned through the offset compensation model. The original defect coordinates are offset compensated to obtain more accurate defect coordinates. Compared with the fixed parameter compensation method in related technologies, the accuracy is higher and it can avoid defect overkill caused by defect size expansion. Accurate compensation for the position offset of epitaxial wafer defects helps to build a reliable position mapping relationship between epitaxial wafer defects and chips and other devices, effectively improving the accuracy of subsequent yield analysis and the precision of process control.

[0055] According to the epitaxial wafer defect location offset compensation method provided in the embodiments of this application, the pre-alignment parameters of the first epitaxial wafer and the first defect location information are input into the offset compensation model. The offset compensation model is used to offset the defect coordinates to obtain the target defect location information output by the offset compensation model. The offset compensation model is used to accurately learn the functional relationship between the pre-alignment parameters, the original defect coordinates and the actual defect coordinates, and to accurately compensate for the offset of the epitaxial wafer defect location. This helps to build a reliable position mapping relationship between the epitaxial wafer defect and devices such as chips, and effectively improves the accuracy of subsequent yield analysis and the precision of process control.

[0056] In some embodiments, the sample pre-alignment parameters and sample defect location information are test data of epitaxial wafers that have not undergone zero-layer lithography; the defect location sample label is test data of epitaxial wafers that have completed zero-layer lithography.

[0057] Zero-layer lithography refers to the first lithography performed on the wafer. Zero-layer lithography defines the first physical circuit pattern on the wafer, which can serve as the alignment reference for all subsequent multilayer patterns.

[0058] The sample defect location information is the test data of the sample epitaxial wafer before zero-layer lithography. At this time, there is no lithographic pattern on the sample epitaxial wafer. The defect coordinates of the sample defect location information are based on the sample pre-alignment parameters and belong to mechanical coarse positioning based on the pre-aligner.

[0059] The defect location sample label is the test data of the sample epitaxial wafer that has completed zero-layer lithography. At this time, the first layer of lithography circuit pattern is defined on the sample epitaxial wafer. The defect location sample label is based on the first layer of lithography circuit pattern on the sample epitaxial wafer. It belongs to the pattern fine positioning. The defect location sample label can more accurately reflect the actual physical location of the defect on the epitaxial wafer.

[0060] In this embodiment, sample pre-alignment parameters, sample defect location information, and defect location sample labels are used to enable the offset compensation model to accurately learn the coordinate offset before and after zero-layer lithography. By performing offset compensation through the offset compensation model, the mechanical offset error caused by the pre-aligner can be reduced, allowing the offset compensation model to predict target defect location information that is closer to the real defect location. This establishes a reliable positional mapping relationship between epitaxial wafer defects and devices such as chips, effectively improving the accuracy of subsequent yield analysis and the precision of process control.

[0061] In practice, the sample epitaxial wafer can be sent to an epitaxial metrology machine to collect historical test data (defect type, defect coordinates, and defect size) to obtain sample pre-alignment parameters and sample defect location information. After performing zero-layer lithography on the sample epitaxial wafer, the sample epitaxial wafer is sent to a zero-layer wafer metrology machine to collect historical test data (defect type, defect coordinates, and defect size) to obtain defect location sample labels.

[0062] In some embodiments, such as Figure 2 As shown, based on the epitaxial wafer defect sample set, the offset compensation model is determined, including: Step 210: Based on the sample pre-alignment parameters, sample defect location information, and the offset compensation model to be trained, obtain the predicted defect location of the sample. Step 220: Determine the model loss function based on the sample prediction of defect location and defect location sample labels; Step 230: Based on the model loss function, update the model parameters of the offset compensation model to obtain the trained offset compensation model.

[0063] In this embodiment, the offset compensation model is trained using sample pre-alignment parameters, sample defect location information, and defect location sample labels. The input parameters of the offset compensation model are sample pre-alignment parameters and sample defect location information. The offset compensation model predicts the defect location of the output sample. The model loss function (such as the cross-entropy loss function) is calculated using the sample predicted defect location and defect location sample labels. The model parameters of the offset compensation model are iteratively updated according to the model loss function. When the stopping condition is met (the number of iterations reaches a preset number, or the model loss function is less than a preset threshold), the trained offset compensation model is obtained.

[0064] In some embodiments, updating the model parameters of the offset compensation model based on the model loss function may include: Based on the model loss function, an adaptive moment estimator optimizer is used to iteratively update the model parameters.

[0065] The Adam Optimizer adaptively adjusts the learning rate for each parameter by calculating the first and second moment estimates of the gradient.

[0066] In this embodiment, the adaptive moment estimation optimizer is used to iteratively update the model parameters according to the model loss function, which can accelerate the convergence speed of the offset compensation model and improve training stability and model robustness.

[0067] In some embodiments, such as Figure 3 As shown, the offset compensation model includes an input layer, a residual network structure, and an output layer connected in sequence. The residual network structure includes a preset number of residual blocks connected in sequence.

[0068] In this embodiment, residual block 1, residual block 2, residual block 3, ..., residual block n are connected in sequence to construct a residual network structure. By utilizing the mathematical form consistent with residual learning and offset compensation, the prediction accuracy of the offset compensation model is improved. A preset number of residual blocks can also achieve compensation at different scales.

[0069] In practice, for offset compensation models that include residual network structures, an adaptive moment estimator optimizer is used to iteratively update the model parameters, automatically update the path magnitude in the residual network structure, and coordinate with the residual blocks for optimization, thereby achieving fast and stable convergence.

[0070] It is understandable that the preset number can be set according to actual needs. For example, the preset number can be 18. The offset compensation model includes an input layer, a residual network structure and an output layer connected in sequence. The residual network structure includes 18 residual blocks connected in sequence.

[0071] In this embodiment, such as Figure 4 As shown, a residual block can include a convolutional component (Conv), a batch normalization component (BN), and an activation component (ReLU). The residual block contains two processing paths. The first processing path sequentially performs a 1x3 convolution, normalization, activation function, 1x3 convolution, and normalization on the input. The second processing path performs a 1x1 convolution on the input data. The processing results of the two processing paths are added together and then activated by the activation function to obtain the output of the residual block.

[0072] The following is a specific example.

[0073] like Figure 5As shown, the Pre-Aligner parameters (i.e., the pre-alignment parameters of the first epitaxial wafer) and the epitaxial wafer defect data (i.e., the first defect location information, including defect coordinates, defect type and defect size) are input to the input layer of the offset compensation model. The data is then input to the residual network structure through the input layer. Different sizes (e.g. from coarse to fine) of offset compensation are achieved through 18 residual blocks connected in sequence. The output layer of the offset compensation model outputs the compensated defect coordinates.

[0074] In this embodiment, a deep residual network is used to more accurately fit the functional relationship between the pre-Aligner parameters, epitaxial wafer defect data, and actual defect coordinates. The offset compensation model accurately learns the coordinate offset before and after zero-layer lithography. By performing offset compensation through the offset compensation model, the mechanical offset error caused by the pre-aligner can be reduced, enabling the offset compensation model to predict target defect location information that is closer to the real defect location. A reliable positional mapping relationship between epitaxial wafer defects and devices such as chips is constructed, effectively improving the accuracy of subsequent yield analysis and the precision of process control.

[0075] The method for offset compensation of epitaxial wafer defect positions provided in this application can be executed by an epitaxial wafer defect position offset compensation device. This application uses an example of an epitaxial wafer defect position offset compensation device executing the method to illustrate the epitaxial wafer defect position offset compensation device provided in this application.

[0076] This application also provides an offset compensation device for the location of defects in epitaxial wafers.

[0077] like Figure 6 As shown, the offset compensation device for the defect location of the epitaxial wafer includes: The acquisition module 610 is used to acquire the pre-alignment parameters and the first defect location information of the first epitaxial wafer; The first processing module 620 is used to determine the offset compensation model based on the epitaxial wafer defect sample set, wherein the epitaxial wafer defect sample set includes sample pre-alignment parameters, sample defect location information, and defect location sample labels. The second processing module 630 is used to obtain the target defect location information of the first epitaxial wafer based on the pre-alignment parameters, the first defect location information and the offset compensation model.

[0078] According to the epitaxial wafer defect position offset compensation device provided in the embodiments of this application, the pre-alignment parameters of the first epitaxial wafer and the first defect position information are input into the offset compensation model. The offset compensation model is used to offset the defect coordinates to obtain the target defect position information output by the offset compensation model. The offset compensation model accurately learns the functional relationship between the pre-alignment parameters, the original defect coordinates and the actual defect coordinates, and accurately compensates for the offset of the epitaxial wafer defect position. This helps to build a reliable position mapping relationship between epitaxial wafer defects and devices such as chips, and effectively improves the accuracy of subsequent yield analysis and the precision of process control.

[0079] In some embodiments, the sample pre-alignment parameters and sample defect location information are test data of a sample epitaxial wafer that has not undergone zero-layer lithography; The defect location sample label is the test data of the epitaxial wafer that has completed zero-layer lithography.

[0080] In some embodiments, the first processing module 620 is configured to determine an offset compensation model based on an epitaxial wafer defect sample set, including: Based on the sample pre-alignment parameters, sample defect location information, and the offset compensation model to be trained, the predicted defect location of the sample is obtained. The model loss function is determined based on the predicted defect location and the defect location sample labels; Based on the model loss function, the model parameters of the offset compensation model are updated to obtain the trained offset compensation model.

[0081] In some embodiments, the first processing module 620 is used to update the model parameters of the offset compensation model based on the model loss function, including: Based on the model loss function, an adaptive moment estimator optimizer is used to iteratively update the model parameters.

[0082] In some embodiments, the offset compensation model includes an input layer, a residual network structure, and an output layer connected in sequence, wherein the residual network structure includes a predetermined number of residual blocks connected in sequence.

[0083] The offset compensation device for the epitaxial wafer defect location in the embodiments of this application can be an electronic device or a component in an electronic device, such as an integrated circuit or a chip.

[0084] The offset compensation device for the epitaxial wafer defect location in this embodiment can be a device with an operating system. This operating system can be a Microsoft (Windows) operating system, an Android operating system, an iOS operating system, or other possible operating systems; this embodiment does not specifically limit it.

[0085] The epitaxial wafer defect position offset compensation device provided in this application embodiment can realize the various processes implemented in the above-described epitaxial wafer defect position offset compensation method embodiment. To avoid repetition, it will not be described again here.

[0086] In some embodiments, such as Figure 7 As shown, this application embodiment also provides an electronic device 700, including a processor 701, a memory 702, and a computer program stored in the memory 702 and executable on the processor 701. When the program is executed by the processor 701, it implements the various processes of the above-described epitaxial wafer defect location offset compensation method embodiment and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0087] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0088] This application also provides a non-transitory computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the various processes of the above-described epitaxial wafer defect location offset compensation method embodiment and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0089] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0090] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method for offset compensation of epitaxial wafer defect locations.

[0091] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0092] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface and the processor are coupled. The processor is used to run programs or instructions to implement the various processes of the above-described epitaxial wafer defect location offset compensation method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0093] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0094] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0095] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the related technology, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0096] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

[0097] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0098] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for offset compensation of the position of defects in an epitaxial wafer, characterized in that, include: Obtain the pre-alignment parameters and the location information of the first defect of the first epitaxial wafer; Based on the epitaxial wafer defect sample set, an offset compensation model is determined, wherein the epitaxial wafer defect sample set includes sample pre-alignment parameters, sample defect location information, and defect location sample labels; Based on the pre-alignment parameters, the first defect location information, and the offset compensation model, the target defect location information of the first epitaxial wafer is obtained.

2. The method for offset compensation of epitaxial wafer defect positions according to claim 1, characterized in that, The sample pre-alignment parameters and the sample defect location information are test data of the epitaxial wafer of the sample that has not undergone zero-layer lithography; The defect location sample label is the test data of the sample epitaxial wafer that has completed zero-layer lithography.

3. The method for offset compensation of epitaxial wafer defect positions according to claim 1, characterized in that, The determination of the offset compensation model based on the epitaxial wafer defect sample set includes: Based on the sample pre-alignment parameters, the sample defect location information, and the offset compensation model to be trained, the predicted defect location of the sample is obtained. Based on the predicted defect location from the samples and the sample labels at the defect location, the model loss function is determined; Based on the model loss function, the model parameters of the offset compensation model are updated to obtain the trained offset compensation model.

4. The method for offset compensation of epitaxial wafer defect positions according to claim 3, characterized in that, The step of updating the model parameters of the offset compensation model based on the model loss function includes: Based on the model loss function, an adaptive moment estimation optimizer is used to iteratively update the model parameters.

5. The method for offset compensation of epitaxial wafer defect positions according to any one of claims 1-4, characterized in that, The offset compensation model includes an input layer, a residual network structure, and an output layer connected in sequence. The residual network structure includes a preset number of residual blocks connected in sequence.

6. A device for offset compensation of the position of defects in an epitaxial wafer, characterized in that, include: The acquisition module is used to acquire the pre-alignment parameters and the location information of the first defect of the first epitaxial wafer; The first processing module is used to determine the offset compensation model based on the epitaxial wafer defect sample set, wherein the epitaxial wafer defect sample set includes sample pre-alignment parameters, sample defect location information, and defect location sample labels. The second processing module is used to obtain the target defect location information of the first epitaxial wafer based on the pre-alignment parameters, the first defect location information, and the offset compensation model.

7. The offset compensation device for the position of epitaxial wafer defects according to claim 6, characterized in that, The sample pre-alignment parameters and the sample defect location information are test data of the epitaxial wafer of the sample that has not undergone zero-layer lithography; The defect location sample label is the test data of the sample epitaxial wafer that has completed zero-layer lithography.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the offset compensation method for the epitaxial wafer defect position as described in any one of claims 1-5.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the method for offset compensation of epitaxial wafer defect locations as described in any one of claims 1-5.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the offset compensation method for the epitaxial wafer defect position as described in any one of claims 1-5.

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