Semiconductor device

Abstract

There is provided a semiconductor device including: a plurality of active patterns spaced apart in a first direction intersecting a surface of a substrate; a gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of active patterns; and a source / drain pattern spaced apart from the gate electrode in a third direction intersecting the first direction and the second direction, and connected to the plurality of active patterns in the third direction. Each of the plurality of active patterns includes: a contact portion, at least a portion of which is inserted within the source / drain pattern; and a connection portion extending away from the source / drain pattern from the contact portion in the third direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] As one of the scaling techniques for increasing the density of semiconductor devices, multi-gate transistors have been proposed. In multi-gate transistors, a silicon substrate with a fin-shaped or nanowire-shaped structure is formed on a substrate, and the gate is formed on the surface of the silicon substrate. However, due to the miniaturization of semiconductor devices, the resistance between components has become an issue. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor device with reduced resistance.

[0004] Another embodiment of this disclosure provides a semiconductor device with improved reliability.

[0005] The example embodiments are not limited to the technical features described above, and other unstated technical features will be clear to those skilled in the art based on the following description.

[0006] According to an embodiment, a semiconductor device is provided, the semiconductor device comprising: a plurality of active patterns spaced apart in a first direction intersecting a surface of a substrate; a gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of active patterns; and a source / drain pattern spaced apart from the gate electrode in a third direction intersecting the first and second directions, and connected to the plurality of active patterns in the third direction. Each of the plurality of active patterns may include: a contact portion, at least a portion of which extends into the source / drain pattern; and a connection portion extending from the contact portion away from the source / drain pattern in the third direction.

[0007] According to another embodiment, a semiconductor device is provided, the semiconductor device comprising: a plurality of active patterns spaced apart in a first direction intersecting a surface of a substrate; a gate structure including a gate electrode and a gate spacer, the gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of active patterns, the gate spacer being located on a side of the gate electrode in a third direction intersecting the first and second directions; and source / drain patterns spaced apart from the gate structure in the third direction and connected to the plurality of active patterns in the third direction, each of the plurality of active patterns protruding further toward the source / drain pattern than the gate structure in the third direction, and including a multilayer pattern in the third direction.

[0008] According to another embodiment, a semiconductor device is provided, the semiconductor device comprising: a plurality of active patterns spaced apart in a first direction intersecting a surface of a substrate; a gate structure including a gate electrode and a gate spacer, the gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of active patterns, the gate spacer being disposed on a side of the gate electrode in a third direction intersecting the first and second directions; and a source / drain pattern spaced apart from the gate structure in the third direction and connected to the plurality of active patterns in the third direction, each of the plurality of active patterns including: a contact portion contacting the source / drain pattern in the third direction; and a connection portion extending away from the contact portion from the source / drain pattern in the third direction, the contact portion potentially protruding further toward the source / drain pattern than the gate structure in the third direction, the connection portion potentially comprising a two-dimensional material, and the contact portion and the connection portion potentially comprising a first transition metal.

[0009] Details of the example embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0010] These and / or other embodiments, features, and advantages of this disclosure will become clear and more readily understood through the following description of exemplary embodiments in conjunction with the accompanying drawings, wherein: Figure 1 This is an example diagram illustrating a schematic layout of a semiconductor device according to some example embodiments; Figure 2 It shows along Figure 1 Example diagram of the cross section intercepted by line AA; Figure 3 It is shown Figure 2 Enlarged example of R; Figure 4 It shows along Figure 1 Example diagram of the cross section intercepted by line BB; Figure 5 It is shown Figure 2 An enlarged example view of part R is provided to illustrate a semiconductor device according to other example embodiments; Figure 6 It is shown Figure 2 An enlarged example view of part R is provided to illustrate a semiconductor device according to some other example embodiments; Figure 7 It is shown Figure 2An enlarged example view of part R is provided to illustrate a semiconductor device according to other example embodiments; Figure 8 It shows along Figure 1 An example diagram of a cross-section taken by line AA is provided to illustrate a semiconductor device according to other example embodiments; Figure 9 It shows along Figure 1 An example diagram of a cross-section taken by line AA is provided to illustrate a semiconductor device according to some other example embodiments; Figures 10 to 24 It shows the basis for explanation Figure 2 The illustration shows example diagrams of intermediate operations in a method for manufacturing a semiconductor device according to some example embodiments. Detailed Implementation

[0011] Before describing the exemplary embodiments in detail, the words and terms used in the specification and claims should not be construed as limited to their general or dictionary meanings, but rather as meanings and concepts consistent with the technical spirit of this disclosure, provided that the inventor can appropriately define the concepts of the terms to best explain the principles of his or her own invention. Therefore, the embodiments described in the specification and the configurations shown in the drawings are provided by way of example rather than limitation. It should therefore be understood that various equivalents and modifications that can be substituted for those may exist at the time of filing this application.

[0012] The term “and / or” includes any and all combinations of one or more associated listed items. The term “connection” may be used herein to refer to a physical and / or electrical connection. When a component or layer is referred to herein as being “directly” on, “directly in contact with,” or “directly connected to,” it indicates that no intermediate component or layer exists. Similarly, when components are “directly” adjacent to each other, no intermediate component may exist. In the following description, singular expressions include plural expressions unless the context clearly defines otherwise. It should be understood that terms such as “including or comprising” and “forming or composing” are intended to indicate the presence of features, numbers, steps, operations, elements, components, or combinations thereof described in the specification, and are not intended to pre-exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0013] Furthermore, although terms such as "first" and "second" can be used to describe various elements, these elements are not limited by the terms described above, and these terms can be used to distinguish one element from another. Within the scope of this disclosure, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element. Additionally, in the accompanying drawings, the shape and size of the elements may be exaggerated for clarity.

[0014] It should be understood that spatial relative terms such as “above,” “upper,” “upper part,” “upper surface,” “below,” “lower,” “lower part,” “lower surface,” “side surface,” etc., may be indicated by reference to the accompanying drawings, unless otherwise stated. It should be understood that such spatial relative terms are intended to encompass not only the orientation shown in the figures but also different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the term “below” can encompass both upper and lower orientations. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0015] The accompanying drawings of semiconductor devices according to some example embodiments illustrate, by way of example, a fin field-effect transistor (FinFET) including a channel region having a fin pattern shape, a transistor including nanowires or nanosheets, and a multi-bridge channel field-effect transistor (MBCFET), but the example embodiments are not limited thereto.

[0016] Semiconductor devices according to some example embodiments may include tunneling FETs, three-dimensional (3D) transistors, or vertical FETs. Semiconductor devices according to some example embodiments may also include planar transistors. Additionally, this disclosure can be applied to FETs based on two-dimensional (2D) materials and their heterostructures. Furthermore, semiconductor devices according to some example embodiments may also include bipolar junction transistors and laterally diffused metal-oxide-semiconductor (LDMOS) transistors.

[0017] In the following description, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0018] Figure 1 This is an example diagram illustrating a schematic layout of a semiconductor device according to some example embodiments. Figure 2 It shows along Figure 1 Example diagram of the cross section taken by line AA. Figure 3 It is shown Figure 2 A magnified example of part of R. Figure 4 It shows along Figure 1 Example diagram of the cross section taken by line BB.

[0019] refer to Figures 1 to 4 A semiconductor device according to some example embodiments may include a substrate 100, a gate structure GS, a first source / drain pattern 150, a plurality of first active patterns 200, a first source / drain contact 170, a first gate contact 180, a first wiring path 301, and a first wiring layer 311.

[0020] According to some example embodiments, substrate 100 may include active regions AR and field regions FR. Active regions AR and field regions FR may extend in a third direction D3. Active regions AR and field regions FR may be alternately arranged in a second direction D2. For example, active regions AR may be disposed between field regions FR in the second direction D2. Field regions FR may be disposed between active regions AR in the second direction D2. Each of the second direction D2 and the third direction D3 may refer to a direction parallel to substrate 100 and intersecting with a first direction D1. The first direction D1 may refer to a direction perpendicular to substrate 100. The third direction D3 may refer to the direction in which active regions AR and field regions FR extend. The second direction D2 may refer to the direction in which active regions AR and field regions FR are alternately arranged.

[0021] According to some example embodiments, the field region FR may be defined by a trench, but is not limited thereto. Although not shown, the field region FR may be defined by an insulating layer within a trench formed on the substrate 100. Furthermore, it will be apparent to those skilled in the art to which this disclosure pertains that each portion can be classified as a field region and an active region. The field region FR may have a shallow trench isolation (STI) structure. However, the example embodiments are not limited thereto. For example, the field region FR may also be defined by a deep trench.

[0022] According to some example embodiments, a device isolation layer can be disposed around active regions AR spaced apart from each other. In this case, the portion existing in the device isolation layer between two adjacent active regions AR can be a field region FR. For example, the portion forming the channel region of a transistor, which can be an example of a semiconductor device, can be an active region, and the portion formed in the active region that divides the channel region of the transistor can be a field region. Alternatively, the active region can be a portion forming a fin pattern or nanosheet that serves as a channel region of a transistor, and the field region can be a portion where no fin pattern or nanosheet is formed that serves as a channel region.

[0023] According to some example embodiments, substrate 100 may be bulk silicon or silicon-on-insulator (SOI). In contrast, substrate 100 may be a silicon substrate or may include other materials, such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0024] According to some example embodiments, a first interlayer insulating layer 101 may be disposed on the substrate 100 in a first direction D1. The first interlayer insulating layer 101 may cover the upper surface of the substrate 100. The first interlayer insulating layer 101 may be disposed on the substrate 100 and below the gate structure GS and the first source / drain pattern 150.

[0025] According to some example embodiments, the first interlayer insulating layer 101 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. For example, the low dielectric constant material may include, but is not limited to, tetraethyl orthosilicate (FTEOS), hydrosilsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilylborate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate silicon (TMSP), polytetrafluoroethylene (PTFE), TOSZ (TonenSilaZen), fluorinated silicate glass (FSG), polyimide nanofoams such as polypropylene oxide, carbon-doped silicon oxide (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica dry gel, mesoporous silica, or combinations thereof.

[0026] According to some example embodiments, gate structures GS may be disposed on substrate 100. Each gate structure GS may extend in a second direction D2. The gate structures GS may be spaced apart from each other in a third direction D3.

[0027] According to some example embodiments, a gate structure GS can be disposed on a plurality of first active patterns 200. For example, the gate structure GS can intersect with a plurality of first active patterns 200. The gate structure GS can surround a plurality of first active patterns 200. Specifically, the gate electrode 120 of the gate structure GS can surround a plurality of first active patterns 200.

[0028] The gate electrode 120 of the gate structure GS is in Figure 1 The configuration is shown as spanning an active region AR and a field region FR, but is not limited thereto. For example, the gate structure GS may not extend continuously across two active regions AR spaced apart in the second direction D2 and having a field region FR between them, but may be separated in the field region FR. In this case, the gate structure GS extending in the second direction D2 but intersecting one active region AR and the gate structure GS extending in the second direction D2 but intersecting the other active region AR may be spaced apart from each other in the second direction D2.

[0029] According to some example embodiments, the gate structure GS may include a gate electrode 120, a gate insulating layer 130, and a gate spacer 140.

[0030] According to some example embodiments, the gate electrode 120 may extend in the second direction D2. The gate electrode 120 may be disposed between first source / drain patterns 150 adjacent to each other along the third direction D3. The gate electrode 120 may be formed above the substrate 100. The gate electrode 120 may surround a plurality of first active patterns 200. A portion of the gate electrode 120 may be disposed between a plurality of first active patterns 200 adjacent along the first direction D1. The width of the gate electrode 120 in the third direction D3 may be less than the width W220 of the first connection portion.

[0031] According to some example embodiments, the gate electrode 120 may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. For example, the gate electrode 120 may include, but is not limited to, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), and tantalum (Ta). At least one of nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. Conductive metal oxides and conductive metal nitrides may be, but are not limited to, the oxidation forms of the materials mentioned above.

[0032] According to some example embodiments, gate electrodes 120 may be disposed on both sides of the first source / drain pattern 150, which will be described below. Gate structures GS may be disposed on both sides of the first source / drain pattern 150 in the third direction D3. As an example, all gate electrodes 120 disposed on both sides of the first source / drain pattern 150 may be functional gate electrodes used as gates of transistors. As another example, the gate electrode 120 disposed on one side of the first source / drain pattern 150 may be used as the gate of a transistor, while the gate electrode 120 disposed on the other side of the first source / drain pattern 150 may be a dummy gate electrode.

[0033] According to some example embodiments, the gate insulating layer 130 may extend along the upper surface of the first interlayer insulating layer 101 in the second direction D2. The gate insulating layer 130 may surround a plurality of first active patterns 200. The gate insulating layer 130 may be disposed along the periphery of the plurality of first active patterns 200. The gate electrode 120 may be disposed on the gate insulating layer 130. The gate insulating layer 130 may be disposed between the gate electrode 120 and the plurality of first active patterns 200. The gate insulating layer 130 may be disposed inside the gate spacer 140 in the third direction D3 and may surround the gate electrode 120.

[0034] According to some example embodiments, a portion of the gate insulating layer 130 may be disposed between a plurality of first active patterns 200 adjacent along the first direction D1 and between a plurality of first active patterns 200 adjacent along the first direction D1 and the first interlayer insulating layer 101.

[0035] According to some example embodiments, the gate insulating layer 130 may include silicon oxide, silicon germanium oxide, germanium oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material with a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0036] Gate insulating layer 130 in Figures 2 to 4 The gate insulating layer 130 is shown as a single layer for ease of description only, but is not limited thereto. The gate insulating layer 130 may include multiple layers. The gate insulating layer 130 may also include an interface layer disposed between the plurality of first active patterns 200 and the gate electrode 120 and a high dielectric constant insulating layer.

[0037] The semiconductor device according to some example embodiments may include a negative capacitance (NC) FET that uses a negative capacitor. For example, the gate insulating layer 130 may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0038] According to some example embodiments, ferroelectric material films can have negative capacitance, and paraelectric material films can have positive capacitance. For example, when two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance becomes less than the capacitance of each individual capacitor. Conversely, when at least one of the capacitances of two or more capacitors connected in series has a negative capacitance, the total capacitance can be positive and greater than the absolute value of each individual capacitor.

[0039] According to some example embodiments, when a ferroelectric material film with negative capacitance and a paraelectric material film with positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric and paraelectric material films can be increased. Using the increased total capacitance, a transistor including the ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0040] According to some example embodiments, ferroelectric material films can possess ferroelectric properties. Ferroelectric material films can include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide can be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide can also be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0041] According to some example embodiments, the ferroelectric material film may also include doped dopants. For example, the dopants may include at least one selected from aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopants included in the ferroelectric material film can vary depending on which ferroelectric material is included in the film.

[0042] For example, when the ferroelectric material film includes hafnium oxide, the dopants included in the ferroelectric material film may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and yttrium (Y).

[0043] According to some example embodiments, when the dopant is aluminum (Al), the ferroelectric material film may include 3 atomic percent (at%) to 8 at% aluminum. Here, the proportion of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0044] According to some example embodiments, when the dopant is silicon (Si), the ferroelectric material film may include 2 at% to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may include 2 at% to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include 1 at% to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include 50 at% to 80 at% zirconium.

[0045] According to some example embodiments, the paraelectric material film may have paraelectric properties. The paraelectric material film may include at least one of, for example, silicon oxide and metal oxides having a high dielectric constant. For example, the metal oxide included in the paraelectric material film may include, but is not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

[0046] According to some example embodiments, the ferroelectric material film and the paraelectric material film may comprise the same material. While the ferroelectric material film may have ferroelectric properties, the paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0047] According to some example embodiments, the ferroelectric material film can have a thickness that exhibits ferroelectric properties. For example, the thickness of the ferroelectric material film can be, but is not limited to, 0.5 nanometers (nm) to 10 nm. Because the threshold thickness representing the ferroelectric property can vary for each ferroelectric material, the thickness of the ferroelectric material film can vary depending on the ferroelectric material.

[0048] As an example, the gate insulating layer 130 may include a ferroelectric material film. As another example, the gate insulating layer 130 may include multiple ferroelectric material films spaced apart from each other. The gate insulating layer 130 may have a stacked layer structure in which multiple ferroelectric material films and multiple paraelectric material films are stacked alternately.

[0049] According to some example embodiments, the gate spacer 140 may be disposed on the side of the gate electrode 120 in the third direction D3. The gate spacer 140 may cover the sidewall of the gate electrode 120 in the third direction D3. The gate spacer 140 may be disposed between the substrate 100 and a plurality of first active patterns 200 and between a plurality of adjacent first active patterns 200 in the first direction D1.

[0050] According to some example embodiments, the gate spacer 140 may include an inner spacer 141 and an outer spacer 142. The inner spacer 141 and the outer spacer 142 may be disposed in a first direction D1. The inner spacer 141 and the outer spacer 142 may be referred to as gate spacers.

[0051] According to some example embodiments, the inner spacer 141 may be disposed between the plurality of first active patterns 200 and the substrate 100 in the first direction D1. For example, the inner spacer 141 may be disposed between the plurality of first active patterns 200 that are adjacent to each other along the first direction D1. The inner spacer 141 may be disposed between the substrate 100 and the lowermost first active pattern 200 among the plurality of first active patterns 200. The inner spacer 141 may be disposed below the uppermost first active pattern 200 among the plurality of first active patterns 200.

[0052] According to some example embodiments, the outer spacer 142 may be disposed above the uppermost first active pattern 200 among a plurality of first active patterns 200. The outer spacer 142 may be disposed on the protective layer 110.

[0053] According to some example embodiments, the protective layer 110 may be disposed in the first direction D1 between the uppermost first active pattern 200 of a plurality of first active patterns 200 and the outer spacer 142. The protective layer 110 may include, for example, silicon nitride. The protective layer 110 may be disposed below the outer spacer 142 and on one side of the gate electrode 120 and the gate insulating layer 130. The outer surface of the protective layer 110 may be disposed on the same plane as the outer surface 142OSS of the outer spacer.

[0054] According to some example embodiments, the width W142 of the outer spacer in the third direction D3 may be greater than the width W141 of the inner spacer. The width W141 of the inner spacer in the third direction D3 may refer to the distance between the outer surfaces 141OSS of the inner spacer. The width W142 of the outer spacer in the third direction D3 may refer to the distance between the outer surfaces 142OSS of the outer spacer.

[0055] exist Figure 2 and Figure 3 In the example, the width W141 of the inner spacer in the third direction D3 is shown to be smaller than the width W142 of the outer spacer, but the example embodiment is not limited to this. For example, the width W141 of the inner spacer in the third direction D3 may also be equal to or greater than the width W142 of the outer spacer.

[0056] According to some example embodiments, the gate spacer 140 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof. The gate spacer 140 is shown as a single layer only for ease of description, but is not limited thereto.

[0057] According to some example embodiments, a first source / drain pattern 150 may be connected to a plurality of first active patterns 200 on a third-direction D3. The plurality of first source / drain patterns 150 may be spaced apart on the third-direction D3, with the plurality of first active patterns 200 located between them. The first source / drain pattern 150 may be the source / drain of a transistor using the plurality of first active patterns 200 as a channel region. The first source / drain pattern 150 may be disposed between adjacent gate electrodes 120 along the third-direction D3. The first source / drain pattern 150 may be referred to as source / drain pattern 150.

[0058] According to some example embodiments, the first source / drain pattern 150 may surround at least a portion of the first contact portion 210. The first source / drain pattern 150 may cover the outer surface of the first contact portion 210. The first source / drain pattern 150 may cover at least a portion of the upper and lower surfaces of the first contact portion 210. The upper surface 150US of the first source / drain pattern and the upper surface 120US of the gate electrode may be disposed on the same plane.

[0059] According to some example embodiments, the first source / drain pattern 150 may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxide nitride. For example, the first source / drain pattern 150 may include, but is not limited to, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride (Ta... At least one of the following: CN, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. Conductive metal oxides and conductive metal nitrides may be, but are not limited to, the oxidation forms of the materials described above.

[0060] According to some example embodiments, a plurality of first active patterns 200 may be disposed above the active region AR of the substrate 100. The plurality of first active patterns 200 may be disposed on the first interlayer insulating layer 101. For example, the plurality of first active patterns 200 may be active patterns comprising nanosheets or nanowires. The plurality of first active patterns 200 may be spaced apart from the substrate 100 in a first direction D1. The plurality of first active patterns 200 may be spaced apart from each other in the first direction D1. The plurality of first active patterns 200 may extend between the first source / drain patterns 150 in a third direction D3. The plurality of first active patterns 200 may be referred to as a plurality of active patterns 200.

[0061] According to some example embodiments, on a third-party D3, a plurality of first active patterns 200 may be disposed between first source / drain patterns 150. The plurality of first active patterns 200 may be connected to the first source / drain patterns 150.

[0062] According to some example embodiments, the width of the plurality of first active patterns 200 in the second direction D2 may increase or decrease proportionally as they move away from the substrate 100 in the first direction D1. The widths of the plurality of first active patterns 200 in the second direction D2 are shown to be the same, but are not limited thereto.

[0063] According to some example embodiments, the plurality of first active patterns 200 may include, for example, silicon or germanium as elemental semiconductor materials. Additionally, the plurality of first active patterns 200 may include compound semiconductors, and may include, for example, group IV-IV compound semiconductors or group III-V compound semiconductors.

[0064] For example, a group IV-IV compound semiconductor can be a binary or ternary compound containing at least two or more of carbon (C), silicon (Si), germanium (Ge) and tin (Sn), or a compound doped with a group IV element.

[0065] For example, a III-V compound semiconductor can be a binary, ternary, or quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In), which are group III elements, with one of phosphorus (P), arsenic (As), and antimony (Sb), which are group V elements.

[0066] Multiple first active patterns 200 in Figure 2 The example is shown as two groups of 200 in the first direction D1, but the example embodiment is not limited thereto. For example, a plurality of first active patterns 200 may include three or more groups of 200 in the first direction D1.

[0067] According to some example embodiments, a plurality of first active patterns 200 may protrude further toward the first source / drain pattern 150 on the third-direction D3 than the gate structure GS. The width W200 of the plurality of first active patterns on the third-direction D3 may be greater than the width of the gate structure GS. The width W200 of the plurality of first active patterns on the third-direction D3 may refer to the distance between the outer surfaces of the first contact portions 210 that contact the first source / drain pattern 150. The width of the gate structure GS may refer to the larger of the width W141 of the inner spacer and the width W142 of the outer spacer. The width W200 of the plurality of first active patterns on the third-direction D3 may be greater than the width W141 of the inner spacer and the width W142 of the outer spacer.

[0068] According to some example embodiments, each of the plurality of first active patterns 200 may include a multilayer pattern disposed on a third-party orientation D3. Each of the plurality of first active patterns 200 may include a first contact portion 210 and a first connecting portion 220. Each multilayer pattern included in the plurality of first active patterns 200 may include a first contact portion 210 and a first connecting portion 220. The first contact portion 210 and the first connecting portion 220 may be disposed on the third-party orientation D3. The first contact portion 210 and the first connecting portion 220 may be connected to each other on the third-party orientation D3. The first contact portion 210 may be referred to as contact portion 210. The first connecting portion 220 may be referred to as connecting portion 220.

[0069] According to some example embodiments, the first contact portion 210 may be disposed further outward on the third-direction D3 than the first connection portion 220. The first contact portion 210 may contact the first source / drain pattern 150. At least a portion of the first contact portion 210 may be inserted into the first source / drain pattern 150. At least a portion of the first contact portion 210 may penetrate into the first source / drain pattern 150. At least a portion of the first contact portion 210 may be surrounded by the first source / drain pattern 150.

[0070] According to some example embodiments, the first contact portion 210 may protrude further toward the first source / drain pattern 150 than the gate structure GS on the third-direction D3. The first contact portion 210 may protrude further toward the first source / drain pattern 150 than the gate spacer 140 on the third-direction D3. The first contact portion 210 may protrude further toward the first source / drain pattern 150 than the outer surfaces 141OSS and 142OSS of the gate spacer on the third-direction D3.

[0071] According to some example embodiments, at least a portion of the first contact 210 may overlap with the gate spacer 140 in the first direction D1. At least a portion of the first contact 210 may overlap with the inner spacer 141 in the first direction D1. At least a portion of the first contact 210 may overlap with the outer spacer 142 in the first direction D1.

[0072] When viewed along a line extending in a particular direction or in a plane perpendicular to that direction, components or layers described by reference to “overlapping” in that particular direction may at least partially obscure each other. The terms “around,” “cover,” or “fill,” as may be used herein, do not necessarily need to completely surround, cover, or fill the described element or layer, but may refer, for example, to partially surround, cover, or fill the described element or layer, e.g., always having gaps, spaces, or other discontinuities. The term “exposed” may be used to describe the relationship between elements and / or specific intermediate processes during the fabrication of a finished semiconductor device, but may not necessarily require the exposure of specific regions, layers, structures, or other elements in the context of a finished device.

[0073] According to some example embodiments, a first connection portion 220 may be disposed between the first contacts 210 along a third direction D3. The first connection portion 220 may connect the first contacts 210 spaced apart along the third direction D3. The first connection portion 220 may overlap with the gate electrode 120 in a first direction D1. The first connection portion 220 may extend from the first contacts 210 away from the first source / drain pattern 150 in the third direction D3.

[0074] According to some example embodiments, the width W220 of the first connection portion on the third direction D3 may be smaller than the width of the gate spacer 140. The width W220 of the first connection portion on the third direction D3 may be smaller than the width W141 of the inner spacer. The width W220 of the first connection portion on the third direction D3 may be smaller than the width W142 of the outer spacer.

[0075] According to some example embodiments, the first contact 210 may include a transition metal. The first contact 210 may include at least one material selected from molybdenum (Mo), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), and titanium (Ti). However, the example embodiments are not limited thereto. Including a transition metal in the first contact 210 can reduce the resistance generated between the first connection 220 and the first source / drain pattern 150.

[0076] According to some example embodiments, the first connecting portion 220 may include a two-dimensional material. The first connecting portion 220 may include MoS2, MoSe2, MoTe2, WS2, WSe2, MoTe2, or PtSe2. The first connecting portion 220 may include a transition metal dichalcogenide (TMD).

[0077] According to some example embodiments, the first contact portion 210 and the first connecting portion 220 may comprise the same transition metal material as each other. Here, "the same material" may comprise the same amount or different amounts of the same material or element, or the same material or element in the same or different compounds. Furthermore, articles comprising a specific element or compound encompass any article that comprises a specific element or compound alone or that comprises a specific element or compound in combination with other elements and compounds. Each of the first contact portion 210 and the first connecting portion 220 may comprise at least one material selected from molybdenum (Mo), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), and titanium (Ti).

[0078] According to some example embodiments, a first source / drain contact 170 may be disposed above the upper surface of the substrate 100. The first source / drain contact 170 may be disposed on the upper surface of the first source / drain pattern 150. The first source / drain contact 170 may be connected to the first source / drain pattern 150. The first source / drain contact 170 may penetrate the second interlayer insulating layer 191 and the first etch stop layer 161 and be connected to the first source / drain pattern 150.

[0079] According to some example embodiments, the first source / drain contact 170 may include a first source / drain contact barrier layer 170a and a first source / drain contact fill layer 170b located on the first source / drain contact barrier layer 170a. The first source / drain contact barrier layer 170a may extend along the sidewalls and bottom surface of the first source / drain contact fill layer 170b.

[0080] According to some example embodiments, the upper surface of the first source / drain contact barrier layer 170a is shown at substantially the same height as the upper surface of the first source / drain contact fill layer 170b relative to the upper surface of the substrate 100, but is not limited thereto. Unlike what is shown, the upper surface of the first source / drain contact barrier layer 170a may be lower than the upper surface of the first source / drain contact fill layer 170b relative to the upper surface of the substrate 100.

[0081] According to some example embodiments, the first source / drain contact barrier layer 170a may include at least one of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and 2D materials. In the semiconductor device according to some example embodiments, the 2D material may be a metallic material and / or a semiconductor material. The 2D material may include 2D allotropes or 2D compounds, and may include, for example, at least one of, graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2), but is not limited thereto. In other words, since the above-mentioned 2D materials are only listed as examples, the 2D materials that can be included in the semiconductor devices of this disclosure are not limited to the aforementioned materials.

[0082] According to some example embodiments, the first source / drain contact filling layer 170b may include at least one of, for example, aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo).

[0083] According to some example embodiments, the first source / drain contact 170 is shown to include multiple conductive layers, but is not limited thereto. Unlike what is shown, the first source / drain contact 170 may also be a single layer.

[0084] According to some example embodiments, a first gate contact 180 may be disposed on the gate electrode 120. The first gate contact 180 may penetrate the second interlayer insulating layer 191 and the first etch stop layer 161 and be connected to the gate electrode 120. The first gate contact 180 may be connected to the first wiring path 301. The upper surface of the first gate contact 180 may be located on the same plane as the upper surface of the first source / drain contact 170.

[0085] According to some example embodiments, the first gate contact 180 may include a first gate contact barrier layer 180a and a first gate contact fill layer 180b located on the first gate contact barrier layer 180a. The description of the materials included in the first gate contact barrier layer 180a and the first gate contact fill layer 180b is the same as the description of the materials included in the first source / drain contact barrier layer 170a and the first source / drain contact fill layer 170b, and is therefore omitted.

[0086] According to some example embodiments, a first wiring path 301 may be disposed on a first source / drain contact 170 and a first gate contact 180. The first wiring path 301 may penetrate a third interlayer insulating layer 192 and a second etch stop layer 162, and connect to the first source / drain contact 170 and the first gate contact 180. The first wiring path 301 may connect to a first wiring layer 311. The first wiring path 301 may include a first path barrier layer 301a and a first path fill layer 301b. The first path barrier layer 301a may extend along the side surface and bottom surface of the first path fill layer 301b.

[0087] According to some example embodiments, the first pathway barrier layer 301a may include at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), nickel (Ni), nickel boron (NiB), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and 2D materials. For example, the first pathway filling layer 301b may include at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo).

[0088] In some example embodiments, the first wiring layer 311 may penetrate the fourth interlayer insulating layer 193 and the third etch stop layer 163 and connect to the first wiring path 301. The first wiring layer 311 can connect to the first source / drain contact 170 and the first gate contact 180 through the first wiring path 301. The first wiring layer 311 may include a first wiring barrier layer 311a and a first wiring fill layer 311b. The descriptions of the first wiring barrier layer 311a and the first wiring fill layer 311b are substantially the same as those of the first path barrier layer 301a and the first path fill layer 301b, and are therefore omitted.

[0089] Figure 5 It is shown Figure 2 A partial enlarged view of R is provided to illustrate a semiconductor device according to other example embodiments. For the purpose of illustrating the semiconductor device according to other example embodiments, the description and references are primarily as follows: Figures 1 to 4 The differences in description.

[0090] refer to Figure 5 The width W220 of the first connecting portion in the third direction D3 may be greater than the width W141 of the inner spacer. The first connecting portion 220 may protrude further toward the first source / drain pattern 150 in the third direction D3 than the inner spacer 141. The inner spacer 141 may overlap with the first connecting portion 220 in the first direction D1.

[0091] Figure 6 It is shown Figure 2 A partial enlarged view of R is provided to illustrate a semiconductor device according to some other example embodiments. For the purpose of illustrating the semiconductor device according to some other example embodiments, the main description and references are provided. Figures 1 to 4 The differences in description.

[0092] refer to Figure 6 The outer surface of the protective layer 110 may not be located on the same plane as the outer surface 142OSS of the outer spacer. Compared to the protective layer 110, the outer spacer 142 may protrude further toward the first source / drain pattern 150 in the third direction D3. The width between the outer surfaces of the protective layer 110 in the third direction D3 may be less than the width W142 of the outer spacer. At least a portion of the first source / drain pattern 150 may be inserted into the space formed by the outer spacer 142 and the protective layer 110.

[0093] Figure 7 It is shown Figure 2 A partial enlarged view of R is provided to illustrate a semiconductor device according to other example embodiments. For the purpose of illustrating the semiconductor device according to other example embodiments, the description and references are primarily as follows: Figures 1 to 4 The differences in description.

[0094] refer to Figure 7 The width W220 of the first connection portion on the third-direction D3 can be greater than the width of the gate structure GS. The width W220 of the first connection portion on the third-direction D3 can be greater than the width W141 of the inner spacer. The width W220 of the first connection portion on the third-direction D3 can be greater than the width W142 of the outer spacer.

[0095] According to some example embodiments, the first connection portion 220 may protrude further toward the first source / drain pattern 150 than the gate spacer 140 in the third direction D3. The first connection portion 220 may protrude further toward the first source / drain pattern 150 than the outer surface 142OSS of the outer spacer in the third direction D3. The first connection portion 220 may protrude further toward the first source / drain pattern 150 than the outer surface 141OSS of the inner spacer in the third direction D3. At least a portion of the first connection portion 220 may be surrounded by the first source / drain pattern 150. At least a portion of the upper and lower surfaces of the first connection portion 220 disposed in the first direction D1 may be covered by the first source / drain pattern 150.

[0096] Figure 8 It shows along Figure 1An example diagram of a cross-section taken by line AA is provided to illustrate a semiconductor device according to other example embodiments. For the purpose of illustrating the semiconductor device according to other example embodiments, the description and references are primarily as follows: Figures 1 to 4 The differences in description.

[0097] refer to Figure 8 The semiconductor device according to other example embodiments may include a second source / drain contact 270 and a second wiring layer 321.

[0098] According to some example embodiments, a second source / drain contact 270 may be disposed on the lower surface of the first source / drain pattern 150. The second source / drain contact 270 may be connected to the first source / drain pattern 150. The second source / drain contact 270 may penetrate the fifth interlayer insulating layer 291 and be connected to the first source / drain pattern 150. The second source / drain contact 270 may include a second source / drain contact barrier layer 270a and a second source / drain contact fill layer 270b located on the second source / drain contact barrier layer 270a. The description of the second source / drain contact barrier layer 270a and the second source / drain contact fill layer 270b is substantially the same as the description of the first source / drain contact barrier layer 170a and the first source / drain contact fill layer 170b, and is therefore omitted.

[0099] According to some example embodiments, the second wiring layer 321 may be disposed below the gate electrode 120 and the first source / drain pattern 150. The second wiring layer 321 may be disposed below the second source / drain contact 270. The second wiring layer 321 may penetrate the sixth interlayer insulating layer 292 and connect to the second source / drain contact 270. The second wiring layer 321 may include a second wiring barrier layer 321a and a second wiring fill layer 321b. The description of the second wiring barrier layer 321a and the second wiring fill layer 321b is substantially the same as the description of the first wiring barrier layer 311a and the first wiring fill layer 311b, and is therefore omitted.

[0100] The second source / drain contact 270 is in Figure 8 The example is shown as being directly connected to the second wiring layer 321, but the example embodiment is not limited thereto. For example, similar to how the first source / drain contact 170 is connected to the first wiring layer 311 via the first wiring path 301, a second wiring path may also be provided between the second source / drain contact 270 and the second wiring layer 321.

[0101] Figure 8The illustration shows only the second source / drain contact 270 disposed below the gate electrode 120 and the first source / drain pattern 150, but the example embodiment is not limited thereto. For example, a second gate contact may be disposed below and connected to the gate electrode 120. The second gate contact may penetrate the fifth interlayer insulating layer 291 and be connected to the gate electrode 120 and the second wiring layer 321.

[0102] Figure 9 It shows along Figure 1 An example diagram of a cross-section taken by line AA is provided to illustrate a semiconductor device according to some other example embodiments.

[0103] refer to Figure 9 The semiconductor device according to some other example embodiments may include a plurality of first active patterns 200, a plurality of second active patterns 400, a first source / drain pattern 150 and a second source / drain pattern 250.

[0104] According to some example embodiments, a plurality of first active patterns 200 and a plurality of second active patterns 400 may be disposed in a first direction D1. The plurality of first active patterns 200 may be disposed below the separating insulating layer 105. The plurality of second active patterns 400 may be disposed above the separating insulating layer 105.

[0105] According to some example embodiments, a plurality of first active patterns 200 may be connected to a first source / drain pattern 150. At least a portion of the first contact portion 210 of the plurality of first active patterns 200 may be surrounded by the first source / drain pattern 150. Second contact portions 410 of the plurality of first active patterns 200 may be inserted into a second source / drain pattern 250.

[0106] According to some example embodiments, a plurality of second active patterns 400 may include a second contact portion 410 and a second connecting portion 420. The description of the second contact portion 410 and the second connecting portion 420 is substantially the same as the description of the first contact portion 210 and the first connecting portion 220, and is therefore omitted.

[0107] According to some example embodiments, a plurality of second active patterns 400 may be connected to a second source / drain pattern 250. At least a portion of the second contact portion 410 of the plurality of second active patterns 400 may be surrounded by the second source / drain pattern 250. The second contact portion 410 of the plurality of second active patterns 400 may be inserted into a first source / drain pattern 150.

[0108] According to some example embodiments, the gate electrode 120 may surround a plurality of first active patterns 200 and a plurality of second active patterns 400. The gate electrode 120 may overlap with the first connection portion 220 of the plurality of first active patterns 200 and the second connection portion 420 of the plurality of second active patterns 400 in a first direction D1.

[0109] According to some example embodiments, a first source / drain pattern 150 and a second source / drain pattern 250 may be disposed in a first direction D1. The first source / drain pattern 150 and the second source / drain pattern 250 may be spaced apart, with a separating insulating layer 105 located between them. The first source / drain pattern 150 may be disposed below the separating insulating layer 105. The second source / drain pattern 250 may be disposed on and above the separating insulating layer 105.

[0110] According to some example embodiments, the first source / drain pattern 150 and the second source / drain pattern 250 may have different conductivity types. For example, the first source / drain pattern 150 may be p-type, and the second source / drain pattern 250 may be n-type. The first source / drain pattern 150 may include a p-type dopant. The p-type dopant may include, but is not limited to, at least one of boron (B) and gallium (Ga). The second source / drain pattern 250 may include an n-type dopant. The n-type dopant may include, but is not limited to, at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). For other example embodiments, the first source / drain pattern 150 may be n-type, and the second source / drain pattern 250 may be p-type.

[0111] According to some example embodiments, the first source / drain pattern 150 may be connected to a plurality of first active patterns 200. The first source / drain pattern 150 may be disposed between the plurality of first active patterns 200 on a third-direction D3. The first source / drain pattern 150 may be disposed between adjacent gate electrodes 120 along the third-direction D3.

[0112] According to some example embodiments, the first source / drain pattern 150 may be the source / drain of a p-type metal-oxide-semiconductor (PMOS) transistor. The first source / drain pattern 150 may be the source / drain of a transistor that uses a plurality of first active patterns 200 as channel regions.

[0113] According to some example embodiments, the second source / drain pattern 250 can be connected to a plurality of second active patterns 400. The second source / drain pattern 250 can be disposed between the plurality of second active patterns 400 on a third-direction D3. The second source / drain pattern 250 can be disposed between adjacent gate electrodes 120 along the third-direction D3.

[0114] According to some example embodiments, the second source / drain pattern 250 can be the source / drain of an n-type metal-oxide-semiconductor (NMOS) transistor. The second source / drain pattern 250 can be the source / drain of a transistor that uses a plurality of second active patterns 400 as channel regions.

[0115] According to some example embodiments, a second source / drain contact 270 may be disposed below the first source / drain pattern 150. The second source / drain contact 270 may penetrate the fifth interlayer insulating layer 291 and the fourth etch stop layer 261 and connect to the first source / drain pattern 150. Description and reference of the second source / drain contact 270. Figure 8 The description of the second source / drain contact 270 is basically the same, so it is omitted.

[0116] According to some example embodiments, a second gate contact 280 may be disposed below the gate electrode 120. The second gate contact 280 may penetrate the fifth interlayer insulating layer 291 and the fourth etch stop layer 261 and connect to the gate electrode 120. Description and reference of the second gate contact 280. Figure 8 The description of the second source / drain contact 270 is basically the same, so it is omitted.

[0117] According to some example embodiments, a second wiring layer 321 may be disposed below the second source / drain contact 270 and the second gate contact 280. The second wiring layer 321 may penetrate the sixth interlayer insulating layer 292 and the fifth etch stop layer 262 and connect to the second source / drain contact 270 and the second gate contact 280. Description and references to the second wiring layer 321 Figure 8 The description of the second wiring layer 321 is basically the same, so it is omitted.

[0118] According to some example embodiments, a first source / drain contact 170 may be disposed on a second source / drain pattern 250. The first source / drain contact 170 may be disposed on the upper surface of the second source / drain pattern 250.

[0119] Figures 10 to 24 It shows the basis for explanation Figure 2 The illustration shows example diagrams of intermediate operations in a method for manufacturing a semiconductor device according to some example embodiments.

[0120] refer to Figure 10A first interlayer insulating layer 101, a first sacrificial layer 102, and a first contact portion 210 may be formed above the substrate 100. The first contact portion 210 may extend along the upper surface of the first sacrificial layer 102. The first contact portion 210 may cover the first sacrificial layer 102. The first contact portion 210 may include a transition metal. The first contact portion 210 may include at least one material selected from molybdenum (Mo), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), and titanium (Ti). The first sacrificial layer 102 may include a silicon oxide layer.

[0121] refer to Figure 11 A mask M can be formed on the first contact portion 210. A portion of the first contact portion 210 can be exposed through the mask M. Chemical treatment can be performed on the portion of the first contact portion 210 exposed through the mask M. For example, for the portion of the first contact portion 210 exposed through the mask M, a vulcanization treatment can be performed using a process gas or precursor including H2S.

[0122] refer to Figure 12 A first connection portion 220 can be formed in the portion exposed by the mask M. The first connection portion 220 can be formed by chemically treating the first contact portion 210. The first connection portion 220 may include the same transition metal element as the first contact portion 210. The first connection portion 220 may include a 2D material formed by chemical treatment.

[0123] refer to Figure 13 A first sacrificial layer 102 and a first contact portion 210 can be formed above a first active pattern 200.

[0124] refer to Figure 14 Similar to a reference Figure 11 and Figure 12 As described above, a mask M for exposing a portion of the first contact portion 210 can be formed on the first contact portion 210, and a first connecting portion 220 can be formed when the portion of the first contact portion 210 exposed through the mask M is chemically treated. A plurality of first active patterns 200 including the first contact portion 210 and the first connecting portion 220 can be sequentially formed along the first direction D1.

[0125] refer to Figure 15 A protective layer 110 and a dummy gate structure (DGS) can be formed over multiple first active patterns 200. The protective layer 110 can cover the uppermost first active pattern 200.

[0126] According to some example embodiments, a dummy gate structure DGS can be formed on the protective layer 110. The dummy gate structure DGS may include a dummy gate electrode 120D, a pre-gate spacer 140P, and a dummy gate capping layer 125D. The dummy gate capping layer 125D may be disposed on the dummy gate electrode 120D. The dummy gate electrode 120D and the dummy gate capping layer 125D may be disposed in a first direction D1.

[0127] According to some example embodiments, each of the dummy gate electrode 120D and the dummy gate capping layer 125D may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbonate (SiOC), and combinations thereof. For example, the dummy gate electrode 120D may include silicon oxide, and the dummy gate capping layer 125D may include silicon nitride.

[0128] According to some example embodiments, a pre-existing gate spacer 140P may be disposed along the surface of the dummy gate electrode 120D and the surface of the dummy gate capping layer 125D. The pre-existing gate spacer 140P may cover the surface of the dummy gate electrode 120D and the surface of the dummy gate capping layer 125D. The pre-existing gate spacer 140P may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0129] refer to Figure 16 A dummy gate structure (DGS) can be used to form a first source / drain patterned via 150H. The dummy gate structure (DGS) can be used as a mask to pattern multiple first active patterns 200 and a first sacrificial layer 102. The first source / drain patterned via 150H can be formed by cutting multiple first active patterns 200 and the first sacrificial layer 102 on a third-direction D3.

[0130] refer to Figure 17 This allows for the removal of a portion of the first sacrificial layer 102 and the formation of an inner spacer hole 141H. The first sacrificial layer 102 can be removed in... Figure 16 The portion exposed within the first source / drain patterned via 150H. The width of the first sacrificial layer 102 in the third direction D3 may be smaller than the width of the plurality of first active patterns 200. The inner spacer via 141H may be defined by the plurality of first active patterns 200 and the first sacrificial layer 102.

[0131] refer to Figure 18An inner spacer 141 can be formed on the side of the first sacrificial layer 102. The inner spacer 141 can be disposed between a plurality of first active patterns 200 in the first direction D1.

[0132] refer to Figure 19 A second sacrificial layer 112 and a sacrificial capping layer 115 may be formed, covering a plurality of first active patterns 200, inner spacers 141, and a dummy gate structure DGS. The second sacrificial layer 112 may include, for example, silicon oxide. The sacrificial capping layer 115 may include, for example, silicon nitride.

[0133] According to some example embodiments, the second sacrificial layer 112 can be filled with Figure 16 The first source / drain patterned via 150H. A sacrificial capping layer 115 can be formed on the second sacrificial layer 112. The sacrificial capping layer 115 can cover the second sacrificial layer 112. In the process of forming the second sacrificial layer 112 and the sacrificial capping layer 115, the sacrificial capping layer can be removed by a polishing process. Figure 18 The dummy gate capping layer 125D.

[0134] refer to Figure 20 It can remove Figure 19 The dummy gate electrode 120D. In removing... Figure 19 While removing the dummy gate electrode 120D, a portion of the protective layer 110 can also be removed. Figure 19 While removing a portion of the dummy gate electrode 120D and the protective layer 110, the surfaces of multiple first active patterns 200 can be exposed. (This is in contrast to the process of removing...) Figure 19 While setting up the dummy gate electrode 120D, a blank space can be formed between a plurality of first active patterns 200 spaced apart along the first direction D1.

[0135] refer to Figure 21 A gate electrode 120 and a gate insulating layer 130 can be formed. The gate electrode 120 and the gate insulating layer 130 can be formed as surfaces surrounding a plurality of first active patterns 200.

[0136] refer to Figure 22 A gate capping layer 125 can be formed on the gate electrode 120 and the gate insulating layer 130. The gate capping layer 125 can be formed as a portion of the gate electrode 120 is removed. In the process of forming the gate capping layer 125, it can be removed by a polishing process. Figure 21 Sacrifice the cover layer 115.

[0137] refer to Figure 23 It can remove Figure 22 The second sacrificial layer 112. In removing... Figure 22 The second sacrificial layer 112 can be removed simultaneously. Figure 21A portion of the prepared gate spacer 140P, and may form an outer spacer 142. With Figure 22 The second sacrificial layer 112 is removed, exposing the first contacts 210 of a plurality of first active patterns 200. The first contacts 210 may protrude further outward than the gate spacers 140.

[0138] refer to Figure 24 A first source / drain pattern 150 can be formed. The first source / drain pattern 150 can be formed between gate electrodes 120 spaced apart along a third direction D3. The first source / drain pattern 150 can cover at least a portion of a plurality of first active patterns 200. The first source / drain pattern 150 can surround a first contact portion 210 that protrudes further outward than the gate spacer 140. In the process of forming the first source / drain pattern 150, a polishing process can be used to remove... Figure 23 The gate capping layer 125. Through a polishing process, the upper surface of the gate electrode 120 and the upper surface of the first source / drain pattern 150 can be disposed on the same plane.

[0139] Subsequently, reference Figure 2 A first gate contact 180 connected to the gate electrode 120 and a first source / drain contact 170 connected to the first source / drain pattern 150 can be formed. A first wiring path 301 and a first wiring layer 311 can be formed above the first gate contact 180 and the first source / drain contact 170.

[0140] While various exemplary embodiments of the present disclosure have been described in detail above, the scope of the disclosure is not limited thereto, and it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the disclosure as defined by the appended claims. Furthermore, the foregoing exemplary embodiments can be implemented with some elements removed, and each exemplary embodiment can be implemented in combination with one another.

[0141] According to the example embodiment, the resistance in a semiconductor device can be reduced.

[0142] According to the example embodiments, reliability in semiconductor devices can be improved.

Claims

1. A semiconductor device, the semiconductor device comprising: Multiple active patterns, the multiple active patterns being spaced apart in a first direction intersecting with the surface of the substrate; A gate electrode that extends in a second direction intersecting the first direction and surrounds the plurality of active patterns; as well as Source / drain patterns, which are spaced apart from the gate electrode in a third direction intersecting the first and second directions, and connected to the plurality of active patterns in the third direction. Each of the plurality of active patterns includes: a contact portion, at least a portion of which extends into the source / drain pattern; and a connection portion extending in a third direction away from the contact portion and away from the source / drain pattern.

2. The semiconductor device according to claim 1, wherein, The connecting part contains a two-dimensional material.

3. The semiconductor device according to claim 1, wherein, The connecting portion and the contact portion each comprise a first metallic material.

4. The semiconductor device of claim 1, further comprising a gate spacer located on the third-direction side of the gate electrode.

5. The semiconductor device according to claim 4, wherein, The contact portion protrudes further toward the source / drain pattern than the gate spacer in the third direction.

6. The semiconductor device according to claim 4, wherein, At least a portion of the contact overlaps with the gate spacer in the first direction.

7. The semiconductor device according to claim 4, wherein, The width of the connection portion in the third direction is greater than the width between the outer surfaces of the gate spacers in the third direction.

8. The semiconductor device according to claim 4, wherein, The gate spacer includes: An inner spacer, the inner spacer being located between the plurality of active patterns and the substrate in the first direction; and An outer spacer is located on the uppermost active pattern among the plurality of active patterns in the first direction.

9. The semiconductor device according to claim 8, wherein, The width between the outer surfaces of the outer spacers in the third direction is greater than the width between the outer surfaces of the inner spacers in the third direction.

10. The semiconductor device of claim 8, further comprising a protective layer located in the first direction between the outer spacer and the uppermost active pattern.

11. The semiconductor device according to claim 1, wherein, In the third direction, the width of the gate electrode is smaller than the width of the connection portion.

12. The semiconductor device according to claim 2, wherein, The contact portion contains a transition metal.

13. The semiconductor device according to claim 1, wherein, The upper surface of the gate electrode and the upper surface of the source / drain pattern are coplanar.

14. A semiconductor device, the semiconductor device comprising: Multiple active patterns, the multiple active patterns being spaced apart in a first direction intersecting with the surface of the substrate; A gate structure comprising a gate electrode and a gate spacer, the gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of active patterns, the gate spacer being located on a side of the gate electrode in a third direction intersecting the first and second directions; as well as Source / drain patterns, which are spaced apart from the gate structure in the third direction and connected to the plurality of active patterns in the third direction. Each of the plurality of active patterns protrudes further toward the source / drain pattern than the gate structure in the third direction, and includes multiple layers of patterns in the third direction.

15. The semiconductor device according to claim 14, wherein, The multi-layered pattern includes: Contact portion, the contact portion being in contact with the source / drain pattern in the third direction; and A connection portion that extends in the third direction from the contact portion away from the source / drain pattern.

16. The semiconductor device according to claim 15, wherein, The contact portion comprises a transition metal, and The connecting part comprises a two-dimensional material, which includes a transition metal.

17. The semiconductor device according to claim 15, wherein, The contact portion extends into the source / drain pattern.

18. The semiconductor device according to claim 14, wherein, The gate structure further includes a gate insulating layer located inside the gate spacer and surrounding the gate electrode in the third direction.

19. The semiconductor device of claim 14, further comprising an interlayer insulating layer located between the substrate and the gate structure and the source / drain pattern.

20. A semiconductor device, the semiconductor device comprising: Multiple active patterns, the multiple active patterns being spaced apart in a first direction intersecting with the surface of the substrate; A gate structure comprising a gate electrode and a gate spacer, the gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of active patterns, the gate spacer being located on a side of the gate electrode in a third direction intersecting the first and second directions; as well as Source / drain patterns, which are spaced apart from the gate structure in the third direction and connected to the plurality of active patterns in the third direction. Each of the plurality of active patterns includes: a contact portion that contacts the source / drain pattern in the third direction; and a connection portion that extends from the contact portion away from the source / drain pattern in the third direction. The contact portion protrudes further toward the source / drain pattern than the gate structure in the third direction. The connecting portion comprises a two-dimensional material, and The contact portion and the connecting portion each contain a first transition metal.

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