Data writing method and equipment of flash memory storage unit and storage medium

Abstract

The invention discloses a data writing method and device for a flash memory storage unit and a storage medium. The data writing method comprises the steps that a historical data error set of the flash memory storage unit is obtained; analyzing the historical data error set, and identifying at least one error rate storage interval of which the error bit number is higher than a preset error threshold value in the flash memory storage unit based on an analysis result; generating a distributed storage rule based on the identified error rate storage interval; and recombining user data to be stored according to the scattered storage rule, and writing the recombined user data into the flash memory storage unit. According to the method and the device, the high-error-rate storage interval is identified, and the continuous data is dispersedly stored to different physical intervals, so that the technical effects of reducing the error rate of each storage unit and improving the writing reliability of the flash memory data are realized.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to a data writing method, device and storage medium for a flash memory cell. Background Technology

[0002] With the evolution of technologies such as 3D stacking, the density of NAND Flash memory cells has significantly increased, leading to a corresponding increase in bit errors caused by charge interference and programming interference during read and write operations. To ensure data reliability, storage systems typically employ error-correcting code technology, but its error-correcting capability has a physical upper limit.

[0003] In practical applications, flash memory media often exhibits a non-uniform error distribution characteristic. That is, bit errors are not randomly and uniformly distributed throughout the entire storage space, but tend to concentrate in certain specific physical storage areas. In this concentrated distribution, although the overall original error rate of the storage medium may still be within an acceptable range, the cumulative number of error bits in individual data segments within their respective physical areas can easily exceed the maximum error correction capability of the master error correction code, thus causing local data failure that cannot be recovered.

[0004] Traditional optimization strategies such as uniform wear leveling and bad block management primarily target the lifecycle and macroscopic reliability of storage cells, without addressing the microscopic concentration of errors within pages or blocks. Therefore, effectively addressing the insufficient local error correction capability caused by the concentrated distribution of erroneous bits has become a key challenge in improving the reliability of high-density flash memory data writing and storage.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main objective of this application is to provide a data writing method, device, and storage medium for flash memory cells, aiming to solve the technical problem of local data being uncorrectable due to the concentrated distribution of errors in existing flash memory.

[0007] To achieve the above objectives, this application proposes a data writing method for a flash memory cell, the method comprising: Obtain the historical data error set of the flash memory storage unit; Analyze the historical data error set, and based on the analysis results, identify at least one error rate storage interval in the flash memory storage unit where the number of error bits is higher than a preset error threshold; Based on the identified error rate storage interval, a distributed storage rule is generated, wherein the distributed storage rule is configured to allocate multiple data units belonging to the same continuous logical data segment to multiple physical storage intervals with different batches in the flash memory storage unit for storage, and exclude the error rate storage interval from the multiple physical storage intervals. The user data to be stored is reorganized according to the distributed storage rules, and the reorganized user data is written into the flash memory storage unit.

[0008] In one embodiment, the step of obtaining the historical data error set of the flash memory storage unit includes: Obtain the device parameters of the flash memory unit, and determine the scanning strategy based on the device parameters; The flash memory storage unit is scanned for errors using the scanning strategy, and the historical data error set is generated based on the scan results.

[0009] In one embodiment, the step of analyzing the historical data error set and identifying at least one error rate storage interval in the flash memory storage cell where the number of error bits exceeds a preset error threshold based on the analysis results includes: Count the number of error bits in each storage page of the historical data error set; Calculate the average and variance of at least one of the storage pages in the historical data error set based on the number of error bits; If the average value is lower than a preset first threshold and the variance is higher than a preset second threshold, then the error distribution is determined to be uneven, and the storage interval where the number of error bits exceeds a third threshold is determined as the error rate storage interval.

[0010] In one embodiment, the step of analyzing the historical data error set and identifying at least one high-error-rate storage interval in the flash memory storage cell where the number of error bits exceeds a preset error threshold includes: Based on the historical data error set, calculate the historical unit data error rate of each physical storage interval in the flash memory storage unit; The historical unit data error rate is compared with a preset error rate threshold, and the physical storage range where the historical unit data error rate exceeds the preset error rate threshold is determined as the error rate storage range.

[0011] In one embodiment, the step of generating distributed storage rules based on the identified error rate storage range includes: Obtain the interval error rate parameter for each storage interval in the flash memory storage unit, the interval error rate parameter being derived based on the historical data error set; Based on the interval error rate parameter, a distributed mapping relationship is created from the original user data sequence to multiple storage intervals; The distributed storage rules are generated based on the distributed mapping relationship.

[0012] In one embodiment, the step of creating a distributed mapping relationship from the original user data sequence to multiple storage intervals based on the interval error rate parameter includes: Obtain the historical erase count for each storage region in the flash memory unit; A multi-objective optimization function is constructed based on the interval error rate parameter and the number of historical erases, wherein the optimization objectives of the multi-objective optimization function include the overall data error risk and the degree of wear; Based on the error rate parameter and the number of historical erases, the multi-objective optimization function is solved to obtain the distributed mapping relationship.

[0013] In one embodiment, the step of reorganizing the user data to be stored according to the distributed storage rules and writing the reorganized user data into the flash memory storage unit includes: The user data is divided into multiple data units, and a user data unit sequence is formed according to the original order of the data units; The distributed mapping relationship in the distributed storage rule is invoked to allocate a corresponding target storage interval for each data unit in the data unit sequence; According to the distributed mapping relationship, each user data unit is classified according to the target storage area and temporarily stored in the buffer queue of the corresponding target storage area. In response to a data write command, the data units in each buffer queue are written to the corresponding target storage area.

[0014] In one embodiment, the method further includes: In response to preset rule update triggering conditions, the triggering conditions include at least one of the following: reaching a predetermined time period, the cumulative amount of written data exceeding a threshold, or detecting that the overall error rate change of the flash memory storage unit exceeds a set range; Obtain the updated data error set of the flash memory storage unit; Based on the updated data error set, the error rate storage interval is re-identified, and an updated distributed storage rule is generated based on the re-identified error rate storage interval. In response to a data write command, user data is written to the flash memory storage unit based on the updated distributed storage rules.

[0015] In addition, to achieve the above objectives, this application also proposes a data writing device for a flash memory cell, the device comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the data writing method for the flash memory cell as described above.

[0016] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the data writing method for the flash memory cell as described above.

[0017] One or more technical solutions proposed in this application have at least the following technical effects: The technical solution of this application involves: acquiring a historical data error set of a flash memory storage unit; analyzing the historical data error set and identifying at least one error rate storage interval in the flash memory storage unit where the number of error bits exceeds a preset error threshold based on the analysis results; generating a distributed storage rule based on the identified error rate storage interval, wherein the distributed storage rule is configured to allocate multiple data units belonging to the same continuous logical data segment to multiple physical storage intervals in the flash memory storage unit with different batches for storage, and excluding the error rate storage interval from among the multiple physical storage intervals; reassembling the user data to be stored according to the distributed storage rule, and writing the reassembly user data into the flash memory storage unit.

[0018] This application achieves the technical effect of reducing the error rate of each storage unit and improving the reliability of flash memory data writing by identifying high error rate storage areas and accordingly distributing continuous data to different physical areas. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating the first embodiment of the data writing method for the flash memory storage unit of this application; Figure 2 This is a detailed step diagram based on step S10 in the first embodiment; Figure 3 This is a detailed step diagram based on step S20 in the first embodiment; Figure 4 This is a schematic diagram of another detailed step based on step S20 in the first embodiment; Figure 5 This is a detailed step diagram based on step S30 in the first embodiment; Figure 6 This is a detailed step diagram based on step S40 in the first embodiment; Figure 7 This is a flowchart illustrating the second embodiment of the data writing method for the flash memory storage unit of this application; Figure 8 This is a schematic diagram of the device structure of the hardware operating environment involved in the data writing method of the flash memory storage unit in the embodiments of this application.

[0022] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0024] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0025] The main solution of this application embodiment is as follows: obtaining a historical data error set of a flash memory storage unit; analyzing the historical data error set and identifying at least one error rate storage interval in the flash memory storage unit where the number of error bits is higher than a preset error threshold based on the analysis results; generating a distributed storage rule based on the identified error rate storage interval, wherein the distributed storage rule is configured to allocate multiple data units belonging to the same continuous logical data segment to multiple physical storage intervals in the flash memory storage unit with different batches for storage, and excluding the error rate storage interval from among the multiple physical storage intervals; reassembling the user data to be stored according to the distributed storage rule, and writing the reassembly user data into the flash memory storage unit.

[0026] Traditional optimization strategies such as uniform wear leveling and bad block management primarily target the lifecycle and macroscopic reliability of storage cells, without addressing the microscopic concentration of errors within pages or blocks. Therefore, effectively addressing the insufficient local error correction capability caused by the concentrated distribution of erroneous bits has become a key challenge in improving the reliability of high-density flash memory data writing and storage.

[0027] This application provides a solution that identifies high-error-rate storage intervals and accordingly distributes continuous data to different physical intervals, thereby reducing the error rate of each storage unit and improving the reliability of flash memory data writing.

[0028] Based on this, embodiments of this application provide a data writing method for a flash memory storage cell, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the data writing method for the flash memory cell of this application. In this embodiment, the data writing method for the flash memory cell includes steps S10 to S40: Step S10: Obtain the historical data error set of the flash memory storage unit; In this embodiment, during the implementation of data reliability optimization for high-density NAND Flash memory cells, it is first necessary to systematically acquire historical data error sets reflecting their error distribution characteristics. This acquisition operation relies on the storage controller or connected testing tools, such as the Mass Production Tool (MPTool) or the Reliability Data Test (RDT) module. During the mass production testing phase before the flash media leaves the factory or within a specific reliability monitoring cycle, the controller performs full-disk or sampled read-write verification operations on the flash memory memory cells. Specifically, a known test data pattern is written to each physical page or larger storage block, and then the data is read and compared with the original data to accurately count the bit errors occurring in each bit or each data unit (such as a 512-byte or 1KB segment).

[0029] The historical error set is constructed in the form of structured data, typically including the following key fields: physical address identifier (e.g., block number, page number, page offset), number of error bits, timestamp of error occurrence, or programming / erase cycle count. During data acquisition, all or representative sample areas of the flash memory medium are covered to ensure that the historical error set reflects the error characteristics of the flash memory cells in spatial distribution. The acquired raw error information is summarized and stored in the controller's non-volatile memory or flash memory system reserve area, forming a dataset that can be used for subsequent analysis. The completeness and accuracy of this dataset are fundamental to identifying the concentrated characteristics of errors; therefore, during acquisition, it is necessary to ensure that the coverage and statistical granularity of the test data are sufficient to reveal the micro-error distribution within pages or blocks.

[0030] Step S20: Analyze the historical data error set, and based on the analysis results, identify at least one error rate storage interval in the flash memory storage unit where the number of error bits is higher than a preset error threshold; In this embodiment, after obtaining the historical data error set, the storage controller executes a data analysis process to identify physical intervals where error bits are concentrated in the flash memory medium. The analysis process first logically segments the flash memory storage units according to a preset data partitioning granularity, for example, uniformly dividing each physical page into 16 1KB data segments (corresponding to 16 DMA regions). For each segment, the corresponding average number of error bits and the statistical variance of the error distribution are calculated. By comparing the error statistics between different segments, it can be determined whether the errors exhibit spatial concentration.

[0031] The error rate storage range is identified by setting one or more preset error thresholds. These preset error thresholds can be dynamically set based on the maximum error correction capability of the master control error correction code, for example, set to 70%~90% of the upper limit of the error correction capability, or determined based on a certain percentage above the overall average error rate of the flash memory storage unit. The controller traverses the historical data error set, comparing the number of error bits counted in each segment with the preset error thresholds. Segments whose error bit counts consistently or repeatedly exceed the threshold are identified as error rate storage ranges by marking the corresponding physical address ranges.

[0032] Furthermore, to enhance the robustness of the identification, a sliding window statistical method or multi-period error trend analysis of the historical data error set is employed to avoid misjudgments caused by fluctuations in a single test. The identification results are recorded as a list of one or more address ranges and associated with their corresponding error severity levels.

[0033] Step S30: Based on the identified error rate storage interval, generate a distributed storage rule, wherein the distributed storage rule is configured to allocate multiple data units belonging to the same continuous logical data segment to multiple physical storage intervals with different batches in the flash memory storage unit for storage, and exclude the error rate storage interval from the multiple physical storage intervals. In this embodiment, based on the identified error rate storage range, specific distributed storage rules are generated, thereby breaking the mapping relationship between the original logical data segment and the error-prone physical range. Specifically, the logic for generating the distributed storage rules is as follows: first, the size of the basic processing unit of the user data to be stored is determined, for example, in units of 16 bits (2 bytes) or 32 bits. For a complete logical data segment (such as 4KB), it is sequentially divided into multiple of the aforementioned basic processing units.

[0034] The distributed storage rule is generated by constructing a permutation mapping table or a dynamic scheduling algorithm to calculate the identified error rate storage intervals. Specifically, the physical storage location to which each logical processing unit should be written is defined based on the mapping content in the permutation mapping table. Furthermore, the distributed storage rule ensures that multiple processing units from the same logical data segment are distributed and written to different, non-contiguous physical sub-intervals (e.g., different DMA regions) within the same physical page. When allocating target physical intervals, the marked error rate storage intervals are avoided. For example, if the error rate is identified as high in the last 8K region of a physical page, the rule restricts mapping logical data units to that region and prioritizes sub-intervals with lower error rates in the first 8K.

[0035] In practice, this is achieved through pre-computed interleaving patterns or real-time address translation functions. For example, logical data units are numbered sequentially, reordered using a preset permutation sequence, and then filled into the available low-error-rate sub-intervals of the target physical page in the new order. The distributed storage rules need to be implemented in the controller firmware or hardware address mapping layer to ensure automatic execution during the data writing process while remaining transparent to the upper-layer file system.

[0036] Step S40: Reorganize the user data to be stored according to the distributed storage rules, and write the reorganized user data into the flash memory storage unit.

[0037] In this embodiment, during the data writing phase, real-time reassembly and writing operations of user data are performed according to the generated distributed storage rules. Specifically, when user data to be stored is received from the host, the user data is divided into basic processing units matching the rules in logical order. Subsequently, the address mapping relationship defined in the distributed storage rules is invoked to calculate the corresponding target physical address for each logical processing unit. The target physical address is located within multiple predetermined physical storage sub-intervals that exclude high error rate intervals.

[0038] The reassembly process takes place within the controller's internal buffer or dedicated hardware circuitry. Essentially, it involves rearranging logically consecutive data units according to mapping relationships to form a data sequence that meets the requirements of distributed storage. In this data sequence, previously adjacent logical data units are physically spaced apart, thus creating a misalignment with the concentrated error distribution characteristics of the flash memory medium. After reassembly, the controller programs and writes the reordered data sequence to the calculated physical address via a flash interface channel (such as ONFI or Toggle interface).

[0039] During subsequent data retrieval, data units are read from the dispersed physical intervals according to the same distributed storage rules, and then reassembled into their original logical order according to the reverse mapping relationship before being submitted to the host. Thus, even if some physical sub-intervals experience high bit errors due to error concentration, the number of error bits that actually need to be corrected in each sub-interval is reduced because the errors in each logical data segment are distributed across multiple different physical sub-intervals. This ensures that the error correction capability does not exceed the upper limit of the master control error correction code, improving the overall reliability of data storage.

[0040] Furthermore, you can also view Figure 2 , Figure 2 This is a detailed step diagram based on step S10 in the first embodiment. Figure 2 The step of obtaining the historical data error set of the flash memory storage unit includes S11~12: Step S11: Obtain the device parameters of the flash memory storage unit, and determine the scanning strategy based on the device parameters; Step S12: Perform error scanning on the flash memory storage unit using the scanning strategy, and generate the historical data error set based on the scanning results.

[0041] In this embodiment, to improve the intelligence and efficiency of data acquisition during the specific process of obtaining historical data error sets, it is necessary to first obtain the device parameters of the flash memory storage unit. These device parameters include at least the flash memory chip model, process node (e.g., TLC or QLC), physical page size (e.g., 16KB), block size, predefined bad block distribution information, and reliability characteristic data provided by the flash memory manufacturer. The controller or host computer testing tool reads these device parameters. Based on these device parameters, an appropriate scanning strategy is dynamically determined. This scanning strategy includes the breadth of the scan (e.g., a full scan or targeted sampling scan based on a bad block table), the depth of the scan (e.g., performing a complete read verification of each page or focusing on specific sensitive areas), the test data pattern used (e.g., all "0", all "1", or alternating "0xAA", "0x55", etc., to expose different types of coupling interference), and the scan triggering conditions (e.g., executing during mass production testing, power-on initialization, or background idle periods).

[0042] Subsequently, an error scan is initiated on the flash memory storage unit according to the determined scanning strategy. The controller writes a preset test data pattern to the target physical address according to the scanning strategy, and initiates a read operation after a configurable delay or immediately. The read-back user data is compared bit by bit with the original written data to accurately record the bit position where the flip occurred and its corresponding physical address unit (specifically, the page offset). This scanning process is systematic and may be iterative to observe the trend of error changes with programming / erase cycles or retention time. All raw error information obtained from the scan is collected and processed in real time to generate a structured historical data error set. Each record in the historical error dataset is associated with the physical address, the number of error bits, the possible error mode, and environmental parameters (such as temperature and voltage) during the scan. Through the above-mentioned device parameter-driven strategy-based scanning, a balance can be achieved between resource overhead and information completeness, ensuring that the generated historical data error set has high representativeness and reliability, laying a solid data foundation for subsequent centralized error analysis.

[0043] Furthermore, you can also view Figure 3 , Figure 3 This is a detailed step diagram based on step S20 in the first embodiment. Figure 3 The steps of analyzing the historical data error set and identifying at least one error rate storage interval in the flash memory storage unit where the number of error bits exceeds a preset error threshold based on the analysis results include S21-23: Step S21: Count the number of error bits in each storage page of the historical data error set; Step S22: Calculate the average and variance of at least one of the storage pages in the historical data error set based on the number of error bits; Step S23: If the average value is lower than a preset first threshold and the variance is higher than a preset second threshold, then it is determined that the error distribution is uneven, and the storage interval where the number of error bits exceeds a third threshold is located is determined as the error rate storage interval.

[0044] In this embodiment, a refined method based on statistical feature discrimination is used to analyze the historical data error set and identify the error rate storage range. First, the historical data error set is preliminarily processed, and aggregated statistically analyzed using physical storage pages as the basic unit. The controller traverses the historical data error set, and for each scanned storage page, accumulates the total number of error bits appearing in all sub-units (such as each 1K segment) within that page in multiple scans or a single scan, obtaining the aggregated error bit count for each storage page.

[0045] Subsequently, statistical measures are introduced for in-depth analysis. For at least one storage page (usually all or sampled pages) of interest in the historical data error set, the micro-characteristics of the error distribution within the page are further analyzed. Based on the above operations, taking the division of a physical page into N sub-intervals as an example, the number of error bits in each sub-interval of the physical page is extracted to form a sample set containing N data points. Based on the sample set, two key statistics are calculated: first, the arithmetic mean of the number of error bits in all sub-intervals, used to measure the overall level of errors in the physical page; second, the variance (or standard deviation) of the number of error bits in the sub-intervals, used to measure the dispersion of the error distribution in different sub-intervals within the page. A high variance value indicates that the error bits are distributed extremely unevenly within the page, with obvious concentration phenomena.

[0046] The judgment logic is implemented based on the aforementioned statistics. Specifically, judgments are made using preset first, second, and third thresholds. The first threshold is used to determine the average error level, typically set to a relatively low value, indicating that the overall original error rate of the physical page is not high. The second threshold is used to determine the distribution dispersion, set to a relatively high value. When the analysis shows that the average number of error bits in a storage page is lower than the first threshold, while its variance is higher than the second threshold, a judgment condition is triggered, confirming that the error distribution within the physical page exhibits significant unevenness (i.e., concentrated errors). Based on this, to specifically locate high-risk intervals, the number of error bits in each sub-interval (or storage interval) within the page is compared with a higher third threshold (this threshold can be associated with the main control error correction capability). Specific sub-intervals with error bits exceeding the third threshold are formally marked and determined as the error rate storage interval. This method, through a combination of average and variance criteria, effectively filters out typical scenarios of "overall acceptable, locally deteriorating" and accurately locates high-risk sub-intervals within them.

[0047] You can also view Figure 4 , Figure 4 This is a schematic diagram of another detailed step based on step S20 in the first embodiment. Figure 4 The steps of analyzing the historical data error set and identifying at least one error rate storage interval in the flash memory storage cell where the number of error bits exceeds a preset error threshold based on the analysis results include S24-25: Step S24: Based on the historical data error set, calculate the historical unit data error rate of each physical storage interval in the flash memory storage unit; Step S25: Compare the historical unit data error rate with a preset error rate threshold, and determine the physical storage range where the historical unit data error rate exceeds the preset error rate threshold as the error rate storage range.

[0048] In this embodiment, the error rate storage interval is identified using an intuitive method based on direct calculation of the error rate and comparison with a threshold. First, the historical unit data error rate for each physical storage interval is calculated. The physical storage interval can be flexibly defined, including a complete storage page, a fixed-size sub-interval within a page (such as a 1K region corresponding to a DMA), or a larger storage block. This calculation process is based on multiple scans of data accumulated in the historical data error set. For each physical storage interval to be evaluated, the total number of error bits that occurred in the historical access or testing history is counted. Simultaneously, the total number of data bits verified in all relevant scans of the physical storage interval in history (i.e., unit data size multiplied by the number of accesses) is counted. The historical unit data error rate is obtained by dividing the cumulative total number of error bits by the cumulative total number of verified data bits. The final result of the historical unit data error rate can be represented as a percentage or errors per billion bits (RBER). The above calculation method aggregates error information over time, and can more stably reflect the inherent reliability degradation trend of the physical interval.

[0049] Subsequently, a threshold determination is performed based on the historical unit data error rate calculated above to identify high-risk intervals. Specifically, a preset error rate threshold is established, which can be set comprehensively based on the system's error correction capability, reliability targets, and technological level. The historical unit data error rate corresponding to each physical storage interval calculated above is compared one by one with the preset error rate threshold. This comparison operation includes simple scalar comparison or is performed based on confidence intervals. Specifically, if the historical unit data error rate of a certain physical storage interval consistently exceeds the preset error rate threshold, it indicates that the probability of bit errors occurring in that physical storage interval is significantly higher than the system's acceptable normal level, and its risk is high. The controller then marks that physical storage interval as the error rate storage interval.

[0050] In this embodiment, the error rate storage range is determined by directly focusing on the frequency density of error occurrence, which is suitable for identifying stable deterioration regions where both the overall and local error rates are consistently high.

[0051] Furthermore, you can also view Figure 5 , Figure 5 This is a detailed step diagram based on step S30 in the first embodiment. Figure 5 The step of generating distributed storage rules based on the identified error rate storage range includes S31-33: Step S31: Obtain the interval error rate parameter of each storage interval in the flash memory storage unit, wherein the interval error rate parameter is derived based on the historical data error set; Step S32: Based on the interval error rate parameter, create a distributed mapping relationship from the original user data sequence to multiple storage intervals; Step S33: Generate the distributed storage rules based on the distributed mapping relationship.

[0052] In this embodiment, during the specific implementation of generating distributed storage rules, the interval error rate parameter of each physical storage interval in the flash memory storage unit is first obtained. The definition of the physical storage interval must be consistent with the basic unit of subsequent mapping and writing, such as a fixed-size sub-interval within a flash physical page (e.g., a 1KB DMA region). The interval error rate parameter is a quantitative indicator calculated statistically based on the historical data error set, used to characterize the inherent reliability status of each specific physical storage interval. The specific form of the interval error rate parameter includes unit data error rate (e.g., number of error bits per kilobyte), cumulative number of error bits, error occurrence rate, or a score value that combines error severity and occurrence frequency. The controller reads the original error records from the non-volatile area storing the historical data error set, classifies and aggregates them according to the target physical storage interval, and applies a predefined algorithm model to calculate the corresponding interval error rate parameter, forming a reliability parameter table covering the entire or target storage space.

[0053] Subsequently, a specific mapping relationship is created using the interval error rate parameter. This mapping relationship defines how basic data units (e.g., 16 bits) in a logically continuous sequence of raw user data (e.g., a 4KB logical data block) are distributed and stored in multiple different physical storage intervals. Specifically, data units from the same logical segment are allocated to multiple physical storage intervals with lower interval error rate parameter values, strictly avoiding high-risk areas identified as error rate storage intervals. In the specific implementation, this is accomplished by constructing a static replacement table or a dynamic address mapping function. For example, based on the interval error rate parameter of each physical storage interval, the intervals with the optimal parameter value (lowest error rate) are selected as the target pool. Then, an interleaving or round-robin algorithm is designed to sequentially fill the logical data units into different physical storage interval addresses in the target pool, ensuring that logical adjacency relationships are effectively broken up in physical space.

[0054] Finally, the created distributed mapping relationship is solidified into distributed storage rules that can be invoked by the storage controller's execution engine. These distributed storage rules not only contain the logical definition of the mapping but also necessary metadata and control information, such as: a list of valid mapping intervals, the basic processing unit size, the identifier of the mapping algorithm, and the conditions under which the rules apply (e.g., specific flash memory chips or temperature ranges). These distributed storage rules can be written into the controller's configuration register or solidified in a specific module of the firmware. When a user data write request arrives, the controller's address translation layer or data path will automatically perform the conversion from the logical address to the distributed-mapped physical address according to these rules and schedule data reassembly operations, thereby enhancing reliability without intervention from upper-layer applications.

[0055] Based on the above Figure 5 The content described in step S32 is further refined to include the step of creating a distributed mapping relationship from the original user data sequence to multiple storage intervals based on the interval error rate parameter, including S32-1 to S32-3: Step S32-1: Obtain the historical erase count of each storage region in the flash memory storage unit; Step S32-2: Construct a multi-objective optimization function based on the interval error rate parameter and the number of historical erases, wherein the optimization objectives of the multi-objective optimization function include the overall data error risk and the degree of wear; Step S32-3: Based on the error rate parameter and the number of historical erases, solve the multi-objective optimization function to obtain the distributed mapping relationship.

[0056] In this embodiment, the historical erase count of each physical storage region in the flash memory storage unit is obtained. The historical erase count is a key indicator for measuring the wear and tear of the storage unit, and is usually maintained and recorded in a specific metadata area by the wear leveling module of the storage controller. The controller reads the programming / erase cycle count of each target physical storage region (such as each physical block or sub-block) since it has been put into use.

[0057] Subsequently, a multi-objective optimization function is constructed to find a globally optimal solution for data sparse mapping. This multi-objective optimization function is based on decision variables (i.e., the physical storage address to which each logical data unit should be mapped). Specifically, the optimization objectives of the multi-objective optimization function include at least minimizing the overall data error risk and optimizing the wear distribution. Specifically, minimizing the overall data error risk is formalized as minimizing the sum of the expected error bits of all written data, and its calculation depends on the obtained interval error rate parameter. Mapping a data unit to an interval with a lower error rate parameter results in a smaller contribution to the expected error risk. Optimizing the wear distribution aims to promote the uniformity of wear across all physical storage intervals, preventing individual intervals from failing prematurely due to excessively frequent writing. This objective can be formalized as minimizing the variance of the expected number of erases after this mapping write for all relevant physical storage intervals, or minimizing the maximum expected number of erases. When constructing the multi-objective optimization function, appropriate weighting coefficients must be configured for both minimizing the overall data error risk and optimizing the wear distribution, based on the system's preference for reliability and lifespan.

[0058] Finally, based on the input interval error rate parameter and the dataset of historical erase counts, the multi-objective optimization function is solved. Considering the potentially large problem size, heuristic algorithms (such as genetic algorithms or simulated annealing) or linear programming methods under a simplified model are employed in the solution process. Under the premise of satisfying predetermined constraints (such as avoiding error rate storage intervals and data integrity constraints), the solver searches for a mapping scheme that makes the optimization function value Pareto optimal or near-optimal. Finally, based on the solution process, the distributed mapping relationship is output. This distributed mapping relationship not only considers the error distribution at the current moment but also proactively considers the impact of write operations on flash memory lifespan, thereby achieving a synergistic optimization of improved data reliability and extended storage media lifespan.

[0059] Furthermore, you can also view 6. Figure 6 This is a detailed step diagram based on step S40 in the first embodiment. Figure 6 The steps of reorganizing the user data to be stored according to the distributed storage rules and writing the reorganized user data into the flash memory storage unit include S41-44: Step S41: Divide the user data into multiple data units and form a user data unit sequence according to the original order of the data units; Step S42: Invoke the distributed mapping relationship in the distributed storage rule to allocate a corresponding target storage interval for each data unit in the data unit sequence; Step S43: According to the distributed mapping relationship, each user data unit is classified according to the target storage area and temporarily stored in the buffer queue of the corresponding target storage area. Step S44: In response to the data write command, write the data units in each buffer queue to the corresponding target storage area.

[0060] In this embodiment, the data reassembly and write operations are implemented through a structured four-step process. First, data partitioning and serialization are performed. When the host interface of the storage controller receives the user data stream to be stored, the controller partitions the continuous user data stream according to the predefined or distributed storage rules specified by the basic processing unit size. The basic processing unit size is usually matched with the unit based on the internal access granularity of the flash memory or the distributed mapping relationship design, such as 16 bits, 32 bits, or a sector size (e.g., 512 bytes). During the partitioning process, the user data is partitioned sequentially starting from the logical starting address, thereby generating a series of continuous data units. The data units are logically organized into an ordered sequence of user data units in the controller's memory according to the order in which they are partitioned, and this sequence completely maintains the logical continuity of the original user data.

[0061] Next, target address allocation is performed by invoking the loaded or built-in distributed storage rules and accessing the distributed mapping relationships defined therein. These distributed mapping relationships are embodied in mapping functions, lookup tables, or dynamic scheduling algorithms. The controller traverses the user data unit sequence, sequentially indexing each data unit from the first to the last according to its logical order. By querying the mapping relationship or calculating the mapping function, a unique physical target address is determined for each unit. This physical target address points to a specific physical storage region within the flash memory unit (e.g., a specific DMA region within a physical page), ensuring that the error rate storage region does not belong to the previously identified error rate storage region.

[0062] Then, based on the target storage region identifier assigned to each data unit, the controller reclassifies and temporarily stores each unit in the user data unit sequence. During implementation, the controller maintains an independent buffer queue in its internal memory for each possible target physical storage region (or a set of associated regions). Based on the target region identifier of each data unit, the controller copies or moves its data content to the corresponding buffer queue. During this copying or moving process, logically contiguous data is demultiplexed and pre-grouped according to the physical target address, ensuring that all data units ultimately written to the same physical storage region are collected in the same buffer queue. This buffering mechanism helps convert randomized logical-physical mapping into sequential or batch write operations on the physical medium, improving efficiency.

[0063] Finally, data writing is performed. When specific data write command trigger conditions are met, such as a buffer queue reaching its capacity threshold, the host issuing a synchronization command, or the controller entering an idle scheduling cycle, the controller initiates the actual flash programming operation. For each physical storage region containing data to be written, the controller sequentially retrieves data units from the corresponding buffer queue and combines them into data packets or page fragments that meet the flash interface requirements according to the order in which the data units are in the queue. Subsequently, the combined data is accurately programmed and written to the actual physical address of the target storage region in the flash memory through the flash channel controller. After completing the writing of all relevant buffer queues...

[0064] Reference Figure 7 , Figure 7 This is a flowchart illustrating a second embodiment of the data writing method for a flash memory cell according to this application. In this embodiment, the data writing method for the flash memory cell includes steps S50-S80, and the method further includes: Step S50, in response to a preset rule update trigger condition, the trigger condition includes at least one of the following: reaching a predetermined time period, the cumulative amount of written data exceeding a threshold, or detecting that the overall error rate change of the flash memory storage unit exceeds a set range; Step S60: Obtain the updated data error set of the flash memory storage unit; Step S70: Re-identify the error rate storage interval based on the updated data error set, and generate an updated distributed storage rule based on the re-identified error rate storage interval; In step S80, in response to the data write command, user data is written to the flash memory storage unit based on the updated distributed storage rules.

[0065] In this embodiment, to achieve dynamic adaptation of the storage optimization strategy to the time-varying reliability characteristics of the flash memory medium, this data writing process also includes a periodic or event-driven rule update mechanism. This rule update mechanism needs to be triggered based on continuous monitoring and in response to one or more preset rule update trigger conditions. These trigger conditions are set as nodes that can reflect significant changes in the flash memory state. Specific trigger conditions include, but are not limited to, at least one of the following: First, a predetermined time period is reached, for example, the system has run for a fixed duration (e.g., 24 hours) or experienced a specific number of power cycles since the last rule generation or update. Second, the total amount of user data written to the flash memory storage unit exceeds a preset capacity threshold, which can be associated with the total capacity of the flash memory or the expected write endurance, indicating that the medium wear has reached a new stage. Third, through background inspection or read operations, the overall raw bit error rate of the flash memory storage unit or its changing trend (e.g., slope) exceeds a set safety range, indicating that the error distribution characteristics may have migrated or deteriorated. When the controller logic unit determines that any of the aforementioned trigger conditions are met, a rule update event is generated, triggering the subsequent re-evaluation process.

[0066] Subsequently, data acquisition is initiated to obtain the updated data error set. This is achieved by launching a new background scan, which includes an incremental scan focusing on the entire disk and known error hotspots. The scanning process can reuse the logical or operational reliability data test (RDT) of the production tool (MPTool) to collect error statistics for physical ranges that have been added or changed since the last assessment. The acquired scan results are then fused with some historical data (such as data from relatively stable regions) to generate the updated data error set that reflects the latest reliability status of the flash memory. The structure of the updated data error set is consistent with the historical dataset to ensure compatibility with subsequent analysis processes.

[0067] Subsequently, based on the updated data error set, error distribution analysis is re-executed to identify physical storage intervals where the number of error bits exceeds a threshold at the current moment, i.e., the updated error rate storage intervals. Due to wear or changes in charge retention capability, the high-risk intervals identified this time may differ from those before. Then, based on the newly identified error rate storage intervals and the current reliability parameters of each physical interval, the same or optimized rule generation algorithm (such as an interleaving mapping algorithm or a multi-objective optimization model) is used to recalculate the optimal mapping relationship for data dispersion. Finally, new, updated dispersion storage rules matching the current flash memory state are generated. These updated dispersion storage rules will replace or coexist with the old rules in the controller's rule base according to version.

[0068] Finally, the new rules are applied for data writing. When the system responds again to a data write command from the host, it invokes the updated distributed storage rules to guide this and subsequent write operations. The specific execution process is consistent with the write operation described in the first embodiment above, that is, according to the new rules, user data is divided, target address is allocated, data is reorganized and buffered, and finally the data is written to the target physical address specified by the new rules, avoiding the newly identified error rate storage range. Through this dynamic update mechanism, the degradation trajectory of the flash memory medium can be continuously tracked, so that the data distribution strategy always remains synchronized with the actual error distribution characteristics of the medium, thereby continuously and adaptively maintaining high data storage reliability throughout the entire flash memory lifecycle.

[0069] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the data writing method of the flash memory storage cell of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0070] This application provides a data writing device for a flash memory cell, the data writing device for a flash memory cell includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the data writing method for the flash memory cell in the above embodiment 1.

[0071] The following is for reference. Figure 8 The diagram illustrates a structural schematic of a data writing device suitable for implementing the flash memory storage cell in the embodiments of this application. The data writing device for the flash memory storage cell in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 8 The data writing device for the flash memory storage unit shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0072] like Figure 8As shown, the data writing device for the flash memory storage unit may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in the read-only memory (ROM) 1002 or a program loaded from the storage device 1003 into the random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the data writing device for the flash memory storage unit. The processing device 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the flash memory cell data writing device to wirelessly or wiredly communicate with other devices to exchange data. Although the figure shows flash memory cell data writing devices with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented alternatively.

[0073] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0074] The data writing device for flash memory cells provided in this application, employing the data writing method for flash memory cells in the above embodiments, can solve the technical problem of local data uncorrectability caused by the concentrated distribution of errors in existing flash memory. Compared with the prior art, the beneficial effects of the data writing device for flash memory cells provided in this application are the same as those of the data writing method for flash memory cells provided in the above embodiments, and other technical features in this data writing device for flash memory cells are the same as those disclosed in the method of the previous embodiment, and will not be repeated here.

[0075] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0076] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0077] This application provides a storage medium, which is a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the data writing method of the flash memory storage cell in the above embodiments.

[0078] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0079] The aforementioned computer-readable storage medium may be included in a data writing device for flash memory cells; or it may exist independently in a data writing device not assembled into flash memory cells.

[0080] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by a data writing device for a flash memory cell, cause the data writing device for the flash memory cell to implement the technical content of the data writing method embodiment for the flash memory cell as shown above.

[0081] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0082] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0083] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0084] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the data writing method of the flash memory storage cell described above. This solves the technical problem in existing flash memory where localized data becomes uncorrectable due to concentrated error distribution. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the data writing method of the flash memory storage cell provided in the above embodiments, and will not be elaborated upon here.

Claims

1. A method for writing data to a flash memory cell, characterized in that, The data writing method for the flash memory cell includes the following steps: Obtain the historical data error set of the flash memory storage unit; Analyze the historical data error set, and based on the analysis results, identify at least one error rate storage interval in the flash memory storage unit where the number of error bits is higher than a preset error threshold; Based on the identified error rate storage interval, a distributed storage rule is generated, wherein the distributed storage rule is configured to allocate multiple data units belonging to the same continuous logical data segment to multiple physical storage intervals with different batches in the flash memory storage unit for storage, and exclude the error rate storage interval from the multiple physical storage intervals. The user data to be stored is reorganized according to the distributed storage rules, and the reorganized user data is written into the flash memory storage unit.

2. The data writing method for a flash memory cell as described in claim 1, characterized in that, The step of obtaining the historical data error set of the flash memory storage unit includes: Obtain the device parameters of the flash memory unit, and determine the scanning strategy based on the device parameters; The flash memory storage unit is scanned for errors using the scanning strategy, and the historical data error set is generated based on the scan results.

3. The data writing method for a flash memory cell as described in claim 1, characterized in that, The step of analyzing the historical data error set and identifying at least one error rate storage interval in the flash memory storage cell where the number of error bits exceeds a preset error threshold based on the analysis results includes: Count the number of error bits in each storage page of the historical data error set; Calculate the average and variance of at least one of the storage pages in the historical data error set based on the number of error bits; If the average value is lower than a preset first threshold and the variance is higher than a preset second threshold, then the error distribution is determined to be uneven, and the storage interval where the number of error bits exceeds a third threshold is determined as the error rate storage interval.

4. The data writing method for a flash memory cell as described in claim 1, characterized in that, The step of analyzing the historical data error set and identifying at least one high-error-rate storage interval in the flash memory storage cell where the number of error bits exceeds a preset error threshold includes: Based on the historical data error set, calculate the historical unit data error rate of each physical storage interval in the flash memory storage unit; The historical unit data error rate is compared with a preset error rate threshold, and the physical storage range where the historical unit data error rate exceeds the preset error rate threshold is determined as the error rate storage range.

5. The data writing method for a flash memory cell as described in claim 1, characterized in that, The step of generating distributed storage rules based on the identified error rate storage range includes: Obtain the interval error rate parameter for each storage interval in the flash memory storage unit, the interval error rate parameter being derived based on the historical data error set; Based on the interval error rate parameter, a distributed mapping relationship is created from the original user data sequence to multiple storage intervals; The distributed storage rules are generated based on the distributed mapping relationship.

6. The data writing method for a flash memory cell as described in claim 5, characterized in that, The step of creating a distributed mapping relationship from the original user data sequence to multiple storage intervals based on the interval error rate parameter includes: Obtain the historical erase count for each storage region in the flash memory unit; A multi-objective optimization function is constructed based on the interval error rate parameter and the number of historical erases, wherein the optimization objectives of the multi-objective optimization function include the overall data error risk and the degree of wear; Based on the error rate parameter and the number of historical erases, the multi-objective optimization function is solved to obtain the distributed mapping relationship.

7. The data writing method for a flash memory cell as described in claim 1, characterized in that, The steps of reconstructing the user data to be stored according to the distributed storage rules and writing the reconstructed user data into the flash memory storage unit include: The user data is divided into multiple data units, and a user data unit sequence is formed according to the original order of the data units; The distributed mapping relationship in the distributed storage rule is invoked to allocate a corresponding target storage interval for each data unit in the data unit sequence; According to the distributed mapping relationship, each user data unit is classified according to the target storage area and temporarily stored in the buffer queue of the corresponding target storage area. In response to a data write command, the data units in each buffer queue are written to the corresponding target storage area.

8. The data writing method for a flash memory cell as described in claim 1, characterized in that, The method further includes: In response to preset rule update triggering conditions, the triggering conditions include at least one of the following: reaching a predetermined time period, the cumulative amount of written data exceeding a threshold, or detecting that the overall error rate change of the flash memory storage unit exceeds a set range; Obtain the updated data error set of the flash memory storage unit; Based on the updated data error set, the error rate storage interval is re-identified, and an updated distributed storage rule is generated based on the re-identified error rate storage interval. In response to a data write command, user data is written to the flash memory storage unit based on the updated distributed storage rules.

9. A data writing device for a flash memory storage cell, characterized in that, The data writing device of the flash memory storage unit stores a computer program, which, when executed by a processor, implements the data writing method of the flash memory storage unit according to any one of claims 1-8.

10. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the data writing method for the flash memory storage unit according to any one of claims 1-8.

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