Amplification device and current mirror circuit thereof

Abstract

The invention relates to an amplifying device in which a signal input end receives an input signal. The signal output end outputs an amplified signal. The amplifying circuit is coupled between the signal input end and the signal output end and comprises a first transistor and a second transistor which are spliced. The third transistor receives the first reference current. The fourth transistor receives a second reference current. The fifth transistor receives a third reference current and is coupled to the fourth transistor. The operational amplifier is coupled to the third transistor and the amplifying circuit. The distance between the fourth transistor and one transistor of the amplifying circuit is smaller than the distance between the fifth transistor and the transistor in the amplifying circuit. The fourth transistor is used for detecting temperature change for compensation.

Description

Technical Field

[0001] This invention relates to an amplification device and its current mirror circuit, and more particularly to an amplification device and its current mirror circuit capable of detecting and compensating for temperature changes. Background Technology

[0002] In radio frequency (RF) applications, amplification devices may include, for example, amplifier circuits for converting low-power RF signals into high-power RF signals. Amplifier circuits may include, for example, low-noise amplifiers (LNAs) and power amplifiers (PAs). Amplification devices may also include circuitry that provides bias voltage and / or bias current to the amplifier circuitry, such as current mirror circuits.

[0003] Current mirror circuits are common in analog circuits, and their accurate mirroring characteristics are crucial. The stability and accuracy of the output current determine the quality of the current mirror's performance. Current mirror devices can be implemented using, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). When current mirror circuits are applied to amplifier circuits (e.g., low-noise amplifiers), they may switch between an on and off state. In practice, it has been observed that, for example, thermal effects caused by temperature changes can lead to unexpected changes in the current flowing through the amplifier circuit, altering its operating state and thus reducing accuracy. Furthermore, the history effect of transistors in the amplifier circuit can also cause the current to be difficult to maintain at the desired value. Therefore, a better solution is desired to address at least one of these problems. Summary of the Invention

[0004] One embodiment provides an amplification device including a signal input terminal, a signal output terminal, an amplification circuit, a third transistor, a fourth transistor, a fifth transistor, and an operational amplifier. The signal input terminal is used to receive an input signal. The signal output terminal is used to output an amplified signal. The amplification circuit is coupled between the signal input terminal and the signal output terminal. The amplification circuit includes a cascode-connected first transistor and a second transistor, wherein a first node is coupled between the first transistor and the second transistor and the first node has a first voltage, and the amplification circuit is also coupled to a first reference voltage terminal. The third transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a second reference voltage terminal, the second terminal is coupled to a third node, wherein the third node is used to receive a first reference current and has a third voltage. The fourth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a third reference voltage terminal, and the second terminal is coupled to a fourth node, wherein the fourth node is used to receive a second reference current and has a fourth voltage. The fifth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the fourth reference voltage terminal, the second terminal is coupled to the control terminal of the fifth transistor and also to the control terminal of the fourth transistor, and the second terminal is used to receive a third reference current. The operational amplifier includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the fourth node, the second input terminal is coupled to the third node, and the output terminal is coupled to the amplifier circuit and also to the control terminal of the third transistor. In a chip, the distance between the fourth transistor and a transistor in the amplifier circuit is less than the distance between the fifth transistor and the transistor in the amplifier circuit.

[0005] Another embodiment provides an amplification device including a signal input terminal, a signal output terminal, an amplification circuit, a third transistor, a fourth transistor, a fifth transistor, and an operational amplifier. The signal input terminal is used to receive an input signal. The signal output terminal is used to output an amplified signal. The amplification circuit is coupled between the signal input terminal and the signal output terminal. The amplification circuit includes a first transistor and a second transistor stacked together, wherein a first node is coupled between the first transistor and the second transistor and the first node has a first voltage, and the amplification circuit is also coupled to a first reference voltage terminal. The third transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a second reference voltage terminal, the second terminal is coupled to a third node, wherein the third node is used to receive a first reference current and has a third voltage. The fourth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a third reference voltage terminal, the second terminal is coupled to a fourth node, wherein the fourth node is used to receive a second reference current, and the fourth node has a fourth voltage. The fifth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the fourth reference voltage terminal, the second terminal is coupled to the control terminal of the fifth transistor and coupled to the control terminal of the fourth transistor, and the second terminal is used to receive a third reference current. The operational amplifier includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the fourth node, the second input terminal is coupled to the third node, and the output terminal is coupled to the amplifier circuit and coupled to the control terminal of the third transistor. During an operation, the temperature difference between the fourth transistor and the amplifier circuit is less than the temperature difference between the fifth transistor and the amplifier circuit.

[0006] Another embodiment provides a current mirror circuit for adjusting a load current of an amplifier circuit. The current mirror circuit includes a third transistor, a fourth transistor, a fifth transistor, and an operational amplifier. The third transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a second reference voltage terminal, and the second terminal is coupled to a third node, wherein the third node receives a first reference current and has a third voltage. The fourth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a third reference voltage terminal, and the second terminal is coupled to a fourth node, wherein the fourth node receives a second reference current and has a fourth voltage. The fifth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a fourth reference voltage terminal, and the second terminal is coupled to both the control terminal of the fifth transistor and the control terminal of the fourth transistor, and the second terminal receives a third reference current. The operational amplifier includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the fourth node, the second input terminal is coupled to the third node, and the output terminal is coupled to the amplification circuit and to the control terminal of the third transistor. In a chip, the distance between the fourth transistor and a transistor in the amplification circuit is less than the distance between the fifth transistor and that transistor in the amplification circuit. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of an amplification device according to one embodiment.

[0008] Figure 2 This is a schematic diagram showing the layout of a portion of the transistors in an amplification device according to one embodiment.

[0009] Figure 3 This is a schematic diagram of an amplification device according to another embodiment.

[0010] Figure 4 This is a schematic diagram of the layout of a portion of the transistors in an amplification device according to another embodiment.

[0011] Figures 5-6 This is a schematic diagram of an amplification device according to other embodiments.

[0012] Symbol explanation:

[0013] 100, 200, 400, 500, 600: Amplification devices

[0014] 110: Amplifier Circuit

[0015] CM: Current Mirror Circuit

[0016] 505, 515, 615: Current source circuits

[0017] 520: Load Circuit

[0018] 555: Voltage Source Circuit

[0019] C1, C2: Capacitors

[0020] F1, F2: Filter circuits

[0021] ILOAD: Load current

[0022] IREF1, IREF2, IREF3: Reference currents

[0023] N1, N2, N3, N4: Nodes

[0024] NI: Signal Input Terminal

[0025] NO: Signal output terminal

[0026] OP1: Operational amplifier

[0027] R1: Resistor

[0028] REF1, REF2, REF3, REF4, REF5, REF6: Reference voltage terminals

[0029] SIN: Input signal

[0030] SOUT: Amplified signal

[0031] T1, T2, T3, T4, T5, T6, T7, T8: Transistors

[0032] T11, T12, T41, T42: Transistor units

[0033] VBIAS: Bias voltage terminal

[0034] VD1, VD3, VD4: Voltage

[0035] VDS1, VDS3, VGS1, VGS3: Voltage Difference Detailed Implementation

[0036] The present invention can be understood by referring to the following detailed description and the accompanying drawings. It should be noted that, for ease of understanding and to maintain the simplicity of the drawings, only a portion of the electronic device is depicted, and specific elements are not drawn to scale. Furthermore, the number and dimensions of the elements in the drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Elements indicated by the same symbols in the drawings have the same or similar properties or functions in the context. It should be understood that the following embodiments can be modified by substituting, recombining, or mixing features from several different embodiments to complete other embodiments without departing from the spirit of the invention. Features between embodiments can be used individually or in combination as long as they do not violate the spirit of the invention or conflict with it. In this document, when an element is mentioned as selectively or optionally provided, it means that the element may or may not be provided as needed, and all such modifications fall within the scope of the embodiments.

[0037] In this document, when a component is mentioned as being coupled to another component, it may be directly coupled or indirectly coupled through other components. The reference voltage terminals described herein can provide a substantially stable reference voltage, and may include, but are not limited to, ground. The multiple reference voltage terminals described herein may be the same reference voltage terminal or different reference voltage terminals.

[0038] In this article, when referring to an effect transistor, the first terminal may correspond to one of the source and drain, the second terminal may correspond to the other, and the control terminal may correspond to the gate. When referring to a bipolar transistor, the first terminal may correspond to one of the emitter and collector, the second terminal may correspond to the other, and the control terminal may correspond to the base.

[0039] In the following description and claims, the terms "comprising," "containing," and "having" are open-ended terms and should therefore be interpreted as "containing but not limited to...". Thus, when the terms "comprising," "containing," and / or "having" are used in the description of this invention, they specify the presence of the corresponding features, areas, steps, operations, and / or components, but do not exclude the presence of one or more other features, areas, steps, operations, and / or components.

[0040] Figure 1 This is a schematic diagram of an amplification device 100 according to one embodiment. (As shown...) Figure 1 As shown, in one embodiment, the amplification device 100 can be used to convert a low-power radio frequency signal into a high-power radio frequency signal. The amplification device 100 may include a current mirror circuit CM and an amplification circuit 110. Figure 1 In the diagram, the current mirror circuit, CM, and amplifier circuit 110 are distinguished by dashed boxes; however, this is merely for ease of description and is not intended to limit the invention. In other words, in other embodiments, the current mirror circuit, CM, and amplifier circuit 110 may include different components than those specified in the diagram. Figure 1The components shown, or the current mirror circuit and CM, and the amplifier circuit 110 may contain common components. For example, the current mirror circuit CM may include the transistor in the amplifier circuit 110.

[0041] In one embodiment, the amplification device 100 may include a signal input terminal NI and a signal output terminal NO, wherein the signal input terminal NI can be used to receive the input signal SIN. The signal output terminal NO is used to output the amplified signal SOUT. The amplified signal SOUT may be the signal generated by amplifying the input signal SIN. The amplification circuit 110 may be coupled between the signal input terminal NI and the signal output terminal NO, and may include a cascode-connected first transistor T1 and a second transistor T2. The amplification circuit 110 is not limited to... Figure 1 In other embodiments, the amplifier circuit 110 may include more stacked transistors. The first transistor T1 and the second transistor T2 may be directly stacked, or indirectly stacked via another transistor, an active element, and / or a passive element.

[0042] In the illustrated embodiment, the first transistor T1 may include a first terminal, a second terminal, and a control terminal. Its first terminal may be coupled to a first reference voltage terminal REF1, its second terminal may be coupled to a first node N1, and its control terminal may be coupled to a signal input terminal NI. The second transistor T2 may include a first terminal, a second terminal, and a control terminal. Its first terminal may be coupled to the first node N1, its second terminal may be coupled to a signal output terminal NO, and its control terminal may be coupled to a second node N2. In other words, the first node N1 may be coupled between the first transistor T1 and the second transistor T2. Furthermore, the first node N1 may have a first voltage VD1, which will be further described below.

[0043] For example, in the case where the first transistor T1 and the second transistor T2 are directly stacked, the second terminal of the first transistor T1 can be directly coupled to the first node N1, and the first terminal of the second transistor T2 can be directly coupled to the first node N1. In the case where the first transistor T1 and the second transistor T2 are indirectly stacked, for example, other transistors may be additionally included between the second terminal of the first transistor T1 and the first node N1, or additional transistors may be additionally included between the first node N1 and the first terminal of the second transistor T2.

[0044] In one embodiment, the current mirror circuit CM may include a third transistor T3, a fourth transistor T4, a fifth transistor T5, and an operational amplifier OP1. Specifically, the third transistor T3 may include a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a second reference voltage terminal REF2, and the second terminal is coupled to a third node N3. The fourth transistor T4 may include a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the third reference voltage terminal REF3, and the second terminal is coupled to the fourth node N4. The fifth transistor T5 may include a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the fourth reference voltage terminal REF4, and the second terminal is coupled to the control terminal of the fifth transistor T5. Further, the second terminal and the control terminal of the fifth transistor T5 may be further coupled to the control terminal of the fourth transistor T4.

[0045] In the above embodiments, the second terminal of the third transistor T3 can receive the first reference current IREF1 via the third node N3, and the third node N3 can have a third voltage VD3. In other words, the third node N3 can be used to receive the first reference current IREF1, and the path of the first reference current IREF1 can include the path where the third transistor T3 is located. The second terminal of the fourth transistor T4 can receive the second reference current IREF2 via the fourth node N4, and the fourth node N4 can have a fourth voltage VD4. In other words, the fourth node N4 can be used to receive the second reference current IREF2, and the path of the second reference current IREF2 can include the path where the fourth transistor T4 is located. Furthermore, the second terminal of the fifth transistor T5 can be configured to receive the third reference current IREF3, and the path of the third reference current IREF3 can include the path where the fifth transistor T5 is located, which will be further described below.

[0046] In one embodiment, operational amplifier OP1 may include a first input terminal, a second input terminal, and an output terminal. The first input terminal may be coupled to a fourth node N4, and further coupled to the second terminal of a fourth transistor T4. The second input terminal may be coupled to a third node N3, and further coupled to the second terminal of a third transistor T3. The output terminal of operational amplifier OP1 may be coupled to amplifier circuit 110, for example, to the control terminal of the first transistor T1 of amplifier circuit 110. Furthermore, the output terminal of operational amplifier OP1 may also be coupled to the control terminal of the third transistor T3, as will be further described below. For example, the first input terminal of operational amplifier OP1 may be one of a positive input terminal and a negative input terminal, and the second input terminal of operational amplifier OP1 may be the other of a positive input terminal and a negative input terminal. In the illustrated embodiment, the first input terminal of operational amplifier OP1 may be a positive input terminal, and the second input terminal of operational amplifier OP1 may be a negative input terminal.

[0047] In one embodiment, the load current ILOAD flows through the amplifier circuit 110, and the current mirror circuit CM can be used to adjust the load current ILOAD of the amplifier circuit 110. The path of the load current ILOAD may include the path containing the first transistor T1 and the second transistor T2. The current flowing through the first transistor T1 and the second transistor T2 may cause the temperature of the first transistor T1 and / or the second transistor T2 to rise. The heating of the first transistor T1 and the second transistor T2 depends on the operating power; for example, a higher operating power results in greater heating and a larger temperature change.

[0048] During operation, the fourth transistor T4 can be used to detect temperature changes in the amplifier circuit 110. For example, the temperature of the amplifier circuit 110 may depend on the average temperature of the first transistor T1 and the second transistor T2. In the chip, the distance from the fourth transistor T4 to a predetermined transistor (e.g., the first transistor T1 or the second transistor T2) in the amplifier circuit 110 may be less than the distance from the fifth transistor T5 to that predetermined transistor. Alternatively, during operation, the temperature difference between the fourth transistor T4 and the amplifier circuit 110 may be less than the temperature difference between the fifth transistor T5 and the amplifier circuit 110.

[0049] In one embodiment, during operation, one of the first transistor T1 and the second transistor T2 in the amplifier circuit 110 may have a higher temperature. In this case, during circuit layout design, the fourth transistor T4 can be positioned on the chip close to the higher-temperature transistor, so that the temperature of the fourth transistor T4 can track the temperature of the higher-temperature transistor. Specifically, if simulation shows that the temperature of the first transistor T1 is higher than that of the second transistor T2 during operation, the fourth transistor T4 can be positioned on the chip close to the first transistor T1, that is, the distance between the fourth transistor T4 and the first transistor T1 is smaller, for example, smaller than the distance between the fifth transistor T5 and the first transistor T1.

[0050] In another embodiment, the temperatures of the first transistor T1 and the second transistor T2 may be substantially the same during operation. In this case, the fourth transistor T4 can be positioned in the chip close to the two transistors, such that the temperature of the fourth transistor T4 can track the temperatures of the two transistors. Specifically, if, through simulation, the temperature of the first transistor T1 during operation is substantially equal to the temperature of the second transistor T2, the fourth transistor T4 can be positioned in the chip close to both the first transistor T1 and the second transistor T2, such that the sum of the distances between the fourth transistor T4 and the first transistor T1 and the fourth transistor T4 and the second transistor T2 is less than the sum of the distances between the fifth transistor T5 and the first transistor T1 and the fifth transistor T5 and the second transistor T2. In one particular embodiment, in the chip, the distance between the fourth transistor T4 and the first transistor T1 is less than the distance between the fifth transistor T5 and the first transistor T1, and the distance between the fourth transistor T4 and the second transistor T2 is less than the distance between the fifth transistor T5 and the second transistor T2, so that the fourth transistor T4 can detect the temperature changes of the first transistor T1 and the second transistor T2.

[0051] It should be noted that, although Figure 1 The first transistor T1 is illustrated as a single transistor, but those skilled in the art will recognize that it may comprise at least one transistor cell. For example, in the case of a field-effect transistor (FET), each transistor cell includes at least one gate. Furthermore, each transistor cell may also include a source and a drain, and adjacent transistor cells may share either a source or a drain. Moreover, in the case of a bipolar junction transistor (BJT), each transistor cell includes at least one base. It should also be noted that, in this document, when referring to the size of a transistor, it may mean the number of transistor cells it contains, such as the number of gates. Specifically, in cases where the gates are substantially arranged in a finger-like pattern, the number of transistor cells equals the number of finger gates. Alternatively, the size of a transistor may also be characterized by at least one of the following: gate width, width / length ratio (W / L ratio), etc.

[0052] Figure 2 This is a schematic diagram showing the layout of a portion of the transistors in an amplification device according to one embodiment. Figure 2 It can be a top view used to schematically illustrate the position of transistors in the chip layout, not to provide precise dimensions. Figure 2 The layout diagram may be adjusted appropriately, but it still falls within the scope of this invention.

[0053] like Figure 2 As shown, the first transistor T1 may include a first group of transistor units T11 and a second group of transistor units T12. The fourth transistor T4 may include a first group of transistor units T41 and a second group of transistor units T42. As in the example above, the temperature of the first transistor T1 during operation may be higher than the temperature of the second transistor T2. In this case, the fourth transistor T4 may be located close to the first transistor T1 in the chip to detect temperature changes in the first transistor T1.

[0054] Specifically, in the chip, the first group of transistor units T41 of the fourth transistor T4 can be adjacent to the first group of transistor units T11 of the first transistor T1, and also adjacent to the second group of transistor units T12 of the first transistor T1. For example, the first group of transistor units T41 can be placed between the first group of transistor units T11 and the second group of transistor units T12 of the first transistor T1. Furthermore, the second group of transistor units T42 of the fourth transistor T4 can be adjacent to the second group of transistor units T12 of the first transistor T1. Figure 2 The schematic location of the fifth transistor T5 in the chip is also shown. As shown, the distance between the fourth transistor T4 (including the first group of transistor units T41 and the second group of transistor units T42) and the first transistor T1 (including the first group of transistor units T11 and the second group of transistor units T12) is smaller than the distance between the fifth transistor T5 and the first transistor T1.

[0055] In one embodiment, with respect to the fourth transistor T4, the first group of transistor units T41 may include m transistor units, and the second group of transistor units T42 of the fourth transistor T4 may include n transistor units, where m and n can be positive integers. The temperature of the fourth transistor T4 may depend on the average of the temperatures of the first group of transistor units T41 and the second group of transistor units T42. In a further embodiment, m may be substantially equal to n. As mentioned above, the number of transistor units can be counted, for example, by the number of finger gates. Figure 2 The schematic location of the third transistor T3 in the chip is also shown, which will be further referenced below. Figure 4 To describe it.

[0056] Figure 3This is a schematic diagram of an amplification device 300 according to another embodiment. The amplification device 300 may be similar to the amplification device 100, and the similarities will not be repeated. The amplification device 300 may further include a sixth transistor T6, which may include a first terminal, a second terminal, and a control terminal. The first terminal of the sixth transistor T6 may be coupled to a fourth node N4, thereby further coupled to the second terminal of the fourth transistor T4. The second terminal of the sixth transistor T6 can be used to receive a second reference current IREF2. Furthermore, the control terminal of the sixth transistor T6 may be coupled to a second node N2. As described above, the control terminal of the second transistor T2 may be coupled to the second node N2. Therefore, the control terminal of the sixth transistor T6 is coupled to the control terminal of the second transistor T2 via the second node N2. In this case, the path of the second reference current IREF2 may include the path where the sixth transistor T6 and the fourth transistor T4 are located. Furthermore, the second node N2 may be additionally coupled to a bias voltage terminal VBIAS, which can be used to provide a bias voltage signal having a predetermined potential or a variable potential.

[0057] In one embodiment, the first transistor T1 and the third transistor T3 can be manufactured using substantially the same process, resulting in substantially the same process voltage-temperature (PVT) performance. Specifically, the first transistor T1 and the third transistor T3 may have substantially the same process variation parameter, also known as the process corner parameter, to assess the differences in transistor performance due to the manufacturing process. For example, in the case of MOSFETs, the process corner parameter may include TT, FF, SS, FS, and SF, where the first letter represents the operating speed of the N-type transistor, the second letter represents the operating speed of the P-type transistor, and T represents the typical operating speed, F represents the fast operating speed, and S represents the slow operating speed. Generally, those skilled in the art will understand the meaning of these parameters, and will not elaborate further here.

[0058] Furthermore, the second transistor T2 and the sixth transistor T6 can be manufactured using substantially the same process, resulting in substantially the same process difference parameters. Specifically, the second transistor T2 and the sixth transistor T6 can have substantially the same process voltage-temperature performance.

[0059] Furthermore, in the chip layout, the third transistor T3 can be placed close to the first transistor T1, allowing them to form a better current mirror architecture. Specifically, the distance from the third transistor T3 to the first transistor T1 can be less than the distance from the third transistor T3 to the second transistor T2. Similarly, in the chip layout, the sixth transistor T6 can be placed close to the second transistor T2, allowing them to form a better current mirror architecture. Specifically, the distance from the sixth transistor T6 to the second transistor T2 can be less than the distance from the sixth transistor T6 to the first transistor T1.

[0060] Figure 4 This is a schematic diagram of the layout of a portion of the transistors in an amplification device according to another embodiment. Figure 4 It can be a top view used to schematically illustrate the position of transistors in the chip layout, not to provide precise dimensions. Figure 4 The layout diagram may be adjusted appropriately, but it still falls within the scope of this invention.

[0061] like Figure 4 As shown, the sixth transistor T6 and the second transistor T2 can be arranged in the same region, shown as region A1. As mentioned above, the second transistor T2 and the sixth transistor T6 can form a current mirror architecture. Placing the sixth transistor T6 and the second transistor T2 in the same region (e.g., region A1) can help achieve better current mirror performance. The third transistor T3 and the first transistor T1 can be arranged in the same region, shown as region A2, to achieve better current mirror performance. Furthermore, the fourth transistor T4 can also be arranged in region A2 to track the temperature of the first transistor T1, as referenced above. Figure 2 Specifically, the third transistor T3 may be located adjacent to the first transistor T1 in the first group of transistor units T11, and the fourth transistor T4 may be located between the first transistor T1 in the first group of transistor units T11 and the second group of transistor units T12.

[0062] In some embodiments, as described above, the third transistor T3 and the first transistor T1 can form a current mirror architecture. The first transistor T1 and the third transistor T3 can each include a substrate (body or bulk), and their substrates can have the same connection state. For example, the substrates of the first transistor T1 and the third transistor T3 can be floating, wherein the substrates may not have a predetermined voltage. Similarly, as described above, the sixth transistor T6 and the second transistor T2 can form a current mirror architecture. The second transistor T2 and the sixth transistor T6 can each include a substrate, and their substrates can have the same connection state. For example, the substrates of the second transistor T2 and the sixth transistor T6 can be contacted, wherein the substrates can have a predetermined voltage. However, the invention is not limited thereto. For example, in other embodiments, the substrates of the first transistor T1 and the third transistor T3 can also be contacted, or the substrates of the second transistor T2 and the sixth transistor T6 can also be floating.

[0063] Generally, in a current mirror architecture, the current flowing through a transistor is positively correlated with its width-to-length ratio (W / L ratio). If two transistors have the same W / L ratio, the current flowing through each transistor will be the same. If two transistors have different W / L ratios, the current flowing through each transistor will be scaled accordingly. For example, if the W / L ratio of one transistor is twice that of another transistor, the current flowing through the former will be twice that of the latter.

[0064] exist Figure 3 In this embodiment, in the path of the load current ILOAD, the load current ILOAD may be substantially equal to the current IDS2 flowing through the second transistor T2 and equal to the current IDS1 flowing through the first transistor T1. In the path of the first reference current IREF1, the first reference current IREF1 may be substantially equal to the current IDS3 flowing through the third transistor T3.

[0065] To elaborate further, refer to Figure 3 The first transistor T1 may have a first size S1, and the third transistor T3 may have a third size S3. In the current mirror architecture formed by the first transistor T1 and the third transistor T3, the current IDS1 flowing between the first and second terminals of the first transistor T1, and the current IDS3 flowing between the first and second terminals of the third transistor T3, may be related to the aforementioned dimensions. Specifically, the ratio of the first size S1 to the third size S3 may be substantially equal to the ratio of current IDS1 to current IDS3, which can be generally expressed as S1 / S3 = IDS1 / IDS3. For example, if the first size S1 is X times the third size S3, then the current IDS1 may be X times the current IDS3. Here, X may be, for example, 1, 20, 50, or other suitable values.

[0066] As described above, the current IDS2 flowing through the second transistor T2 can be correlated with the current IDS6 flowing through the sixth transistor T6, therefore, the load current ILOAD can be correlated with the first reference current IREF1.

[0067] Similarly, the second transistor T2 may have a second size S2, and the sixth transistor T6 may have a sixth size S6. In the current mirror architecture formed by the second transistor T2 and the sixth transistor T6, the current IDS2 flowing between the first and second terminals of the second transistor T2, and the current IDS6 flowing between the first and second terminals of the sixth transistor T6, may be related to the aforementioned dimensions. Specifically, the ratio of the second size S2 to the sixth size S6 may be substantially equal to the ratio of the current IDS2 to the current IDS6, which can be generally expressed as S2 / S6 = IDS2 / IDS6. For example, if the second size S2 is Y times the sixth size S6, then the current IDS2 may be Y times the current IDS6. Here, Y may be, for example, 1, 20, 50, or other suitable values.

[0068] Additionally, in the path of the second reference current IREF2, the second reference current IREF2 may be substantially equal to the current IDS6 flowing through the sixth transistor T6 and equal to the current IDS4 flowing through the fourth transistor T4. In the path of the third reference current IREF3, the third reference current IREF3 may be substantially equal to the current IDS5 (not shown) flowing through the fifth transistor T5.

[0069] In one embodiment, operational amplifier OP1 can be used to maintain the third voltage VD3 of the third node N3 and the fourth voltage VD4 of the fourth node N4 substantially equal. For example, when the fourth voltage VD4 decreases, the third voltage VD3 can decrease accordingly. In other words, through operational amplifier OP1, the third voltage VD3 can track the fourth voltage VD4 to be substantially equal to the fourth voltage VD4.

[0070] Furthermore, the output terminal of operational amplifier OP1 can be coupled to the control terminal of the first transistor T1 and the control terminal of the third transistor T3, such that the voltage at the control terminal of the first transistor T1 is substantially equal to the voltage at the control terminal of the third transistor T3. In some embodiments, the first reference voltage terminal REF1 and the second reference voltage terminal REF2 can provide reference voltages at the same potential. For example, the first reference voltage terminal REF1 and the second reference voltage terminal REF2 can be grounded. In this case, the voltage difference VGS3 between the control terminal and the first terminal of the third transistor T3 can be substantially equal to the voltage difference VGS1 between the control terminal and the first terminal of the first transistor T1. As described above, in some embodiments, the first transistor T1 and the third transistor T3 can be fabricated using substantially the same process. In this case, the voltage difference VDS3 between the second terminal and the first terminal of the third transistor T3 can be substantially equal to the voltage difference VDS1 between the second terminal and the first terminal of the first transistor T1. Since the third voltage VD3 of the third node N3 can depend on the value of the voltage difference VDS3, and the first voltage VD1 of the first node N1 can depend on the value of the voltage difference VDS1, the third voltage VD3 can be substantially equal to the first voltage VD1. Furthermore, the third voltage VD3, the fourth voltage VD4, and the first voltage VD1 can be substantially equal.

[0071] For example, the first terminal, the second terminal, and the control terminal of the first transistor T1 can be, for example, the source, the drain, and the gate, respectively. In this case, the voltage difference VGS1 can be, for example, the gate-source voltage difference of the first transistor T1, and the voltage difference VDS1 can be, for example, the drain-source voltage difference of the first transistor T1. However, the present invention is not limited thereto. In other embodiments, the first terminal, the second terminal, and the control terminal of the first transistor T1 can be, for example, the emitter, the collector, and the base, respectively.

[0072] Figure 5This is a schematic diagram of an amplification device 500 according to another embodiment. The amplification device 500 may be similar to amplification device 100 and / or amplification device 300, and the similarities will not be repeated. The amplification device 500 may also include a load circuit 520, which may be coupled to a second terminal of the second transistor T2. For example, the load circuit 520 may include a low dropout regulator (LDO) or other circuitry. The amplification device 500 may also include current source circuits 505 and 515, respectively coupled to a third transistor T3 and a fifth transistor T5, to provide a first reference current IREF1 and a third reference current IREF3, respectively. The current source circuits 505 and 515 may be further coupled to a voltage source circuit 555 to receive a supply voltage. Generally, it is desirable that the gain of the amplification circuit 110 does not change with temperature, thereby maintaining better linearity. However, in practical applications, current can cause the temperature of the amplification circuit 110 to rise, resulting in an undesirable decrease in its gain.

[0073] In some embodiments, as described above, at the start of operation, the third voltage VD3 of the third node N3 may be substantially equal to the first voltage VD1 of the first node N1. During operation, the temperature of the first transistor T1 and / or the second transistor T2 may rise. Taking the first transistor T1 as an example where the temperature is higher, the fourth transistor T4 may be positioned close to the first transistor T1 to detect temperature changes in the first transistor T1 and thus compensate for them. For example, the distance from the fourth transistor T4 to the first transistor T1 is less than the distance from the fifth transistor T5 to the first transistor T1.

[0074] In detail, when the temperature of the first transistor T1 rises, the temperature of the fourth transistor T4 also rises, causing the threshold voltage (Vth) of the fourth transistor T4 to decrease. This threshold voltage (Vth) can be, for example, the gate-source threshold voltage (Vgs(th)). Therefore, the current IDS4 flowing through the fourth transistor T4 increases, and the current IDS6 flowing through the sixth transistor T6 also increases. In this case, the fourth voltage VD4 of the fourth node N4 decreases.

[0075] Through operational amplifier OP1, the third voltage VD3 of the third node N3 can decrease in sync with the fourth voltage VD4. Therefore, the third voltage VD3 of the third node N3 can be lower than the first voltage VD1 of the first node N1. In the current mirror architecture formed by the first transistor T1 and the third transistor T3, the third voltage VD3 being lower than the first voltage VD1 can cause an increase in the current IDS1 flowing through the first transistor T1. In this configuration, since the fifth transistor T5 is farther from the first transistor T1, its threshold voltage can remain substantially unchanged or change only slightly.

[0076] Figure 6 This is a schematic diagram of an amplification device 600 according to another embodiment. The amplification device 600 may be similar to amplification device 100, amplification device 300, and / or amplification device 500, and the similarities will not be repeated. The amplification device 600 may also include a current source circuit 615, a seventh transistor T7, and an eighth transistor T8. In this embodiment, the seventh transistor T7 may be, for example, a... Figure 5 The current source circuit 505 shown is a specific embodiment, and the seventh transistor T7 and the eighth transistor T8 can form a current mirror architecture.

[0077] In detail, when the temperature of the first transistor T1 rises, the temperature of the fourth transistor T4 also rises, causing the threshold voltage of the fourth transistor T4 to decrease. Therefore, the current IDS4 flowing through the fourth transistor T4 and the current IDS6 flowing through the sixth transistor T6 increase, which in turn increases the second reference current IREF2. Through the current mirror structure formed by the seventh transistor T7 and the eighth transistor T8, the first reference current IREF1 also increases. In the path of the first reference current IREF1, the increase in the first reference current IREF1 can lead to an increase in the current IDS3 flowing through the third transistor T3. Furthermore, through the current mirror structure formed by the first transistor T1 and the third transistor T3, the current IDS1 flowing through the first transistor T1 will increase.

[0078] For example, the increase in current IDS1 can be based on the ratio of the first dimension S1 of the first transistor T1 to the third dimension S3 of the third transistor T3. Therefore, the current IDS1 flowing through the first transistor T1 increases, thereby compensating for the gain of the amplifier circuit 110.

[0079] In other embodiments, during operation, the second transistor T2 may be the one with a higher temperature, and the fourth transistor T4 may be positioned close to the second transistor T2 to detect and compensate for temperature changes in the second transistor T2. For example, the distance between the fourth transistor T4 and the second transistor T2 may be less than the distance between the fifth transistor T5 and the second transistor T2.

[0080] In some embodiments, during operation, the temperatures of the first transistor T1 and the second transistor T2 may be substantially the same, and the fourth transistor T4 may be positioned close to both the first transistor T1 and the second transistor T2 to detect temperature changes in both. For example, the sum of the distances from the fourth transistor T4 to the first transistor T1 and the fourth transistor T4 to the second transistor T2 is less than the sum of the distances from the fifth transistor T5 to the first transistor T1 and the fifth transistor T5 to the second transistor T2. Specifically, the distance from the fourth transistor T4 to the first transistor T1 is less than the distance from the fifth transistor T5 to the first transistor T1, and the distance from the fourth transistor T4 to the second transistor T2 is less than the distance from the fifth transistor T5 to the second transistor T2.

[0081] In some embodiments, during operation, other parts of the amplifier circuit 110, such as the load circuit 520, may be at higher temperatures, and the fourth transistor T4 may be positioned close to the load circuit 520 to detect and compensate for temperature changes in the load circuit 520.

[0082] like Figure 5 As shown, in some embodiments, the amplification device 500 may further include a first filter circuit F1, which may be coupled to the signal input terminal NI, for example, between the signal input terminal NI and the output terminal of the operational amplifier OP1, to avoid unintended effects of the input signal SIN on the operational amplifier OP1. For example, it may avoid or mitigate interference from radio frequency components in the input signal SIN on the operational amplifier OP1. Specifically, the first filter circuit F1 may include a first capacitor C1 and a first resistor R1. The first terminal of the first capacitor C1 is coupled to the fifth reference voltage terminal REF5. The first terminal of the first resistor R1 may be coupled to the second terminal of C1, and the second terminal of the first resistor R1 may be coupled to the signal input terminal NI.

[0083] In some embodiments, the amplification device 500 may further include a second filter circuit F2, which may be coupled to the second node N2, for example, coupled between the control terminal of the second transistor T2 and the control terminal of the sixth transistor T6, to avoid unintended effects of the amplified signal SOUT on the sixth transistor T6. More specifically, the second filter circuit F2 may include a second capacitor C2, whose first terminal may be coupled to the sixth reference voltage terminal REF6, and whose second terminal may be coupled to the second node N2. In the above embodiments, the first filter circuit F1 and the second filter circuit F2 are examples; other suitable filter circuit architectures are also within the scope of these embodiments.

[0084] In at least one of the above embodiments, the first reference voltage terminal REF1, the second reference voltage terminal REF2, the third reference voltage terminal REF3, the fourth reference voltage terminal REF4, the fifth reference voltage terminal REF5, and the sixth reference voltage terminal REF6 can provide the same or different reference voltages. For example, at least one of them can be a ground terminal.

[0085] In summary, in at least one embodiment of the present invention, by using a fourth transistor in the current mirror circuit to detect the temperature of the amplifier circuit (e.g., at least one of the first transistor T1 and the second transistor T2), or to detect the temperature of the circuit associated with the amplifier circuit (e.g., the load circuit), the gain of the amplifier circuit 110 can be compensated, thereby making the gain of the amplifier circuit 110 less affected by temperature, which helps to improve the performance of the circuit.

[0086] In this document, some features, elements, structures, materials, configurations, etc., may be described illustratively in one embodiment, but are not limited to that embodiment. For example, elements described in one embodiment may be omitted from that embodiment, or may be applied to another embodiment.

[0087] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.

Claims

1. An amplification device, characterized in that, include: A signal input terminal is used to receive an input signal; One signal output terminal is used to output an amplified signal; An amplifier circuit is coupled between the signal input terminal and the signal output terminal. The amplifier circuit includes a first transistor and a second transistor stacked together, wherein a first node is coupled between the first transistor and the second transistor and the first node has a first voltage, and wherein the amplifier circuit is also coupled to a first reference voltage terminal. A third transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a second reference voltage terminal, the second terminal is coupled to a third node, wherein the third node is used to receive a first reference current, and the third node has a third voltage. A fourth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a third reference voltage terminal, the second terminal is coupled to a fourth node, wherein the fourth node is used to receive a second reference current, and the fourth node has a fourth voltage. A fifth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a fourth reference voltage terminal, the second terminal is coupled to the control terminal of the fifth transistor and also coupled to the control terminal of the fourth transistor, and the second terminal is used to receive a third reference current; and An operational amplifier includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the fourth node, the second input terminal is coupled to the third node, and the output terminal is coupled to the amplifier circuit and coupled to the control terminal of the third transistor. In a chip, the distance between the fourth transistor and one of the first and second transistors in the amplifier circuit is less than the distance between the fifth transistor and the first and second transistors, where the fifth transistor is less than the distance between the fifth transistor and the first and second transistors.

2. The amplification device according to claim 1, characterized in that: The first transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the first reference voltage terminal, the second terminal is coupled to the first node, and the control terminal is coupled to the signal input terminal and the output terminal of the operational amplifier; and The second transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the first node, the second terminal is coupled to the signal output terminal, and the control terminal is coupled to a second node.

3. The amplification device according to claim 2, characterized in that: During an operation, one of the first transistors and the second transistor has a higher temperature, and in the chip, the distance between the fourth transistor and the higher-temperature transistor is less than the distance between the fifth transistor and the higher-temperature transistor.

4. The amplification device according to claim 3, characterized in that: The fourth transistor includes a first group of transistor units and a second group of transistor units; and In the chip, the distance between the first group of transistor cells of the fourth transistor and the one with the higher temperature is less than the distance between the fifth transistor and the one with the higher temperature.

5. The amplification device according to claim 4, characterized in that: In the chip, the distance between the second group of transistor cells of the fourth transistor and the one with the higher temperature is less than the distance between the fifth transistor and the one with the higher temperature.

6. The amplification device according to claim 4, characterized in that: The first group of transistor units includes m transistor units, and the second group of transistor units includes n transistor units, where m and n are positive integers, and m is substantially equal to n.

7. The amplification device according to claim 2, characterized in that: During an operation, the first transistor and the second transistor have the same temperature. In the chip, the distance between the fourth transistor and the first transistor is less than the distance between the fifth transistor and the first transistor, and the distance between the fourth transistor and the second transistor is less than the distance between the fifth transistor and the second transistor.

8. The amplification device according to claim 2, characterized in that: The voltage difference between the control terminal and the first terminal of the third transistor is substantially equal to the voltage difference between the control terminal and the first terminal of the first transistor; and The voltage difference between the second terminal and the first terminal of the third transistor is substantially equal to the voltage difference between the second terminal and the first terminal of the first transistor.

9. The amplification device according to claim 2, characterized in that: The third voltage is essentially equal to the fourth voltage; and The first voltage is essentially equal to the fourth voltage.

10. The amplification device according to claim 2, characterized in that: The first transistor and the third transistor have the same process difference parameters; and In the chip, the distance between the third transistor and the first transistor is less than the distance between the third transistor and the second transistor.

11. The amplification device according to claim 1, characterized in that: A load current flows through the amplifier circuit, and the load current is related to the first reference current.

12. The amplification device according to claim 11, characterized in that: The first transistor has a first size, the third transistor has a third size, and a ratio of the first size to the third size is substantially equal to a ratio of the load current to the first reference current.

13. The amplification device according to claim 2, characterized in that, Also includes: A sixth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the fourth node, the second terminal is used to receive the second reference current, and the control terminal is coupled to the second node.

14. The amplification device according to claim 13, characterized in that: The second transistor and the sixth transistor have the same process difference parameters; and In the chip, the distance between the sixth transistor and the second transistor is less than the distance between the sixth transistor and the first transistor.

15. The amplification device according to claim 13, characterized in that: The first transistor further includes a substrate, the third transistor further includes a substrate, and the connection state of the substrate of the first transistor is the same as the connection state of the substrate of the third transistor; and The second transistor further includes a substrate, and the sixth transistor further includes a substrate, wherein the connection state of the substrate of the second transistor is the same as the connection state of the substrate of the sixth transistor.

16. The amplification device according to claim 13, characterized in that, The amplifier circuit also includes: A first filter circuit is coupled between the signal input terminal and the output terminal of the operational amplifier; and A second filter circuit is coupled between the control terminal of the second transistor and the control terminal of the sixth transistor.

17. An amplification device, characterized in that, It includes: A signal input terminal is used to receive an input signal; One signal output terminal is used to output an amplified signal; An amplifier circuit is coupled between the signal input terminal and the signal output terminal. The amplifier circuit includes a first transistor and a second transistor stacked together, wherein a first node is coupled between the first transistor and the second transistor and the first node has a first voltage, and wherein the amplifier circuit is also coupled to a first reference voltage terminal. A third transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a second reference voltage terminal, the second terminal is coupled to a third node, wherein the third node is used to receive a first reference current, and the third node has a third voltage. A fourth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a third reference voltage terminal, the second terminal is coupled to a fourth node, wherein the fourth node is used to receive a second reference current, and the fourth node has a fourth voltage. A fifth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a fourth reference voltage terminal, the second terminal is coupled to the control terminal of the fifth transistor and also coupled to the control terminal of the fourth transistor, and the second terminal is used to receive a third reference current; and An operational amplifier includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the fourth node, the second input terminal is coupled to the third node, and the output terminal is coupled to the amplifier circuit and coupled to the control terminal of the third transistor. During one operation, the temperature difference between the fourth transistor and the amplifier circuit is less than the temperature difference between the fifth transistor and the amplifier circuit.

18. The amplification device according to claim 17, characterized in that: During the operation, the temperature of the amplifier circuit depends on the average of the temperatures of the first transistor and the second transistor.

19. The amplification device according to claim 17, characterized in that: The fourth transistor includes a first group of transistor units and a second group of transistor units, and the temperature of the fourth transistor depends on the average of the temperatures of the first group of transistor units and the second group of transistor units.

20. A current mirror circuit for adjusting a load current of an amplifier circuit, characterized in that, The current mirror circuit includes: A third transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a second reference voltage terminal, the second terminal is coupled to a third node, wherein the third node is used to receive a first reference current, and the third node has a third voltage. A fourth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a third reference voltage terminal, the second terminal is coupled to a fourth node, wherein the fourth node is used to receive a second reference current, and the fourth node has a fourth voltage. A fifth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a fourth reference voltage terminal, the second terminal is coupled to the control terminal of the fifth transistor and also coupled to the control terminal of the fourth transistor, and the second terminal is used to receive a third reference current; and An operational amplifier includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the fourth node, the second input terminal is coupled to the third node, and the output terminal is coupled to the amplifier circuit and coupled to the control terminal of the third transistor. In one chip, the distance between the fourth transistor and a transistor in the amplifier circuit is less than the distance between the fifth transistor and the transistor in the amplifier circuit.

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