Processing methods for components, chips, boards, devices, and processing components.

Abstract

This application discloses a processing component, a chip, a board, a device, and a processing method for the processing component, relating to the field of chips. The processing component includes: a storage queue consisting of a first-level storage queue and a second-level storage queue, and an output unit. The first-level storage queue includes n entries, and the second-level storage queue includes m entries, where n is less than m. The first-level storage queue is used to perform a read operation based on a query instruction, obtain a first operation result, and send the first operation result to the second-level storage queue and the output unit. The second-level storage queue is used to perform a read operation based on the query instruction and the first operation result, obtain a second operation result, and send the second operation result to the output unit. The output unit is used to return a forward result to the loading pipeline based on the first operation result and the second operation result, wherein the forward result includes first data corresponding to the first operation result or second data corresponding to the second operation result.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to a processing component, chip, board, device, and processing method of the processing component. Background Technology

[0002] The Load instruction loads data from memory into a register inside the processor, while the Store instruction stores data from a register inside the processor into memory.

[0003] In related technologies, store instructions and load instructions can have data dependencies, with the store address of the store instruction and the load address of the load instruction being the same. For example, a store instruction writes data from a register to a specified address in memory, and a load instruction reads data from that specified address in memory and writes it to another register. During this process, the data for the store instruction may exist in a store queue. The load instruction needs to query the store queue, and after finding a store instruction at the same address, it retrieves the data from the store queue.

[0004] However, the methods used in this technology result in significant latency when accessing the storage queue. Summary of the Invention

[0005] This application provides a processing component, a chip, a board, a device, and a method for processing the processing component. The technical solution is as follows:

[0006] On one hand, a processing component is provided, the processing component comprising: a storage queue consisting of a first-level storage queue and a second-level storage queue, and an output unit, wherein the first-level storage queue comprises n entries, the second-level storage queue comprises m entries, where n is less than m, and the entries correspond to storage instructions; the first-level storage queue is connected to the second-level storage queue, and the first-level storage queue and the second-level storage queue are also respectively connected to the output unit;

[0007] The first-level storage queue is used to perform a read operation based on a query instruction to obtain a first operation result. The query instruction is used to query the entry in the storage queue to obtain the data indicated by the query instruction. The first operation result is used to characterize the query situation in the first-level storage queue. The first operation result is sent to the second-level storage queue and the output unit.

[0008] The second-level storage queue is used to perform a read operation based on the query instruction and the first operation result to obtain a second operation result, which is used to characterize the query situation in the second-level storage queue; the second operation result is sent to the output unit.

[0009] The output unit is configured to return a forward result to the loading pipeline based on the first operation result and the second operation result. The forward result includes first data corresponding to the first operation result or second data corresponding to the second operation result. The first data is data indicated by the query instruction obtained from the first-level storage queue, and the second data is data indicated by the query instruction obtained from the second-level storage queue.

[0010] On the other hand, a processing method for a processing component is provided. The processing component includes: a storage queue consisting of a first-level storage queue and a second-level storage queue, and an output unit. The first-level storage queue includes n entries, and the second-level storage queue includes m entries, where n is less than m. The entries correspond to storage instructions. The first-level storage queue is connected to the second-level storage queue, and the first-level storage queue and the second-level storage queue are also respectively connected to the output unit.

[0011] The method includes:

[0012] The first-level storage queue performs a read operation based on a query instruction to obtain a first operation result. The query instruction is used to query the entry in the storage queue to obtain the data indicated by the query instruction. The first operation result is used to characterize the query situation in the first-level storage queue. The first operation result is sent to the second-level storage queue and the output unit.

[0013] The second-level storage queue performs a read operation based on the query instruction and the first operation result to obtain a second operation result, which is used to characterize the query status in the second-level storage queue; the second operation result is then sent to the output unit.

[0014] The output unit returns a forward result to the loading pipeline based on the first operation result and the second operation result. The forward result includes first data corresponding to the first operation result or second data corresponding to the second operation result. The first data is the data indicated by the query instruction obtained from the first-level storage queue, and the second data is the data indicated by the query instruction obtained from the second-level storage queue.

[0015] In some embodiments, the processing component further includes: a push-and-pop unit; the first-level storage queue is connected to the second-level storage queue through the push-and-pop unit, and the second-level storage queue is connected to the cache through the push-and-pop unit;

[0016] The method further includes:

[0017] When a storage instruction enters the first-level storage queue, the storage instruction is stored in one of the n entries. When the first-level storage queue is full, an entry that meets the relocation conditions is determined from the n entries. The storage instruction corresponding to the entry that meets the relocation conditions is sent to the second-level storage queue through the push-pop path of the push-pop unit.

[0018] The second-level storage queue stores the storage instructions corresponding to the entries that meet the relocation conditions; after the storage instruction corresponding to any one of the m entries is submitted, the submitted storage instruction is popped from the stack through the pop path of the push-pop unit, so as to move the submitted storage instruction to the cache.

[0019] In some embodiments, when the first-level storage queue is full, determining entries that meet the relocation conditions from the n entries includes:

[0020] If the first-level storage queue is full, the oldest entry among the n entries is determined as the entry that meets the relocation conditions.

[0021] In some embodiments, the tag table maintenance unit further includes: a counter value update unit; the second-level storage queue is connected to the counter value update unit through the push-pop unit;

[0022] The method further includes:

[0023] For storage instructions entering the second-level storage queue, the second-level storage queue calculates the second XOR tag of the storage instruction;

[0024] If the second XOR tag of the storage instruction exists in the tag table, the counter value update unit updates the counter value of the second XOR tag; otherwise, it stores the second XOR tag in the tag table and updates the counter value of the second XOR tag.

[0025] In some embodiments, the method further includes:

[0026] The counter value update unit updates the counter value of the second XOR tag of the submitted storage instruction after the submitted storage instruction is popped from the second-level storage queue.

[0027] In some embodiments, the output unit includes: a multiplexer and a logic OR circuit; the first-level storage queue and the second-level storage queue are respectively connected to the multiplexer, and the first-level storage queue and the second-level storage queue are respectively connected to the logic OR circuit; the forward result includes: forward data and forward valid signal;

[0028] The first-level storage queue sends the result of the first operation to the output unit; the second-level storage queue sends the result of the second operation to the output unit; the output unit, based on the first operation result and the second operation result, returns a forward result to the loading pipeline, including:

[0029] The first-level storage queue sends the first data corresponding to the first operation result to the multiplexer, and sends the first operation result to the logic OR circuit;

[0030] The second-level storage queue sends the second data corresponding to the second operation result to the multiplexer, and sends the second operation result to the logic OR circuit;

[0031] If the first operation result or the second operation result matches the data indicated by the query instruction, the logic or circuit will return the forward valid signal of the preset value to the loading pipeline.

[0032] The multiplexer selects the valid data from the first data corresponding to the first operation result and the second data corresponding to the second operation result as the forward data and returns it to the loading pipeline.

[0033] On the other hand, a chip is provided, the chip comprising: the processing component as described above.

[0034] On the other hand, a board is provided, the board including: the processing component as described above.

[0035] On the other hand, a computer device is provided, the computer device comprising: a processing component as described above, or a chip as described above, or a board as described above.

[0036] On the other hand, a computer device is provided, the computer device comprising: a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the processing method of the processing component as described above.

[0037] On the other hand, a computer-readable storage medium is provided that stores a computer program, which is loaded and executed by a processor to implement the processing method of the processing component as described above.

[0038] On the other hand, a computer program product is provided, the computer program product including computer instructions stored in a computer-readable storage medium, wherein a processor retrieves the computer instructions from the computer-readable storage medium, causing the processor to load and execute them to implement the processing method of the processing component as described above.

[0039] The beneficial effects of the technical solutions provided in this application include at least the following:

[0040] A single storage queue is divided into two levels: a first-level storage queue and a second-level storage queue. The first-level storage queue contains n entries, and the second-level storage queue contains m entries, where n is less than m, meaning the capacity of the first-level storage queue is less than that of the second-level storage queue. A query instruction first accesses the first-level storage queue, performing a read operation there. If the data indicated by the query instruction is found in the first-level storage queue, that data is output. Because the first-level storage queue has a smaller capacity, the access speed is faster, the access latency is lower, and unnecessary access to the second-level storage queue is avoided, resulting in lower power consumption. Only if the data indicated by the query instruction is not found in the first-level storage queue does the second-level storage queue become accessed, and the data indicated by the query instruction is output. This ensures that the data indicated by the query instruction can be retrieved from the second-level storage queue and also facilitates the execution of subsequent programs and instructions. Even if it is necessary to access the second-level storage queue after accessing the first-level storage queue, the first-level storage queue and the second-level storage queue can be started sequentially. Compared with the method in related technologies that requires starting an entire storage queue, the power consumption is still lower. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a structural block diagram of a computer system provided in an exemplary embodiment of this application;

[0043] Figure 2This is a schematic diagram of instructions provided in an exemplary embodiment of this application;

[0044] Figure 3 This is a schematic diagram of the related technology provided in an exemplary embodiment of this application;

[0045] Figure 4 This is a schematic block diagram of a processing component provided in an exemplary embodiment of this application;

[0046] Figure 5 This is a schematic block diagram of a processing component provided in an exemplary embodiment of this application;

[0047] Figure 6 This is a schematic block diagram of a processing component provided in an exemplary embodiment of this application;

[0048] Figure 7 This is a schematic block diagram of a processing component provided in an exemplary embodiment of this application;

[0049] Figure 8 This is a schematic block diagram of a processing component provided in an exemplary embodiment of this application;

[0050] Figure 9 This is a schematic block diagram of a processing component provided in an exemplary embodiment of this application;

[0051] Figure 10 This is a schematic diagram of the architecture of a processing component provided in an exemplary embodiment of this application;

[0052] Figure 11 This is a schematic diagram of a first-level storage queue hit scenario provided in an exemplary embodiment of this application;

[0053] Figure 12 This is a schematic diagram of a second-level storage queue hit scenario provided in an exemplary embodiment of this application;

[0054] Figure 13 This is a flowchart of a processing method of a processing component provided in an exemplary embodiment of this application;

[0055] Figure 14 This is a schematic block diagram of a chip provided in an exemplary embodiment of this application;

[0056] Figure 15 This is a schematic block diagram of a board provided in an exemplary embodiment of this application;

[0057] Figure 16 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application;

[0058] Figure 17 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application;

[0059] Figure 18 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application;

[0060] Figure 19 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application;

[0061] Figure 20 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0063] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0064] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0065] It should be understood that although the terms first, second, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0066] It should be noted that this application may display prompt interfaces, pop-ups, or output voice prompts before and during the collection of user, chip, and computer device data. These prompt interfaces, pop-ups, or voice prompts are used to inform the user that their data is being collected. This ensures that the application only begins the steps for collecting user data after receiving confirmation from the user regarding the prompt interface or pop-up; otherwise (i.e., without user confirmation), the steps for collecting user data end, meaning no user data is collected. In other words, all user data collected in this application is collected with the user's consent and authorization, and the collection, use, and processing of this user data must comply with the relevant laws, regulations, and standards of the relevant countries and regions.

[0067] First, let me briefly introduce the terms used in the embodiments of this application.

[0068] Chip: Also known as an artificial intelligence (AI) chip, it includes a processor and memory. The processor is used to process data.

[0069] Registers are used for temporary storage of data and / or instructions. Register types include at least one of the following: Data Register, Instruction Register, Status Register, and Program Counter.

[0070] Memory: also known as a storage system, is used to store data and / or programs.

[0071] Load instruction: can load data from memory into the processor's internal registers.

[0072] Store instruction: can store data from the processor's internal registers into memory.

[0073] Load Queue: Used to maintain data loading and ensure data loading and processing.

[0074] A store queue is used to maintain the order of load and store operations, ensuring data consistency during out-of-order execution. The store queue can reside within the processor. In some embodiments, store instructions and load instructions may have data dependencies, with the store address of the store instruction and the load address of the load instruction being the same. For example, a store instruction writes data from a register to a specified address in memory, and a load instruction reads data from that specified address in memory and writes it to another register. During this process, the data for the store instruction may exist in the store queue. The load instruction then needs to query the store queue, and after finding a store instruction at the same address, retrieves the data from the store queue.

[0075] In this embodiment, a single storage queue is divided into two levels: a first-level storage queue and a second-level storage queue. The first-level storage queue is also called the Lightweight Store Queue (LSQ). The second-level storage queue is also called the Main Store Queue (MSQ). The first-level storage queue contains n entries, and the second-level storage queue contains m entries, where n is less than m. This means that the capacity of the first-level storage queue is less than the capacity of the second-level storage queue, or that the first-level storage queue has a smaller capacity, and the second-level storage queue has a larger capacity. The most recently issued storage instructions are stored in the first-level storage queue. When the first-level storage queue is full, the storage instructions in the first-level storage queue are moved to the second-level storage queue; that is, the storage instructions corresponding to the entries in the second-level storage queue are moved from the first-level storage queue.

[0076] An entry is a basic unit for storing information. An entry stores a stored instruction and includes at least one of the following: the data, address, format, addressing mode, and execution conditions. In hardware implementation, each entry can correspond to a register, and the capacity, model, and specifications of the registers corresponding to each entry can be the same.

[0077] The tag table is a table used to indicate the storage instructions corresponding to entries in the second-level storage queue. Referring to the example in Table 1, the tag table consists of two columns: one column is the XOR tag (xor_tag), and the other column is the counter (counter, cnt) value of the XOR tag. Each row includes an XOR tag and a counter value.

[0078] Table 1: Tag Table

[0079] XOR tag Counter (cnt) xor(A) 1 … …

[0080] Optionally, the XOR tag in the tag table can also be called the second XOR tag. The second XOR tag is obtained based on the XOR operation and corresponds to the storage instruction indicated by the entry in the second-level storage queue. Specifically, the data at different bits of the storage address of the storage instruction is XORed to obtain the second XOR tag of the storage instruction. The counter value in the tag table represents the number of storage instructions. Taking Table 1 as an example, xor(A) is the XOR tag corresponding to the storage instruction with storage address A in the second-level storage queue, and a counter value of 1 indicates that the number of storage instructions is 1. The tag table is continuously updated based on the second-level storage queue. Setting this tag table for the second-level storage queue is used to quickly determine whether a hit has occurred, that is, by querying the tag table, it is determined whether the second-level storage queue needs to be accessed. When the query result of the tag table is a hit, the second-level storage queue is accessed; when the query result of the tag table is a miss, the access to the second-level storage queue can be skipped. In hardware implementation, the tag table can be implemented through registers, that is, the tag table is stored in registers.

[0081] Figure 1 This is a structural block diagram of a computer system provided in an exemplary embodiment of this application. The computer system 100 can be implemented as a hardware architecture that serves as a processing component, or as a system architecture that implements a processing method that serves as a processing component. The computer system 100 includes a terminal 120 and a server 140.

[0082] In some embodiments, terminal 120 includes the processing components of this embodiment, or terminal 120 includes a chip that includes the processing components of this embodiment. Terminal 120 may be an electronic device such as a mobile phone, tablet computer, vehicle terminal (vehicle system), wearable device, PC (Personal Computer), unmanned reservation terminal, etc., and this application embodiment does not limit it to this.

[0083] In some embodiments, server 140 includes the processing component of this embodiment, or server 140 includes a board that includes the processing component of this embodiment. Server 140 may be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud servers, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. Server 140 may be a backend server for terminal 120, used to provide backend services for the data operation and processing of terminal 120.

[0084] Cloud technology refers to a hosting technology that unifies hardware, software, and network resources within a wide area network (WAN) or local area network (LAN) to achieve data computing, storage, processing, and sharing. Based on the cloud computing business model, cloud technology encompasses network technology, information technology, integration technology, management platform technology, and application technology. It can form resource pools, providing flexible and convenient on-demand access. Cloud computing technology will become a crucial support. Backend services of technical network systems require substantial computing and storage resources, such as video websites, image websites, and many portal websites. With the rapid development and application of the internet industry, every item may have its own identification mark in the future, requiring transmission to backend systems for logical processing. Data at different levels will be processed separately, and various industry data will require robust system support, which can only be achieved through cloud computing.

[0085] Optionally, server 140 can also be implemented as a node in a blockchain system. Blockchain is a novel application model of computer technologies such as distributed data storage, peer-to-peer transmission, consensus mechanisms, and cryptographic algorithms. Essentially, a blockchain is a decentralized database, a chain of data blocks linked using cryptographic methods. Each data block contains information about a batch of network transactions, used to verify the validity of the information (anti-counterfeiting) and generate the next block. A blockchain can include a blockchain underlying platform, a platform product service layer, and an application service layer.

[0086] The terminal 120 and the server 140 can communicate via a network, such as a wired or wireless network. In the processing method of the processing component provided in this application embodiment, the executing entity for each step can be a processing component in a computer device, including the terminal 120 and / or the server 140.

[0087] Load instructions load data from memory into registers within the processor, while store instructions store data from registers into memory. In out-of-order processors, load and store instructions are issued and executed out of order to maximize program execution efficiency. To ensure correct program execution, load queues and store queues are introduced to maintain the order of load and store instructions.

[0088] To achieve higher performance, processors have a wide issue width, resulting in a large number of instructions running simultaneously in the pipeline. This necessitates deep load and store queues to accommodate more load and store instructions. However, as the depth increases, the access latency of the store queue also increases. For example, in scenarios where store and load instructions have data dependencies, the store address of the store instruction may be the same as the load address of the load instruction. As an example, see [reference needed]. Figure 2 A store instruction is represented as `store[a],x1`, and a load instruction as `load x2,[a]`. The store instruction writes the data in register x1 to memory address a, and the load instruction reads data from memory address a and writes it to register x2. In this case, the data for the store instruction may exist in the memory queue; the load instruction needs to query the memory queue and retrieve the data after finding a store instruction at the same address. Alternatively, the data for the store instruction may exist in the cache; in this case, the load instruction needs to retrieve the data from the cache. Due to the depth of the memory queue, querying the memory queue results in significant access latency and power consumption.

[0089] As an example, refer to Figure 3 The storage instruction enters the storage queue through storage instruction port 0 (store0). After the storage instruction is submitted, it is written to the cache from the storage queue through storage instruction port 1 (store1). Load instruction query (load_query) is the query port for the load instruction. In this embodiment, the query instruction corresponding to the load instruction is used to query the data of the load instruction. The query instruction is used to instruct the query to retrieve the data indicated by the query instruction. The data indicated by the query instruction is the data of the load instruction. When the data indicated by the query instruction is hit in the storage queue, that is, the data of the load instruction is hit in the storage queue, the valid forward read data is retrieved from the storage queue. Otherwise, the cache read data needs to be retrieved from the cache. Here, the storage queue is an integrated design, that is, the storage queue is a whole storage queue. Then: (1) When the load instruction accesses the storage queue, it needs to perform a comparison with each entry in the storage queue one by one, resulting in a large access delay of the storage queue. (2) When the load instruction accesses the storage queue, it needs to open a whole storage queue, resulting in a large power consumption.

[0090] Based on this, this application proposes a low-latency hierarchical storage queue design. (1) A hierarchical structure is adopted, dividing the storage queue into a first-level storage queue and a second-level storage queue. The first-level storage queue has a smaller capacity, lower access latency, and lower power consumption. When data is hit in the first-level storage queue, a lower access latency can be obtained. (2) The second-level storage queue has a larger capacity. A tag table is set for the second-level storage queue to quickly determine whether a hit has occurred. That is, by querying the tag table, it is determined whether the second-level storage queue needs to be accessed. When the query result of the tag table is a hit, the second-level storage queue is accessed. When the query result of the tag table is a miss, the access to the second-level storage queue can be skipped. This reduces unnecessary access to the second-level storage queue, thereby reducing power consumption. See below for detailed examples.

[0091] Figure 4 This is a schematic block diagram of a processing component 200 provided in an exemplary embodiment of this application.

[0092] The processing component 200 includes a storage queue consisting of a first-level storage queue 10 and a second-level storage queue 20, and an output unit 30. The first-level storage queue 10 is connected to the second-level storage queue 20, and the first-level storage queue 10 and the second-level storage queue 20 are also respectively connected to the output unit 30. Optionally, the connection can be a physical wiring connection or a communication connection. The specific connection method can be one or more combinations of series connection and parallel connection, which is not limited in this embodiment.

[0093] For example, the first-level storage queue 10 is also called a lightweight storage queue (LSQ). The second-level storage queue 20 is also called a main storage queue (MSQ). The first-level storage queue 10 includes n entries, and the second-level storage queue 20 includes m entries, where n is less than m. That is, the first-level storage queue 10 has a smaller capacity, and the second-level storage queue 20 has a larger capacity. An entry is a basic unit for storing information. An entry corresponds to a storage instruction; that is, an entry stores one storage instruction, including at least one of the following: data, address, format, addressing mode, and execution conditions. In hardware implementation, each entry can correspond to a register, and the capacity, model, and specifications of the registers corresponding to each entry can be the same. When the capacity, model, and specifications of the registers corresponding to each entry are the same, the physical performance of each entry is consistent. Because the capacity of the first-level storage queue 10 is smaller, the access latency of the first-level storage queue 10 is smaller. In this embodiment, the most recently issued storage instruction is stored in the first-level storage queue 10. When the first-level storage queue 10 is full, the storage instructions in the first-level storage queue 10 are moved to the second-level storage queue 20.

[0094] The first-level storage queue 10 is used to perform a read operation based on a query instruction to obtain a first operation result. The query instruction is used to query entries in the storage queue to obtain the data indicated by the query instruction. The first operation result is used to characterize the query situation in the first-level storage queue 10. The first operation result is sent to the second-level storage queue 20 and the output unit 30.

[0095] A load query (load_query) can also be called a load query command, a load query instruction, or a query instruction. A query instruction corresponds to a load instruction and is used to instruct the execution of a query operation on the storage queue to retrieve the data indicated by the query instruction. Since the query instruction corresponds to the load instruction, the data indicated by the query instruction is the same as the data indicated by the load instruction. In other words, the query instruction is used to query entries in the storage queue to retrieve the data indicated by the query instruction; the query instruction corresponds to the load instruction, and the data indicated by the query instruction is the same as the data indicated by the corresponding load instruction.

[0096] In some embodiments, load instructions and store instructions have a data dependency relationship, that is, the load address of the load instruction is the same as the store address of the store instruction. For example, a store instruction is represented as: store[a],x1; a load instruction is represented as: load x2,[a]. The store instruction writes the data in register x1 to memory address a, and the load instruction reads data from memory address a and writes it to register x2. When a store instruction with the same load address as the load instruction is found in the store queue, the data of that store instruction is retrieved from the store queue, which means the data of the load instruction can be obtained, i.e., the data indicated by the query instruction can be obtained.

[0097] The first-level storage queue 10 is used to perform a read operation based on a query instruction to obtain a first operation result; the first operation result is then sent to the second-level storage queue 20 and the output unit 30. The first operation result is obtained by performing a read operation on the first-level storage queue 10, and it is used to characterize the query situation in the first-level storage queue 10. The query situation can also be directly named the query result. Optionally, the query situation includes: the data indicated by the query instruction was found in the first-level storage queue 10, and the data indicated by the query instruction could not be found in the first-level storage queue 10.

[0098] In some embodiments, the first operation result is used to indicate whether the data indicated by the query instruction was hit or not hit in the first-level storage queue 10. The first operation result can specifically be indicated by a first result (lsq_hit), for example, by at least one of the values, states, or signals of the first result. The first operation result corresponds to first data (lsq_data), which is the data indicated by the query instruction retrieved from the first-level storage queue 10, i.e., the data of the load instruction.

[0099] Specifically, if the first operation results in a match with the data indicated by the query instruction, the read operation on the second-level storage queue 20 is skipped, and the output unit 30 returns the forward result to the load pipeline. The forward result includes the first data (lsq_data), which is the data indicated by the query instruction obtained from the first-level storage queue 10, i.e., the data of the load instruction. If the first operation results in a miss with the data indicated by the query instruction, the query on the second-level storage queue 20 continues.

[0100] Optionally, if the first result (lsq_hit) is a first value, a first state, or a first signal, it indicates a miss; if the first result (lsq_hit) is a second value, a second state, or a second signal, it indicates a hit. In one example, the first value includes 0, the first state includes a miss, the first signal includes a low level, the second value includes 1, the second state includes a hit, and the second signal includes a high level.

[0101] In some embodiments, a hit or miss is determined based on address. Taking the first-level storage queue 10 as an example, a hit occurs when the storage address of the storage instruction corresponding to one of the n entries in the first-level storage queue 10 is the same as the load address indicated by the query instruction. A miss occurs when the storage addresses of the storage instructions corresponding to all n entries in the first-level storage queue 10 are different from the load addresses indicated by the query instruction.

[0102] The second-level storage queue 20 is used to perform a read operation based on the query instruction and the first operation result to obtain a second operation result. The second operation result is used to characterize the query situation in the second-level storage queue 20. The second operation result is then sent to the output unit 30.

[0103] The second-level storage queue 20 is used to perform a read operation based on the query instruction and the result of the first operation to obtain a second operation result; the second operation result is then sent to the output unit 30. The second operation result is obtained by performing a read operation on the second-level storage queue 20, and it is used to characterize the query situation in the second-level storage queue 20. The query situation can also be directly named the query result. Optionally, the query situation includes: the data indicated by the query instruction was found in the second-level storage queue 20, and the data indicated by the query instruction could not be found in the second-level storage queue 20.

[0104] In some embodiments, the second operation result is used to indicate whether the data indicated by the query instruction was hit or not hit in the second-level storage queue 20. The second operation result can specifically be indicated by a second result (msq_hit), for example, by at least one of the following: a value, a status, or a signal. The second operation result corresponds to second data (msq_data), which is the data indicated by the query instruction retrieved from the second-level storage queue 20, i.e., the data of the load instruction.

[0105] Specifically, if the second operation results in a match with the data indicated by the query instruction, the output unit 30 returns a forward result to the load pipeline. The forward result includes the second data (msq_data), which is the data indicated by the query instruction retrieved from the second-level storage queue 20, i.e., the data of the load instruction. If the second operation results in a mismatch with the data indicated by the query instruction, a query cache is required.

[0106] Optionally, if the second result (msq_hit) is a first value, a first state, or a first signal, it indicates a miss; if the second result (msq_hit) is a second value, a second state, or a second signal, it indicates a hit. In one example, the first value includes 0, the first state includes a miss, the first signal includes a low level, the second value includes 1, the second state includes a hit, and the second signal includes a high level.

[0107] In some embodiments, the second-level storage queue 20 is used to perform a read operation based on a query instruction and the result of a first operation, and to obtain a second operation result if it is determined that the read operation conditions are met. The read operation conditions are the conditions under which the second-level storage queue 20 performs a read operation.

[0108] Optionally, the read operation condition can be: the data indicated by the query instruction is not found in the first-level storage queue 10, but the data indicated by the query instruction is found in the second-level storage queue 20. That is, the data indicated by the query instruction does not exist in the first-level storage queue 10, but exists in the second-level storage queue 20. Specific examples of read operation conditions will be described in detail in subsequent embodiments.

[0109] The output unit 30 is used to return a forward result to the loading pipeline based on the first operation result and the second operation result. The forward result includes first data corresponding to the first operation result or second data corresponding to the second operation result. The first data is data indicated by a query instruction obtained from the first-level storage queue 10, and the second data is data indicated by a query instruction obtained from the second-level storage queue 20.

[0110] Forward refers to the direction of data transmission from the data sender to the data receiver. In this embodiment, the data sender is the output unit 30, and the data receiver is the loading pipeline.

[0111] Output unit 30 is used to return a forward result to the load pipeline based on the first operation result and the second operation result. The forward result includes first data corresponding to the first operation result or second data corresponding to the second operation result. The first data is data indicated by a query instruction obtained from the first-level storage queue 10, and the second data is data indicated by a query instruction obtained from the second-level storage queue 20. Optionally, when the first operation result is a match for the data indicated by the query instruction, the forward result includes the first data; when the second operation result is a match for the data indicated by the query instruction, the forward result includes the second data.

[0112] In some embodiments, to maintain timing consistency and correct data transmission, it is necessary to tagged the valid signal and data. Tagged data is an operation of registers used to maintain timing correctness. Optionally, the forward result includes: a forward valid signal (forward_valid) and forward data (forward_data). The forward valid signal is used to indicate whether the forward data is valid data. The forward data is specific data, which in this embodiment is either first data or second data. The first data is data indicated by a query instruction obtained from the first-level storage queue 10, and the second data is data indicated by a query instruction obtained from the second-level storage queue 20.

[0113] In summary, the processing component 200 provided in this application includes: a storage queue composed of a first-level storage queue 10 and a second-level storage queue 20, and an output unit 30. The first-level storage queue 10 includes n entries, and the second-level storage queue 20 includes m entries, where n is less than m. Each entry corresponds to a storage instruction. The first-level storage queue 10 and the second-level storage queue 20 are connected, and both are also connected to the output unit 30. The first-level storage queue 10 is used to perform a read operation based on a query instruction to obtain a first operation result. The query instruction is used to query entries in the storage queue to obtain the data indicated by the query instruction. The first operation result is used to characterize the data in the first-level storage queue 10. The query status is processed; the first operation result is sent to the second-level storage queue 20 and the output unit 30; the second-level storage queue 20 is used to perform a read operation based on the query instruction and the first operation result to obtain a second operation result, which is used to characterize the query status in the second-level storage queue 20; the second operation result is sent to the output unit 30; the output unit 30 is used to return a forward result to the loading pipeline based on the first operation result and the second operation result, the forward result including the first data corresponding to the first operation result, or the second data corresponding to the second operation result, the first data being the data indicated by the query instruction obtained from the first-level storage queue 10, and the second data being the data indicated by the query instruction obtained from the second-level storage queue 20. Accordingly, a whole storage queue is divided into two levels: the first-level storage queue 10 and the second-level storage queue 20, wherein the first-level storage queue 10 includes n entries and the second-level storage queue 20 includes m entries, n is less than m, that is, the capacity of the first-level storage queue 10 is less than the capacity of the second-level storage queue 20. The query command first accesses the first-level storage queue 10. If the data indicated by the query command is found in the first-level storage queue 10, the data indicated by the query command is output. Because the first-level storage queue 10 has a smaller capacity, the access speed is faster, the access latency is lower, and unnecessary access to the second-level storage queue 20 is avoided, resulting in lower power consumption. Only when the data indicated by the query command is not found in the first-level storage queue 10 is the second-level storage queue 20 accessed, and the data indicated by the query command found in the second-level storage queue 20 is output. This ensures that the data indicated by the query command can be obtained from the second-level storage queue 20, which is beneficial for the execution of subsequent programs and instructions. Moreover, even if it is necessary to access the second-level storage queue 20 after accessing the first-level storage queue 10, the first-level storage queue 10 and the second-level storage queue 20 can be started sequentially. Compared to the method in related technologies that requires starting an entire storage queue, the power consumption is still lower.

[0114] Figure 5This is a schematic block diagram of a processing component 200 provided in an exemplary embodiment of this application.

[0115] In some embodiments, the processing component 200 further includes a tag table maintenance unit 40. The first-level storage queue 10 is connected to the tag table maintenance unit 40, and the tag table maintenance unit 40 is also connected to the second-level storage queue 20. Optionally, the connection can be via physical wiring or a communication connection. The specific connection method can be one or more combinations of series connection and parallel connection; this embodiment does not impose limitations.

[0116] The tag table maintenance unit 40 maintains a tag table (tag_table), which indicates the storage instructions corresponding to entries in the second-level storage queue 20. Referring to the example in Table 1, the tag table includes two columns: one column is the XOR tag (xor_tag), and the other column is the counter (counter, cnt) value of the XOR tag. Each row includes an XOR tag and a counter value. Optionally, the XOR tag in the tag table can also be called a second XOR tag. The second XOR tag is obtained based on the XOR operation and corresponds to the storage instructions indicated by the entries in the second-level storage queue 20. In this embodiment, the purpose of setting up the tag table and the tag table maintenance unit 40 is to quickly query whether a certain address is matched in the second-level storage queue 20.

[0117] The first-level storage queue 10 is used to send the result of the first operation to the tag table maintenance unit 40.

[0118] The first-level storage queue 10 is used to send the first operation result to the tag table maintenance unit 40. The first operation result is used to characterize the query status in the first-level storage queue 10, so that the tag table maintenance unit 40 knows whether the data indicated by the query instruction has been matched in the first-level storage queue 10.

[0119] The tag table maintenance unit 40 is used to query the tag table and obtain the query result; if the first operation result and the query result meet the read operation conditions, a read operation instruction is generated; the read operation instruction is sent to the second-level storage queue 20; the read operation instruction is used to indicate the initiation of a read operation, and the tag table is used to indicate the storage instructions corresponding to the entries in the second-level storage queue 20.

[0120] The read operation condition is the condition for performing a read operation on the second-level storage queue 20. In some embodiments, the read operation condition may be: the data indicated by the query instruction is not found in the first-level storage queue 10, but the data indicated by the query instruction is found in the second-level storage queue 20. The query result is obtained by querying the tag table, specifically by querying the second XOR tag in the tag table. The first operation result is used to indicate whether the row data indicated by the query instruction is found in the first-level storage queue 10, and the query result is used to indicate whether the data indicated by the query instruction is found in the second-level storage queue 20.

[0121] The tag table maintenance unit 40 queries the tag table (tag_table) to obtain query results (tag_table hit, tt_hit); if the first operation result and the query result satisfy the read operation conditions, a read operation instruction (msq_read_en) is generated; and the read operation instruction is sent to the second-level storage queue 20. The read operation instruction is used to indicate the initiation of a read operation, and the tag table is used to indicate the storage instructions corresponding to the entries in the second-level storage queue 20.

[0122] In some embodiments, the query result may be indicated by at least one of a numerical value, a status, or a signal. Optionally, when the query result is a first numerical value, a first status, or a first signal, it indicates that the data indicated by the query instruction was not found in the second-level storage queue 20; when the query result is a second numerical value, a second status, or a second signal, it indicates that the data indicated by the query instruction was found in the second-level storage queue 20. In one example, the first numerical value includes 0, the first status includes a miss, the first signal includes a low level, the second numerical value includes 1, the second status includes a hit, and the second signal includes a high level. The read operation indication may be indicated by at least one of a numerical value, information, instruction, level, signal, command, or request. For example, the read operation indication is a second numerical value, and the second numerical value includes 1.

[0123] The second-level storage queue 20 is used to perform read operations based on query instructions and read operation instructions to obtain the second operation result.

[0124] The second-level storage queue 20 is used to receive read operation instructions (msq_read_en), execute read operations based on the query instruction and the read operation instruction, and obtain the second operation result. Specifically, the read operation can be based on the load address indicated by the query instruction, determine the storage address that is the same as the load address, and read the data of the storage instruction in the entry corresponding to that storage address.

[0125] In this embodiment, by querying the tag table, it is possible to quickly determine whether further access to the second-level storage queue 20 is necessary. If the first operation result and the query result satisfy the read operation conditions, a corresponding read operation instruction is generated to continue accessing the second-level storage queue 20. This avoids unnecessary access to the second-level storage queue 20 and reduces power consumption.

[0126] In some embodiments, the first operation result is used to indicate whether the data indicated by the query instruction was hit or not hit in the first-level storage queue 10.

[0127] The tag table maintenance unit 40 is used to query the tag table and obtain the query result; if the first operation result is that the data indicated by the query instruction is not hit, and the query result is that the data indicated by the query instruction is hit, a read operation instruction is generated; and the read operation instruction is sent to the second-level storage queue 20.

[0128] In some embodiments, the read operation condition may be: the data indicated by the query instruction is not found in the first-level storage queue 10, but the data indicated by the query instruction is found in the second-level storage queue 20. For example, the first-level storage queue 10 is used to send the first operation result to the tag table maintenance unit 40. Since the first operation result can be indicated by a first result (lsq_hit), specifically, at least one of the value, status, or signal of the first result (lsq_hit) can be sent to the tag table maintenance unit 40 so that the tag table maintenance unit 40 knows whether the data indicated by the query instruction has been found in the first-level storage queue 10.

[0129] The tag table maintenance unit 40 is used to query the tag table (tag_table) and obtain the query result (tt_hit); if the first operation result is that the data indicated by the query instruction is not hit, and the query result is that the data indicated by the query instruction is hit, a read operation instruction (msq_read_en) is generated; the read operation instruction is sent to the second-level storage queue 20 to instruct the second-level storage queue 20 to continue to execute the read operation.

[0130] In this embodiment, by querying the tag table, it can be quickly determined whether a hit is needed in the second-level storage queue 20. If the first operation result is a miss and the query result is a hit, a corresponding read operation instruction is generated to continue accessing the second-level storage queue 20. This avoids unnecessary access to the second-level storage queue 20 and reduces power consumption.

[0131] Figure 6 This is a schematic block diagram of a processing component 200 provided in an exemplary embodiment of this application.

[0132] In some embodiments, the tag table maintenance unit 40 includes: an XOR fold unit 41, a tag compare (tag CMP) unit 42, and an AND circuit 43. The XOR fold unit 41 is connected to the tag compare unit 42, the tag compare unit 42 is connected to the AND circuit 43, the AND circuit 43 is connected to the second-level storage queue 20, and the first-level storage queue 10 is connected to the AND circuit 43. Optionally, the connection can be a physical wiring connection or a communication connection. The specific connection method can be one or more combinations of series connection and parallel connection, which is not limited in this embodiment.

[0133] The first-level storage queue 10 is used to send the result of the first operation to the logic AND circuit 43.

[0134] For example, the first-level storage queue 10 is used to send the first operation result to the logic AND circuit 43. Since the first operation result can be represented by the first result (lsq_hit), specifically, the first result (lsq_hit) can be sent to the logic AND circuit 43.

[0135] The XOR folding unit 41 is used to perform an XOR operation based on the query instruction to obtain the first XOR tag of the query instruction; and send the first XOR tag to the tag comparison unit 42.

[0136] The exclusive OR (XOR) operation is an operation performed based on the bitwise XOR principle. The logic of the XOR operation is: when two input values ​​are different, the output is 1; when two input values ​​are the same, the output is 0. In this embodiment, the purpose of the XOR operation is to determine the XOR tag (xor_tag), also known as the first XOR tag, of the load address indicated by the query instruction, which is obtained based on the XOR operation.

[0137] The XOR folding unit 41 is used to perform an XOR operation based on a query instruction. Specifically, it performs an XOR operation on the data in different bits of the load address indicated by the query instruction to obtain the first XOR tag of the query instruction; the first XOR tag is then sent to the tag comparison unit 42. The width of the first XOR tag is smaller than the width of the load address. Querying the tag table using the first XOR tag results in lower latency compared to querying directly by the load address.

[0138] The tag comparison unit 42 is used to query the first XOR tag in the tag table to obtain the query result; and send the query result to the logic AND circuit 43.

[0139] The tag comparison unit 42 is used to query the first XOR tag in the tag table to obtain the query result (tt_hit); and send the query result to the logic AND circuit 43. Specifically, the first XOR tag is queried row by row in the tag table. If a second XOR tag exists in the tag table that is the same as the first XOR tag, then the first XOR tag can be found in the tag table, and the query result is the data indicated by the query instruction. Otherwise, the query result is the data not indicated by the query instruction.

[0140] The logic and circuit 43 is used to generate a read operation instruction when the first operation result is a mismatch of the data indicated by the query instruction and the query result is a match of the data indicated by the query instruction; and to send the read operation instruction to the second-level storage queue 20.

[0141] For example, the logic AND circuit 43 is used to generate a read operation instruction when the first operation result is a mismatch of the data indicated by the query instruction and the query result is a match of the data indicated by the query instruction; and send the read operation instruction to the second-level storage queue 20.

[0142] It should also be noted that the characteristics of the AND circuit are: when both input values ​​are 1, the output is 1; when one of the two input values ​​is 0 or both input values ​​are 0, the output is 0. Since the first operation result is a data not specified by the query instruction, the first result (lsq_hit) used to represent this first operation result has a first value, which is 0. To ensure the logical correctness of the AND circuit 43, for the input terminal corresponding to the first operation result among the two input terminals of the AND circuit 43, before the first operation result is input into the AND circuit 43, an inversion operation is performed on the first operation result to obtain the inverted first operation result. The first result (lsq_hit) used to represent the inverted first operation result then has a second value, which is 1. Therefore, the AND circuit 43 can generate a read operation instruction when the first operation result is a data not specified by the query instruction, and the query result is a data specified by the query instruction.

[0143] In this embodiment, the first XOR tag of the query instruction can be calculated. The width of the first XOR tag is smaller than the width of the load address. Querying the tag table using the first XOR tag has lower latency compared to querying directly by the load address. It should also be noted that this embodiment uses an XOR operation to obtain the first and second XOR tags. In practical use, other operation methods can also be selected to obtain the corresponding tags, such as at least one of assignment, AND operation, OR operation, and NOT operation. The tag name can also be named according to other operation methods, and there are no restrictions here.

[0144] In some embodiments, the tag table stores the XOR tags (xor tags) of the storage addresses of storage instructions in the second-level storage queue 20, also referred to as the second XOR tags. The tag table also stores counter (cnt) values ​​for the second XOR tags, as shown in the example in Table 1. Specifically, the tag table includes the second XOR tags and their counter values, with each second XOR tag corresponding one-to-one with the storage instruction indicated by an entry in the second-level storage queue 20.

[0145] The tag comparison unit 42 is used to query the first XOR tag in the tag table. If there is a second XOR tag in the tag table that is the same as the first XOR tag, and the counter value of the second XOR tag is greater than the threshold, the query result is determined to be the data that matches the query instruction. Otherwise, the query result is determined to be the data that does not match the query instruction.

[0146] The query result indicating a match to the query instruction indicates that the probability of the data indicated by the query instruction existing in the second-level storage queue 20 is greater than a probability threshold, while the query result indicating a miss to the query instruction indicates that the data indicated by the query instruction does not exist in the second-level storage queue 20.

[0147] The first XOR tag is the XOR tag (xor_tag) of the load address corresponding to the query instruction. The second XOR tag is the XOR tag (xor_tag) of the storage address corresponding to the storage instruction in the second-level storage queue 20. For example, the tag comparison unit 42 queries the tag table for the first XOR tag. If a second XOR tag identical to the first XOR tag exists in the tag table, and the counter value of the second XOR tag is greater than a threshold, the query result is determined to be the data indicated by the query instruction; otherwise, the query result is determined to be the data not indicated by the query instruction. Optionally, the threshold can be set according to actual technical needs; in one example, the threshold is 0. When the counter value of the second XOR tag is greater than the threshold, it indicates that the storage instruction corresponding to the second XOR tag is still in the second-level storage queue 20.

[0148] In some embodiments, when the query result matches the data indicated by the query instruction, it indicates that the data indicated by the query instruction may exist in the second-level storage queue 20. That is, the probability that the query result matching the data indicated by the query instruction is used to indicate that the data indicated by the query instruction exists in the second-level storage queue 20 is greater than a probability threshold. When the query result does not match the data indicated by the query instruction, it indicates that the probability that the data indicated by the query instruction exists in the second-level storage queue 20 is less than a probability threshold. That is, the data indicated by the load instruction may not exist, or may not exist at all. That is, the query result does not match the data indicated by the query instruction in the second-level storage queue 20.

[0149] In this embodiment, the tag table stores the second XOR tag and its corresponding counter value. By querying the first XOR tag in the tag table, it is possible to quickly determine whether the same second XOR tag exists in the tag table, thereby accurately determining whether it is hit in the second-level storage queue 20, so as to avoid unnecessary access to the second-level storage queue 20 and reduce access latency.

[0150] The first-level storage queue 10 is used to compare the load address of the query instruction with the storage address of the storage instruction corresponding to each entry in the first-level storage queue 10; if there is no storage address with the same load address, the first operation result is determined to be the data not indicated by the query instruction; otherwise, the first operation result is determined to be the data indicated by the query instruction, and the first data corresponding to the first operation result is obtained.

[0151] A query instruction enters the first-level storage queue 10. The storage address of the storage instruction in each entry in the first-level storage queue 10 is compared with the load address of the query instruction to determine if a storage address with the same load address exists in the first-level storage queue 10. If the storage address of the storage instruction corresponding to an entry is the same as the load address, it is considered that the data indicated by the query instruction has been matched in the first-level storage queue 10; otherwise, it is considered that the data indicated by the query instruction has not been matched in the first-level storage queue 10.

[0152] For example, the first-level storage queue 10 is used to compare the load address of the query instruction with the storage address of the storage instruction corresponding to each entry in the first-level storage queue 10; if no storage address with the same load address exists, the first operation result is determined to be data that was not hit by the query instruction; otherwise, the first operation result is determined to be data that was hit by the query instruction, and the first data (lsq_data) corresponding to the first operation result is obtained. The first data is the data of the storage instruction stored in the entry corresponding to the storage address that is the same as the load address.

[0153] In this embodiment, the query instruction first enters the first-level storage queue 10 to access the first-level storage queue 10. Since the capacity of the first-level storage queue 10 is small, even if the storage addresses of the storage instructions corresponding to each entry in the first-level storage queue 10 are compared, the access latency is still smaller than that of the prior art.

[0154] Figure 7 This is a schematic block diagram of a processing component 200 provided in an exemplary embodiment of this application.

[0155] In some embodiments, the processing component 200 further includes a push-pop unit 50; the first-level storage queue 10 is connected to the second-level storage queue 20 through the push-pop unit 50, and the second-level storage queue 20 is connected to the cache through the push-pop unit 50. Optionally, the connection can be a physical wiring connection or a communication connection. The specific connection method can be one or more combinations of series connection and parallel connection, which is not limited in this embodiment.

[0156] Specifically, the stack push and pop unit 50 includes two data paths: a push path and a pop path. The push path moves the stored instructions corresponding to entries in the first-level storage queue 10 to the second-level storage queue 20. The pop path moves the stored instructions corresponding to entries in the second-level storage queue 20 to the cache.

[0157] The first-level storage queue 10 is used to store the storage instruction in one of n entries when the storage instruction enters the first-level storage queue 10; when the first-level storage queue 10 is full, the entry that meets the transfer conditions is determined from the n entries; and the storage instruction corresponding to the entry that meets the transfer conditions is sent to the second-level storage queue 20 through the push-pop path of the push-pop unit 50.

[0158] Optionally, the most recently issued storage instructions are stored in the first-level storage queue 10. When the first-level storage queue 10 is full, a portion of the storage instructions in the first-level storage queue 10 are moved to the second-level storage queue 20. That is, the storage instructions corresponding to the entries in the second-level storage queue 20 are moved from the first-level storage queue 10.

[0159] Specifically, the first-level storage queue 10 is used to store a storage instruction in one of n entries when the instruction enters it. The first-level storage queue 10 can store n storage instructions. When the first-level storage queue 10 is full, i.e., when the (n+1)th storage instruction enters it, the entry that meets the transfer conditions is determined from the n entries. The storage instruction corresponding to the entry that meets the transfer conditions is then sent to the second-level storage queue 20 through the push / pop path of the push / pop unit 50.

[0160] In some embodiments, the entries that meet the relocation conditions are determined based on timing. Specifically, the first-level storage queue 10 is used to determine the oldest entry (oldest_entry) among n entries as the entry that meets the relocation conditions when the first-level storage queue 10 is full. Here, the oldest entry can also be understood as the entry corresponding to the oldest storage instruction, or the entry corresponding to the earliest storage instruction to enter the first-level storage queue 10.

[0161] The second-level storage queue 20 is used to store the storage instructions corresponding to the entries that meet the relocation conditions. After the storage instruction corresponding to any one of the m entries is submitted, the submitted storage instruction is popped out through the pop path of the push-pop unit 50 to move the submitted storage instruction to the cache.

[0162] The second-level storage queue 20 stores the storage instructions corresponding to entries that meet the relocation conditions; that is, it stores the storage instructions relocated from the first-level storage queue 10. After a storage instruction corresponding to any one of the m entries is submitted, the submitted storage instruction is popped from the stack through the push / pop unit 50 to move it to the cache. When a storage instruction is a submitted storage instruction, it is marked as completed during the submission phase of the storage pipeline, and its data has been saved to the cache.

[0163] In this embodiment, when the first-level storage queue 10 is full, a portion of storage instructions can be moved to the second-level storage queue 20 so that the most recently issued storage instructions are stored in the first-level storage queue 10. This increases the probability that the data indicated by the query instruction will be hit in the first-level storage queue 10. If the data can be hit simply by accessing the first-level storage queue 10, the data of the load instruction that is hit in the first-level storage queue 10 will be directly output, thereby minimizing the access latency and avoiding further access to the second-level storage queue 20.

[0164] Figure 8 This is a schematic block diagram of a processing component 200 provided in an exemplary embodiment of this application.

[0165] In some embodiments, since the storage instructions in the second-level storage queue 20 need to be continuously updated, and the tag table (tag_table) is used to indicate the storage instructions corresponding to the entries in the second-level storage queue 20, and the tag table stores the second XOR tag and the counter value of the second XOR tag of the storage instructions in the second-level storage queue 20, the tag table also needs to be updated. Optionally, the tag table maintenance unit 40 further includes a counter value update unit 44. The second-level storage queue 20 is connected to the counter value update unit 44 through the push and pop unit 50.

[0166] The second-level storage queue 20 is used to calculate the second XOR tag of the storage instruction for the storage instruction entering the second-level storage queue 20.

[0167] The second XOR tag is the XOR tag (xor_tag) of the storage address corresponding to the storage instruction in the second-level storage queue 20. For each storage instruction entering the second-level storage queue 20, the second-level storage queue 20 calculates the second XOR tag of the storage instruction based on the storage address of the storage instruction.

[0168] For example, the second-level storage queue 20 is used to calculate a second XOR tag for a storage instruction entering the second-level storage queue 20. Specifically, an XOR operation is performed on the data in different bits of the storage address of the storage instruction to obtain the second XOR tag of the storage instruction.

[0169] The counter value update unit 44 is used to update the counter value of the second XOR tag if the second XOR tag containing the storage instruction exists in the tag table; otherwise, it stores the second XOR tag in the tag table and updates the counter value of the second XOR tag.

[0170] For example, the counter value update unit 44 is used to update the counter value of the second XOR tag if there is a second XOR tag with a storage instruction in the tag table, which may be to increment the counter value by 1; otherwise, to store the second XOR tag in the tag table, and to update the counter value of the second XOR tag, which may be to set the counter value to 1.

[0171] In some embodiments, the counter value update unit 44 is further configured to update the counter value of the second XOR tag of the submitted storage instruction after the submitted storage instruction is popped from the second-level storage queue 20. Specifically, the counter value of the second XOR tag of the submitted storage instruction is decremented by 1.

[0172] In this embodiment, the tag table can be updated according to the storage instructions in the second-level storage queue 20, which can improve the accuracy of querying the tag table, accurately determine whether it is hit in the second-level storage queue 20, and improve the accuracy of the query results.

[0173] Figure 9 This is a schematic block diagram of a processing component 200 provided in an exemplary embodiment of this application.

[0174] In some embodiments, the output unit 30 includes a multiplexer (mux) 32 and a logic OR circuit 31. The first-level storage queue 10 and the second-level storage queue 20 are respectively connected to the multiplexer 32, and the first-level storage queue 10 and the second-level storage queue 20 are respectively connected to the logic OR circuit 31. Optionally, the connection can be a physical wiring connection or a communication connection. The specific connection method can be one or more combinations of series connection and parallel connection; this embodiment does not impose limitations.

[0175] In some embodiments, the first operation result can be specifically indicated by a first result (lsq_hit), which corresponds to the first data (lsq_data), and the second operation result can be specifically indicated by a second result (msq_hit), which corresponds to the second data (msq_data). The forward result includes forward data (forward_data) and a forward valid signal (forward_valid).

[0176] The first-level storage queue 10 is used to send the first data corresponding to the first operation result to the multiplexer 32 and to send the first operation result to the logic OR circuit 31.

[0177] The first-level storage queue 10 is used to send the first data (lsq_data) corresponding to the first operation result to the multiplexer 32, and to send the first operation result to the logic OR circuit 31. Since the first operation result can be indicated by the first result (lsq_hit), specifically, at least one of the value, status or signal of the first result (lsq_hit) can be sent to the logic OR circuit 31 so that the logic OR circuit 31 can determine whether to output a forward valid signal of a preset value.

[0178] The second-level storage queue 20 is used to send the second data corresponding to the second operation result to the multiplexer 32 and to send the second operation result to the logic OR circuit 31.

[0179] The second-level storage queue 20 is used to send the second data (msq_data) corresponding to the second operation result to the multiplexer 32, and to send the second operation result to the logic OR circuit 31. Since the second operation result can be indicated by the second result (msq_hit), specifically, at least one of the value, status or signal of the second result (msq_hit) can be sent to the logic OR circuit 31 so that the logic OR circuit 31 can determine whether to output a forward valid signal of a preset value.

[0180] The logic OR circuit 31 is used to return a preset value forward valid signal to the loading pipeline when the first operation result or the second operation result is the data indicated by the query instruction.

[0181] The OR circuit 31 is characterized in that it outputs 1 when one of its two input values ​​is 1 or both input values ​​are 1. For example, the OR circuit 31 is used to return a forward valid signal (forward_valid) of a preset value to the load pipeline if the result of the first or second operation matches the data indicated by the query instruction. In one example, the preset value is 1. The forward valid signal of the preset value is used to indicate that the current forward data is valid.

[0182] Multiplexer 32 is used to select valid data from the first data corresponding to the first operation result and the second data corresponding to the second operation result as forward data and return it to the loading pipeline.

[0183] The multiplexer 32 has a specific data selection function, capable of selecting and outputting valid data. For example, the multiplexer 32 is used to select valid data from the first data (lsq_data) corresponding to the first operation result and the second data (msq_data) corresponding to the second operation result as forward data, which is returned to the load pipeline. In some embodiments, the selection method may be: the data is not empty, it matches the forward valid signal, the first data is selected when the first operation result matches the data indicated by the query instruction, and the second data is selected when the second operation result matches the data indicated by the query instruction.

[0184] In this embodiment, the forward valid signal and forward data can be determined based on the first operation result and the first data corresponding to the first operation result, as well as the second operation result and the second data corresponding to the second operation result. The forward data and forward valid signal can be returned to the loading pipeline, which can ensure the correctness and execution speed of the loading instruction and the storage instruction.

[0185] As an example, the processing component 200 provided in the embodiments of this application will be described in detail below with reference to the schematic diagram.

[0186] 1. Product Realization

[0187] In the fields of chips, processors, high-performance processors, and high-performance AI processors, load instructions and store instructions have a significant impact on the overall performance of the processor. The low-latency hierarchical storage queue design proposed in this application has low access latency and low power consumption, effectively improving the competitiveness of the product. It is suitable for scenarios of data parallel computing and high-performance computing, such as image data processing, scientific computing, machine learning, and game data processing.

[0188] 2. Technical Implementation

[0189] Figure 10This is a schematic diagram of the architecture of a processing component 200 provided in an exemplary embodiment of this application.

[0190] This embodiment divides a single storage queue into two levels: a first-level storage queue 10 and a second-level storage queue 20. The first-level storage queue 10 is also called a lightweight storage queue (LSQ), and the second-level storage queue 20 is also called a main storage queue (MSQ). The first-level storage queue 10 has n entries, and the second-level storage queue 20 has m entries, where n is less than m and can be a small number. The storage instructions corresponding to the entries in the second-level storage queue 20 are moved from the first-level storage queue 10.

[0191] The processing component 200 includes: a first-level storage queue 10, a second-level storage queue 20, a logic OR circuit 31, a multiplexer (mux) 32, an XOR fold unit 41, a tag comparison (tag cmp) unit 42, a logic AND circuit 43, a counter value update (cnt update) unit 44, and a stack push / pop unit 50.

[0192] Specifically, the first-level storage queue 10 is connected to the OR logic circuit 31, the AND logic circuit 43, and the multiplexer 32. The XOR folding unit 41 is connected to the tag comparison unit 42, the tag comparison unit 42 is connected to the AND logic circuit 43, and the AND logic circuit 43 is connected to the second-level storage queue 20. The first-level storage queue 10 is connected to the second-level storage queue 20 through the push path 51 of the push / pop unit 50. The second-level storage queue 20 is connected to the cache through the pop path 52 of the push / pop unit 50. The second-level storage queue 20 is connected to the counter value update unit 44 through the push / pop unit 50. The second-level storage queue 20 is connected to the OR logic circuit 31 and the multiplexer 32. Optionally, the connection can be through physical wiring or a communication connection. The specific connection method can be one or more combinations of series connection and parallel connection, which is not limited in this embodiment.

[0193] When a store instruction (store_instr) arrives, it first enters the first-level storage queue 10. When the first-level storage queue 10 is full, the store instruction corresponding to the oldest entry in the first-level storage queue 10 needs to be moved to the second-level storage queue 20. The store instruction corresponding to the oldest entry is written to the second-level storage queue 20 through the push path 51 in the push-pop unit 50. When a store instruction in the second-level storage queue 20 is committed, it is popped through the pop path 52 in the push-pop unit 50, and the data of the store instruction is moved to the cache.

[0194] The load command query (load_query) is the query port for the load command. In this embodiment, a query command corresponding to the load command is used to query the data of the load command. The query command is used to instruct the execution of a query operation on the storage queue to obtain the data indicated by the query command. The data indicated by the query command is the data of the load command. That is, the query command is used to query the entries in the storage queue to obtain the data indicated by the query command.

[0195] The query instruction enters the first-level storage queue 10 for comparison. It determines whether the load address indicated by the query instruction is the same as a valid storage address in the first-level storage queue 10. If an entry with the same address exists in the first-level storage queue 10, it is considered a hit, and the first result (lsq_hit) is output as 1. The corresponding hit data is output as the first data (lsq_data). The first result is sent to the AND circuit 43 and the OR circuit 31, and the first data is sent to the multiplexer 32. Simultaneously, the query instruction undergoes an XOR operation through the XOR fold unit 41. Specifically, it performs an XOR operation on the data in different bits of the load address indicated by the query instruction, obtaining an XOR tag (xor_tag), also called the first XOR tag. The width of the first XOR tag is smaller than the width of the load address. Searching the tag table using the first XOR tag results in lower latency compared to directly searching by the load address.

[0196] When a storage instruction (store_instr) is entered into the second-level storage queue 20, its XOR tag (xor_tag), also known as the second XOR tag, needs to be calculated based on the storage address. If this second XOR tag is the same as an XOR tag in the tag table, its corresponding counter (cnt) value is incremented by 1. If no XOR tag with the same value exists in the tag table, a new entry is allocated to this second XOR tag, and its counter value is set to 1. When a storage instruction leaves the second-level storage queue 20, its second XOR tag needs to be calculated based on the storage address, and the counter value of the corresponding second XOR tag in the tag table is decremented by 1. The counter value update operation can be completed by the counter value update (cnt update) unit 44.

[0197] A tag table is maintained to quickly determine whether a load address is in the second-level storage queue 20. If the queried load address matches the tag table, it means that the data at the queried load address may be in the second-level storage queue 20; otherwise, it is definitely not in the second-level storage queue 20. The tag table comparison unit 42 compares the first XOR tag of the load address of the query instruction with all the second XOR tags in the tag table. If there is a second XOR tag in the tag table that is the same as the first XOR tag, and its counter value is not 0, the output query result (tt_hit) is 1. If the first result (lsq_hit) is 0 and the query result (tt_hit) is 1, the read operation indication (msq_read_en) output by the logic AND circuit 43 is 1. This read operation indication is used to indicate the initiation of a read operation on the second-level storage queue 20; otherwise, no read operation is performed on the second-level storage queue 20. The logic AND circuit 43 sends the read operation instruction to the second-level storage queue 20. The second-level storage queue 20 then performs the read operation based on the read operation instruction (msq_read_en) and the query instruction, outputs the second result (msq_hit) to the logic OR circuit 31, and outputs the second data (msq_data) to the multiplexer 32.

[0198] The OR circuit 31 performs an OR operation on the first result (lsq_hit) and the second result (msq_hit). If either the first result (lsq_hit) or the second result (msq_hit) is a hit, it is considered that the data indicated by the query instruction has been found in the entire store queue, and the forward valid signal is returned as 1. The multiplexer 32 selects the valid data from the first data (lsq_data) and the second data (msq_data) as forward data and returns it to the load pipeline.

[0199] It should be noted that, Figure 10 The various units, devices, queues, connections, and circuits involved in the architecture diagram can all be implemented using corresponding components, connecting lines or circuits, logic circuits, and other types of hardware. It should also be noted that... Figure 10 The various units, devices, queues, connections, and circuits involved in the architecture diagram are merely examples and not limitations. They can be changed according to actual technical needs and hardware type, structure, size, etc. They can also include more or fewer units, devices, queues, connections, and circuits than shown in the diagram, or combine certain units, devices, queues, connections, and circuits, or adopt different arrangements.

[0200] Hit Scene 1: Figure 11 This is a schematic diagram illustrating a hit scenario in the first-level storage queue 10 according to an exemplary embodiment of this application. Assume a storage instruction is issued first, with storage address A, and the instruction remains stored in the first-level storage queue 10. The load instruction at address A is queried (A's load query), meaning the query instruction at address A first accesses the first-level storage queue 10. The first result (lsq_hit) is a hit, indicating a direct hit in the first-level storage queue 10. The first-level storage queue 10 outputs the first hit data. In this case, only the first-level storage queue 10 needs to be accessed, eliminating the need to access the second-level storage queue 20, thus reducing overall power consumption. Furthermore, the access latency to the first-level storage queue 10 is relatively low.

[0201] Hit Scene 2: Figure 12This is a schematic diagram of a hit scenario in the second-level storage queue 20 provided in an exemplary embodiment of this application. Assume a storage instruction is issued first, and the storage address of the storage instruction is A. Initially, the storage instruction is stored in the first-level storage queue 10. When the first-level storage queue 10 is full, the storage instruction is transferred to the second-level storage queue 20. The load instruction at address A is queried (A's load query). That is, the query instruction at address A first accesses the first-level storage queue 10. The first result (lsq_hit) is a miss. Simultaneously, the query result for the tag table (tag_table) is a hit. Therefore, the second-level storage queue 20 is accessed, and the second-level storage queue 20 outputs the second data that was hit.

[0202] In summary, the low-latency hierarchical storage queue design provided in this application divides a single storage queue into two levels: a first-level storage queue 10 and a second-level storage queue 20. Since the first-level storage queue 10 contains n entries and the second-level storage queue 20 contains m entries, where n is less than m, the capacity of the first-level storage queue 10 is smaller than the capacity of the second-level storage queue 20. A query instruction first accesses the first-level storage queue 10. If the data indicated by the query instruction is found in the first-level storage queue 10, the data indicated by the query instruction is output. Because the capacity of the first-level storage queue 10 is smaller, the access rate is faster, the access latency is lower, and unnecessary access to the second-level storage queue 20 is avoided, resulting in lower power consumption. Only when the data indicated by the query instruction is not found in the first-level storage queue 10 is the second-level storage queue 20 accessed, and the data indicated by the query instruction found in the second-level storage queue 20 is output. This ensures that the data indicated by the query instruction can be obtained from the second-level storage queue 20 and also facilitates the execution of subsequent programs and instructions.

[0203] Figure 13 This is a flowchart illustrating a processing method of a processing component provided in an exemplary embodiment of this application. The method is executed by the processing component, which may be located in a chip, board, or computer device. The processing component includes: a storage queue consisting of a first-level storage queue and a second-level storage queue; and an output unit. The first-level storage queue includes n entries, and the second-level storage queue includes m entries, where n is less than m. Each entry corresponds to a storage instruction. The first-level storage queue is connected to the second-level storage queue, and both the first-level and second-level storage queues are also connected to the output unit. Optionally, the connection can be via physical wiring or a communication connection. The specific connection method can be one or more combinations of series connection and parallel connection; this embodiment does not impose limitations on this.

[0204] The method includes at least some of the steps in steps 320, 340, and 360:

[0205] Step 320: The first-level storage queue performs a read operation based on the query instruction to obtain the first operation result. The query instruction is used to indicate the entry in the storage queue to obtain the data indicated by the query instruction. The first operation result is used to characterize the query situation in the first-level storage queue. The first operation result is sent to the second-level storage queue and the output unit.

[0206] Step 340: The second-level storage queue performs a read operation based on the query instruction and the first operation result to obtain the second operation result. The second operation result is used to characterize the query situation in the second-level storage queue; the second operation result is sent to the output unit.

[0207] Step 360: The output unit returns a forward result to the loading pipeline based on the first operation result and the second operation result. The forward result includes the first data corresponding to the first operation result or the second data corresponding to the second operation result. The first data is the data indicated by the query instruction obtained from the first-level storage queue, and the second data is the data indicated by the query instruction obtained from the second-level storage queue.

[0208] In summary, the processing method of the processing component provided in this application embodiment involves the following steps: a first-level storage queue performs a read operation based on a query instruction to obtain a first operation result. The query instruction is used to query entries in the storage queue to obtain data indicated by the query instruction. The first operation result is used to characterize the query situation in the first-level storage queue. The first operation result is then sent to a second-level storage queue and an output unit. The second-level storage queue performs a read operation based on the query instruction and the first operation result to obtain a second operation result. The second operation result is used to characterize the query situation in the second-level storage queue. The second operation result is then sent to the output unit. The output unit returns a forward result to the loading pipeline based on the first and second operation results. The forward result includes first data corresponding to the first operation result or second data corresponding to the second operation result. The first data is data indicated by the query instruction obtained from the first-level storage queue, and the second data is data indicated by the query instruction obtained from the second-level storage queue. Accordingly, the entire storage queue is divided into two levels: a first-level storage queue and a second-level storage queue. The first-level storage queue contains n entries, and the second-level storage queue contains m entries, where n is less than m, meaning the capacity of the first-level storage queue is less than that of the second-level storage queue. A query instruction first accesses the first-level storage queue, performing a read operation there. If the data indicated by the query instruction is found in the first-level storage queue, that data is output. Because the first-level storage queue has a smaller capacity, the access speed is faster, the access latency is lower, and unnecessary access to the second-level storage queue is avoided, resulting in lower power consumption. Only when the data indicated by the query instruction is not found in the first-level storage queue does the second-level storage queue proceed, outputting the data indicated by the query instruction found there. This ensures that the data indicated by the query instruction can be retrieved from the second-level storage queue and also facilitates the execution of subsequent programs and instructions. Even if it is necessary to access the second-level storage queue after accessing the first-level storage queue, the first-level storage queue and the second-level storage queue can be started sequentially. Compared with the method in related technologies that requires starting an entire storage queue, the power consumption is still lower.

[0209] In some embodiments, the processing component further includes: a tag table maintenance unit; a first-level storage queue is connected to the tag table maintenance unit, and the tag table maintenance unit is also connected to a second-level storage queue. Step 320: The first-level storage queue sends the first operation result to the second-level storage queue, which is implemented as step 322. Step 340: The second-level storage queue performs a read operation based on the query instruction and the first operation result to obtain the second operation result, which is implemented as steps 342 and 344.

[0210] Step 322: The first-level storage queue sends the result of the first operation to the tag table maintenance unit;

[0211] Step 342: The tag table maintenance unit queries the tag table to obtain the query result; if the first operation result and the query result meet the read operation conditions, a read operation instruction is generated; the read operation instruction is sent to the second-level storage queue; the read operation instruction is used to indicate the initiation of a read operation, and the tag table is used to indicate the storage instructions corresponding to the entries in the second-level storage queue.

[0212] Step 344: The second-level storage queue performs a read operation based on the query instruction and the read operation instruction to obtain the second operation result.

[0213] In some embodiments, the first operation result is used to indicate whether the data indicated by the query instruction was hit or not hit in the first-level storage queue. Step 342: The tag table maintenance unit queries the tag table to obtain the query result. If the first operation result and the query result meet the read operation conditions, a read operation instruction is generated and sent to the second-level storage queue, which is implemented as step 3420:

[0214] Step 3420: The tag table maintenance unit queries the tag table to obtain the query result; if the first operation result is that the data indicated by the query instruction is not matched, and the query result is that the data indicated by the query instruction is matched, a read operation instruction is generated; and the read operation instruction is sent to the second-level storage queue.

[0215] In some embodiments, the tag table maintenance unit includes: an XOR folding unit, a tag comparison unit, and a logic AND circuit; the XOR folding unit is connected to the tag comparison unit, the tag comparison unit is connected to the logic AND circuit, the logic AND circuit is connected to the second-level storage queue, and the first-level storage queue is connected to the logic AND circuit. Step 322: The first-level storage queue sends the first operation result to the tag table maintenance unit, which is implemented as step 3221; Step 3420: The tag table maintenance unit queries the tag table to obtain the query result. If the first operation result is a mismatch of the data indicated by the query instruction, and the query result is a match of the data indicated by the query instruction, a read operation instruction is generated, and the read operation instruction is sent to the second-level storage queue, which is implemented as steps 3421, 3422, and 3423.

[0216] Step 3221: The first-level storage queue sends the result of the first operation to the logic AND circuit;

[0217] Step 3421: The XOR folding unit performs an XOR operation based on the query instruction to obtain the first XOR tag of the query instruction; and sends the first XOR tag to the tag comparison unit.

[0218] Step 3422: The tag comparison unit queries the tag table for the first XOR tag and obtains the query result; the query result is then sent to the logic AND circuit.

[0219] Step 3423: If the result of the first operation is that the data indicated by the query instruction is not found, and the query result is that the data indicated by the query instruction is found, the logic AND circuit generates a read operation instruction and sends the read operation instruction to the second-level storage queue.

[0220] In some embodiments, the tag table includes a second XOR tag and a counter value for the second XOR tag, and the second XOR tag corresponds one-to-one with the storage instruction indicated by the entry in the second-level storage queue. Specifically, step 3422 is implemented as step 34220:

[0221] Step 34220: The tag comparison unit queries the tag table for the first XOR tag. If a second XOR tag identical to the first XOR tag exists in the tag table, and the counter value of the second XOR tag is greater than a threshold, the query result is determined to be data that matches the query instruction. Otherwise, the query result is determined to be data that does not match the query instruction. Here, a query result that matches the query instruction indicates that the probability of data that matches the query instruction in the second-level storage queue is greater than a probability threshold, and a query result that does not match the query instruction indicates that data that matches the query instruction does not exist in the second-level storage queue.

[0222] In some embodiments, step 320, where the first-level storage queue performs a read operation based on a query instruction to obtain the first operation result, is implemented as step 321:

[0223] Step 321: The first-level storage queue compares the load address of the query instruction with the storage address of the storage instruction corresponding to each entry in the first-level storage queue; if there is no storage address with the same load address, the first operation result is determined to be the data not indicated by the query instruction; otherwise, the first operation result is determined to be the data indicated by the query instruction, and the first data corresponding to the first operation result is obtained.

[0224] In some embodiments, the processing component further includes: a push-and-pop unit; the first-level storage queue is connected to the second-level storage queue via the push-and-pop unit, and the second-level storage queue is connected to the cache via the push-and-pop unit. Exemplarily, the method further includes steps 420 and 440:

[0225] Step 420: When a storage instruction enters the first-level storage queue, the storage instruction is stored in one of the n entries; when the first-level storage queue is full, the entry that meets the transfer conditions is determined from the n entries; the storage instruction corresponding to the entry that meets the transfer conditions is sent to the second-level storage queue through the push-pop unit's push path.

[0226] Step 440: The second-level storage queue stores the storage instructions corresponding to the entries that meet the relocation conditions; after the storage instruction corresponding to any one of the m entries is submitted, the submitted storage instruction is popped from the stack through the pop path of the push and pop unit to move the submitted storage instruction to the cache.

[0227] In some embodiments, step 420, when the first-level storage queue is full, determines the entries that meet the relocation conditions from the n entries, specifically implemented as step 422:

[0228] Step 422: If the first-level storage queue is full, the oldest entry among the n entries is determined as the entry that meets the relocation conditions.

[0229] In some embodiments, the tag table maintenance unit further includes: a counter value update unit; the second-level storage queue is connected to the counter value update unit via a push / pop unit. The method further includes steps 460 and 480:

[0230] Step 460: For storage instructions entering the second-level storage queue, calculate the second XOR tag of the storage instruction;

[0231] Step 480: If the second XOR tag containing the storage instruction exists in the tag table, the counter value update unit updates the counter value of the second XOR tag; otherwise, it stores the second XOR tag in the tag table and updates the counter value of the second XOR tag.

[0232] Optionally, concurrently with or after step 480, the method further includes step 482:

[0233] Step 482: After the submitted storage instruction is popped from the second-level storage queue, the counter value update unit updates the counter value of the second XOR tag of the submitted storage instruction.

[0234] In some embodiments, the output unit includes: a multiplexer and a logic OR circuit; a first-level storage queue and a second-level storage queue are respectively connected to the multiplexer, and the first-level storage queue and the second-level storage queue are respectively connected to the logic OR circuit. The forward result includes: forward data and a forward valid signal.

[0235] Step 320: The first-level storage queue sends the first operation result to the output unit, which is implemented as step 324; Step 340: The second-level storage queue sends the second operation result to the output unit, which is implemented as step 346; Step 360: Based on the first operation result and the second operation result, the output unit returns the forward result to the loading pipeline, which is implemented as steps 362 and 364.

[0236] Step 324: The first-level storage queue sends the first data corresponding to the first operation result to the multiplexer and sends the first operation result to the logic OR circuit.

[0237] Step 346: The second-level storage queue sends the second data corresponding to the second operation result to the multiplexer, and sends the second operation result to the logic OR circuit.

[0238] Step 362: If the result of the first operation or the result of the second operation is the data indicated by the query instruction, the logic OR circuit returns a forward valid signal of the preset value to the loading pipeline.

[0239] Step 364: The multiplexer selects the valid data from the first data corresponding to the first operation result and the second data corresponding to the second operation result as the forward data and returns it to the loading pipeline.

[0240] It should be noted that the embodiments and beneficial effects of the processing method of the processing component provided in this application can be referred to the foregoing description of the embodiments and beneficial effects of the processing component, and will not be repeated here.

[0241] It should also be noted that steps 322, 342, and 344 are all optional steps, and steps 322, 342, 344, and 360 can also be implemented in combination; step 3420 is an optional step, and steps 3420, 344, and 360 can also be implemented in combination; steps 3221, 3421, 3422, and 3423 are all optional steps, and steps 3221, 3421, 3422, 3423, 344, and 360 can also be implemented in combination; step 34220 is an optional step, and steps 3221, 3421, 34220, 3423, 344, and 360 can also be implemented in combination; Steps 0 can also be implemented in combination; step 321 is optional, and steps 321, 340, and 360 can also be implemented in combination; steps 420, 440, 460, 480, and 482 are all optional, and step 440 can be implemented in combination with steps 460 and 480, simultaneously, or sequentially; steps 420, 440, 480, and 482 can be implemented in combination with steps 320, 340, and 360, simultaneously, or sequentially; steps 324, 346, 362, and 364 are all optional, and steps 324, 346, 362, and 364 can also be implemented in combination. The specific execution order and steps can be adjusted according to actual technical needs and actual hardware design.

[0242] This application provides a chip. Figure 14This is a schematic block diagram of a chip provided in an exemplary embodiment of this application. Chip 500 includes the processing component 200 provided in the above embodiment. Alternatively, an embodiment of this application provides a chip including programmable logic circuits and / or program instructions, which, when run on a computer device, are used to implement the processing method of the processing component provided in the above method embodiment.

[0243] As an example, taking chip 500 as an example of image data processing, the load query is implemented using a query instruction. The data indicated by the query instruction is the data of the load instruction, i.e., the data to be loaded. Since the load instruction data is image data, the forward data to be output by processing component 200 is also image data. There is a data dependency between the load instruction and the store instruction; the image data to be loaded by the load instruction may exist in the store query queue. For processing component 200 in chip 500, based on the query instruction, it first accesses the first-level store queue. If a match is found in the first-level store queue, it outputs the data indicated by the query instruction that was found in the first-level store queue. If no match is found in the first-level store queue but a match is found in the tag table, it continues to access the second-level store queue and outputs the data indicated by the query instruction that was found in the second-level store queue to read the required image data.

[0244] This application provides a circuit board. Figure 15 This is a schematic block diagram of a board provided in an exemplary embodiment of this application. The board 600 includes the processing component 200 provided in the above embodiment. Alternatively, an embodiment of this application provides a board that, when running on a computer device, is used to implement the processing method of the processing component provided in the above method embodiment.

[0245] Specifically, a board, also known as a server board, is a type of printed circuit board (PCB). During manufacturing, it includes a connector that inserts into a slot on a server's motherboard to control hardware operations, such as monitors and data acquisition cards. After installing a driver or computer program on the board, it can perform its corresponding functions. This driver or computer program can be installed in the processor, which controls its execution and, in conjunction with the processing component 200, implements the corresponding functions of the board 600.

[0246] This application provides a computer device. Figure 16This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device 700 includes the processing component 200 provided in the above embodiment. Alternatively, an embodiment of this application provides a computer device. Figure 17 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device 800 includes the chip 500 provided in the above embodiment, and the computer device 800 may optionally be implemented as a terminal. Alternatively, an embodiment of this application provides a computer device. Figure 18 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device 900 includes the board 600 provided in the above embodiment, and the computer device 900 may be implemented as a server.

[0247] Optionally, embodiments of this application also provide a computer device, which includes: a processor and a memory, wherein the memory stores a computer program; the processor is used to execute the computer program in the memory to implement the processing method of the processing components provided in the above-described method embodiments.

[0248] Figure 19 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device is a server 1000. Typically, the server 1000 includes a processor 1001 and a memory 1002.

[0249] Processor 1001 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 1001 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). Processor 1001 may also include a main processor and a coprocessor. The main processor, also known as a central processing unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1001 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 1001 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0250] The memory 1002 may include one or more computer-readable storage media, which may be non-transitory. The memory 1002 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1002 are used to store at least one instruction, which is executed by the processor 1001 to implement the processing method of the processing component provided in the method embodiments of this application.

[0251] In some embodiments, the server 1000 may optionally include an input interface 1003 and an output interface 1004. The processor 1001, memory 1002, and input interfaces 1003 and 1004 can be connected via a bus or signal lines. Various peripheral devices can be connected to the input interfaces 1003 and 1004 via a bus, signal lines, or a circuit board. The input interfaces 1003 and 1004 can be used to connect at least one input / output (I / O) related peripheral device to the processor 1001 and memory 1002. In some embodiments, the processor 1001, memory 1002, and input interfaces 1003 and 1004 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 1001, memory 1002, and input interfaces 1003 and 1004 can be implemented on separate chips or circuit boards, and this application does not limit this.

[0252] Figure 20 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. Optionally, the computer device 2000 is a terminal.

[0253] The computer device 2000 can be a portable mobile terminal, also referred to as a mobile terminal in this embodiment. Examples include smartphones, tablets, MP3 players (Moving Picture Experts Group Audio Layer III), and MP4 players (Moving Picture Experts Group Audio Layer IV). The computer device 2000 may also be referred to as user equipment, portable terminal, or other names.

[0254] Typically, a computer device 2000 includes a processor 2001 and a memory 2002.

[0255] Processor 2001 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 2001 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 2001 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 2001 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, processor 2001 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0256] The memory 2002 may include one or more computer-readable storage media, which may be tangible and non-transitory. The memory 2002 may also include high-speed random access memory devices and non-volatile storage devices, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 2002 are used to store at least one instruction, which is executed by the processor 2001 to implement the processing methods of the processing components provided in the various method embodiments of this application.

[0257] In some embodiments, the computer device 2000 may optionally include a peripheral device interface 2003 and at least one peripheral device. Specifically, the peripheral device includes at least one of a radio frequency circuit 2004, a touch display screen 2005, a camera assembly 2006, an audio circuit 2007, and a power supply 2008. The computer device 2000 also includes one or more sensors 2009. The one or more sensors 2009 include, but are not limited to, an accelerometer 2010, a gyroscope 2011, a pressure sensor 2012, an optical sensor 2013, and a proximity sensor 2014.

[0258] Those skilled in the art will understand that Figure 14 The structure shown does not constitute a limitation on the chip. Figure 15 The structure shown does not constitute a limitation on the board. Figure 16 , Figure 17 , Figure 18 , Figure 19 and Figure 20 The structure shown does not constitute a limitation on the computer device and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0259] This application provides a computer-readable storage medium storing a computer program, which is loaded and executed by a processor to implement the processing methods of the processing components provided in the above-described method embodiments.

[0260] This application provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. The processor of a computer device reads the computer instructions from the computer-readable storage medium, executes the computer instructions, and causes the processor of the computer device to load and execute the processing method of the processing component provided in the above-described method embodiments.

[0261] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0262] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0263] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0264] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A processing component, characterized in that, The processing component includes: a storage queue consisting of a first-level storage queue and a second-level storage queue, and an output unit. The first-level storage queue includes n entries, and the second-level storage queue includes m entries, where n is less than m. The entries correspond to storage instructions. The first-level storage queue is connected to the second-level storage queue, and the first-level storage queue and the second-level storage queue are also respectively connected to the output unit. The first-level storage queue is used to perform a read operation based on a query instruction to obtain a first operation result. The query instruction is used to query the entry in the storage queue to obtain the data indicated by the query instruction. The first operation result is used to characterize the query situation in the first-level storage queue. The first operation result is sent to the second-level storage queue and the output unit. The second-level storage queue is used to perform a read operation based on the query instruction and the first operation result to obtain a second operation result, which is used to characterize the query situation in the second-level storage queue; the second operation result is sent to the output unit. The output unit is configured to return a forward result to the loading pipeline based on the first operation result and the second operation result. The forward result includes first data corresponding to the first operation result or second data corresponding to the second operation result. The first data is data indicated by the query instruction obtained from the first-level storage queue, and the second data is data indicated by the query instruction obtained from the second-level storage queue.

2. The processing component according to claim 1, characterized in that, The processing component further includes: a tag table maintenance unit; the first-level storage queue is connected to the tag table maintenance unit, and the tag table maintenance unit is also connected to the second-level storage queue; The first-level storage queue is used to send the result of the first operation to the tag table maintenance unit; The tag table maintenance unit is used to query the tag table and obtain the query result; if the first operation result and the query result satisfy the read operation condition, a read operation instruction is generated; the read operation instruction is sent to the second-level storage queue; the read operation instruction is used to indicate the initiation of a read operation, and the tag table is used to indicate the storage instruction corresponding to the entry in the second-level storage queue; The second-level storage queue is used to perform a read operation based on the query instruction and the read operation instruction to obtain the second operation result.

3. The processing component according to claim 2, characterized in that, The first operation result is used to indicate whether the data indicated by the query instruction was hit or not hit in the first-level storage queue; The tag table maintenance unit is used to query the tag table to obtain the query result; if the first operation result is that the data indicated by the query instruction is not matched, and the query result is that the data indicated by the query instruction is matched, the unit generates the read operation instruction; and sends the read operation instruction to the second-level storage queue.

4. The processing component according to claim 3, characterized in that, The tag table maintenance unit includes: an XOR folding unit, a tag comparison unit, and a logic AND circuit; the XOR folding unit is connected to the tag comparison unit, the tag comparison unit is connected to the logic AND circuit, the logic AND circuit is connected to the second-level storage queue, and the first-level storage queue is connected to the logic AND circuit. The first-level storage queue is used to send the result of the first operation to the logic and circuit; The XOR folding unit is used to perform an XOR operation based on the query instruction to obtain a first XOR tag of the query instruction; and send the first XOR tag to the tag comparison unit. The tag comparison unit is used to query the first XOR tag in the tag table to obtain the query result; and send the query result to the logic AND circuit. The logic and circuitry are configured to generate the read operation instruction when the first operation result is that the data indicated by the query instruction is not matched, and the query result is that the data indicated by the query instruction is matched; and send the read operation instruction to the second-level storage queue.

5. The processing component according to claim 4, characterized in that, The tag table includes a second XOR tag and a counter value for the second XOR tag, and the second XOR tag corresponds one-to-one with the storage instruction indicated by the entry in the second-level storage queue; The tag comparison unit is used to query the tag table for the first XOR tag. If a second XOR tag identical to the first XOR tag exists in the tag table and the counter value of the second XOR tag is greater than a threshold, the query result is determined to be the data that matches the query instruction. Otherwise, the query result is determined to be the data that does not match the query instruction. Wherein, the query result being a match to the data indicated by the query instruction indicates that the probability of the data indicated by the query instruction existing in the second-level storage queue is greater than a probability threshold, and the query result being a miss to the data indicated by the query instruction indicates that the data indicated by the query instruction does not exist in the second-level storage queue.

6. The processing component according to any one of claims 1 to 5, characterized in that, The first-level storage queue is used to compare the load address of the query instruction with the storage address of the storage instruction corresponding to each entry in the first-level storage queue; if there is no storage address that is the same as the load address, the first operation result is determined to be that the data indicated by the query instruction is not matched; otherwise, the first operation result is determined to be that the data indicated by the query instruction is matched, and the first data corresponding to the first operation result is obtained.

7. The processing component according to any one of claims 1 to 5, characterized in that, The processing component further includes: a push-pop unit; the first-level storage queue is connected to the second-level storage queue through the push-pop unit, and the second-level storage queue is connected to the cache through the push-pop unit; The first-level storage queue is used to store the storage instruction in one of the n entries when the storage instruction enters the first-level storage queue; when the first-level storage queue is full, to determine the entry that meets the transfer conditions from the n entries; and to send the storage instruction corresponding to the entry that meets the transfer conditions to the second-level storage queue through the push path of the push and pop unit. The second-level storage queue is used to store the storage instructions corresponding to the entries that meet the relocation conditions; after the storage instruction corresponding to any one of the m entries is submitted, the submitted storage instruction is popped out through the pop path of the push and pop unit to move the submitted storage instruction to the cache.

8. The processing component according to claim 7, characterized in that, The first-level storage queue is used to determine the oldest entry among the n entries as the entry that meets the relocation conditions when the first-level storage queue is full.

9. The processing component according to claim 7, characterized in that, The tag table maintenance unit further includes: a counter value update unit; the second-level storage queue is connected to the counter value update unit through the push-pop unit; The second-level storage queue is used to calculate the second XOR tag of the storage instruction for the storage instruction entering the second-level storage queue; The counter value update unit is used to update the counter value of the second XOR tag if the second XOR tag of the storage instruction exists in the tag table; otherwise, it stores the second XOR tag in the tag table and updates the counter value of the second XOR tag.

10. The processing component according to claim 9, characterized in that, The counter value update unit is further configured to update the counter value of the second XOR tag of the submitted storage instruction after the submitted storage instruction is popped from the second-level storage queue.

11. The processing component according to any one of claims 1 to 10, characterized in that, The output unit includes: a multiplexer and a logic OR circuit; the first-level storage queue and the second-level storage queue are respectively connected to the multiplexer, and the first-level storage queue and the second-level storage queue are respectively connected to the logic OR circuit; the forward result includes: forward data and forward valid signal; The first-level storage queue is used to send the first data corresponding to the first operation result to the multiplexer and to send the first operation result to the logic OR circuit. The second-level storage queue is used to send the second data corresponding to the second operation result to the multiplexer and to send the second operation result to the logic OR circuit; The logic or circuit is configured to return the forward valid signal of a preset value to the loading pipeline when the first operation result or the second operation result is a match with the data indicated by the query instruction. The multiplexer is used to select valid data from the first data corresponding to the first operation result and the second data corresponding to the second operation result as the forward data and return it to the loading pipeline.

12. A chip, characterized in that, The chip includes: a processing component as described in any one of claims 1 to 11.

13. A circuit board, characterized in that, The board includes: a processing component as described in any one of claims 1 to 11.

14. A computer device, characterized in that, The computer device includes: a processing component as described in any one of claims 1 to 11, or a chip as described in claim 12, or a board as described in claim 13.

15. A processing method for a processing component, characterized in that, The processing component includes: a storage queue consisting of a first-level storage queue and a second-level storage queue, and an output unit. The first-level storage queue includes n entries, and the second-level storage queue includes m entries, where n is less than m. The entries correspond to storage instructions. The first-level storage queue is connected to the second-level storage queue, and the first-level storage queue and the second-level storage queue are also respectively connected to the output unit. The method includes: The first-level storage queue performs a read operation based on a query instruction to obtain a first operation result; the first operation result is sent to the second-level storage queue and the output unit; the query instruction is used to query the entries in the storage queue to obtain the data indicated by the query instruction, and the first operation result is used to characterize the query situation in the first-level storage queue. The second-level storage queue performs a read operation based on the query instruction and the first operation result to obtain a second operation result, which is used to characterize the query status in the second-level storage queue; the second operation result is then sent to the output unit. The output unit returns a forward result to the loading pipeline based on the first operation result and the second operation result. The forward result includes first data corresponding to the first operation result or second data corresponding to the second operation result. The first data is the data indicated by the query instruction obtained from the first-level storage queue, and the second data is the data indicated by the query instruction obtained from the second-level storage queue.

16. The method according to claim 15, characterized in that, The processing component further includes: a tag table maintenance unit; the first-level storage queue is connected to the tag table maintenance unit, and the tag table maintenance unit is also connected to the second-level storage queue; The first-level storage queue sends the result of the first operation to the second-level storage queue. The second-level storage queue performs a read operation based on the query instruction and the result of the first operation to obtain the result of the second operation, including: The first-level storage queue sends the result of the first operation to the tag table maintenance unit; The tag table maintenance unit queries the tag table to obtain the query result; if the first operation result and the query result satisfy the read operation condition, a read operation instruction is generated; the read operation instruction is sent to the second-level storage queue; the read operation instruction is used to indicate the initiation of a read operation, and the tag table is used to indicate the storage instruction corresponding to the entry in the second-level storage queue; The second-level storage queue performs a read operation based on the query instruction and the read operation instruction to obtain the second operation result.

17. The method according to claim 16, characterized in that, The first operation result is used to indicate whether the data indicated by the query instruction was hit or not hit in the first-level storage queue; The tag table maintenance unit queries the tag table to obtain the query results; If the result of the first operation and the query result satisfy the read operation conditions, a read operation instruction is generated; Sending the read operation instruction to the second-level storage queue includes: The tag table maintenance unit queries the tag table to obtain the query result; If the result of the first operation is that the data indicated by the query instruction is not found, and the result of the query is that the data indicated by the query instruction is found, the read operation instruction is generated; and the read operation instruction is sent to the second-level storage queue.

18. The method according to claim 17, characterized in that, The tag table maintenance unit includes: an XOR folding unit, a tag comparison unit, and a logic AND circuit; the XOR folding unit is connected to the tag comparison unit, the tag comparison unit is connected to the logic AND circuit, the logic AND circuit is connected to the second-level storage queue, and the first-level storage queue is connected to the logic AND circuit. The first-level storage queue sends the first operation result to the tag table maintenance unit; the tag table maintenance unit queries the tag table to obtain the query result; if the first operation result does not match the data indicated by the query instruction, and the query result matches the data indicated by the query instruction, the read operation instruction is generated; the read operation instruction is sent to the second-level storage queue, including: The first-level storage queue sends the result of the first operation to the logic AND circuit; The XOR folding unit performs an XOR operation based on the query instruction to obtain a first XOR tag of the query instruction; the first XOR tag is then sent to the tag comparison unit. The tag comparison unit queries the first XOR tag in the tag table to obtain the query result; and sends the query result to the logic AND circuit. When the first operation result is that the data indicated by the query instruction is not found, and the query result is that the data indicated by the query instruction is found, the logic and circuit generate the read operation instruction and send the read operation instruction to the second-level storage queue.

19. The method according to claim 18, characterized in that, The tag table includes a second XOR tag and a counter value for the second XOR tag, and the second XOR tag corresponds one-to-one with the storage instruction indicated by the entry in the second-level storage queue; The tag comparison unit queries the tag table for the first XOR tag to obtain the query result, including: The tag comparison unit queries the tag table for the first XOR tag. If a second XOR tag identical to the first XOR tag exists in the tag table and the counter value of the second XOR tag is greater than a threshold, the query result is determined to be the data that matches the query instruction. Otherwise, the query result is determined to be the data that does not match the query instruction. Wherein, the query result is a match for the data indicated by the query instruction, indicating that the probability of the data indicated by the query instruction existing in the second-level storage queue is greater than a probability threshold, and the query result is a miss for the data indicated by the query instruction, indicating that the data indicated by the query instruction does not exist in the second-level storage queue.

20. The method according to any one of claims 15 to 19, characterized in that, The first-level storage queue performs a read operation based on a query instruction, obtaining the first operation result, including: The first-level storage queue compares the load address of the query instruction with the storage address of the storage instruction corresponding to each entry in the first-level storage queue; if there is no storage address that is the same as the load address, the first operation result is determined to be that the data indicated by the query instruction was not matched; otherwise, the first operation result is determined to be that the data indicated by the query instruction was matched, and the first data corresponding to the first operation result is obtained.

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