A kind of in-memory computing unit and array

Abstract

The present invention discloses a memory - in - computing unit and an array, belonging to the technical field of integrated circuit design. The memory - in - computing unit includes: an SRAM six - transistor (6T) memory cell for storing data; and a computing unit composed of two NMOS transistors for performing calculations. The number of SRAM six - transistor memory cells is 8, and each SRAM six - transistor memory cell and 8 of the computing units form a column of the memory - in - computing array. One memory - in - computing unit provided by the present invention contains 8 transistors, one column of the memory - in - computing array contains 22 transistors, and eight columns of the memory - in - computing array have a total of 176 transistors. Compared with the existing solutions for achieving the same function, the present invention has fewer transistors, can save chip area, and can play a role in improving performance and saving costs. The memory - in - computing array provided by the present invention can implement the matrix multiplication of an 8 - bit feature vector and an 8 - bit weight.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically to an SRAM-based in-memory computing unit and array. Background Technology

[0002] In the von Neumann architecture, the computation unit and the storage unit are separate. The computation unit reads data from the storage unit, processes it, and then writes the results back to the storage unit. This separation leads to the "memory wall" problem, where the memory access speed cannot keep up with the processor's processing speed, thus limiting overall performance.

[0003] In-memory computing moves computational operations to an array of memory, avoiding frequent data transfers between storage and computation units. This design significantly reduces data transfers between the processor and memory, thereby increasing computational speed and reducing energy consumption.

[0004] In addition, existing in-memory computing units and arrays generally suffer from large area and relatively high power consumption. Summary of the Invention

[0005] The purpose of this invention is to provide an in-memory computing unit and array that can realize the integration of storage and computing functions, save chip area, and improve performance and save costs.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] An in-memory computing unit includes:

[0008] A single SRAM six-transistor (6T) memory cell is used to store data;

[0009] And a computing unit consisting of two NMOS transistors, used for calculation.

[0010] Furthermore, the number of the SRAM six-transistor storage units is 8, and each of the SRAM six-transistor storage units and the 8 computing units form a column of in-memory computing array.

[0011] Furthermore, the SRAM six-transistor memory cell includes:

[0012] Two inverters connected end-to-end are used to latch data;

[0013] Two NMOS transmission transistors are used to transmit data, and the data of the inverter can be read and modified.

[0014] Two storage nodes, denoted as Q and QN respectively;

[0015] Word lines (WL), bit lines (BL), and bit lines not connected to BLB are used for reading, writing, and storing data in SRAM.

[0016] Furthermore, the computing unit includes two NMOS transistors, one of which has its source (or drain) connected to the input signal IN, its drain (or source) connected to the output signal OUT, and its gate connected to the storage node Q; the other transistor has its source (or drain) connected to ground GND, its drain (or source) connected to the output signal OUT, and its gate connected to the storage node QN.

[0017] Furthermore, it includes 8 input signals IN[0]~IN[7], and the output signal includes: OUT[j][i] (where j∈[0:7], i∈[0:7], and i and j are both integers).

[0018] Furthermore, the eight SRAM six-transistor memory cells are controlled by the same word line signal WL.

[0019] The in-memory computing unit and array provided by this invention have the following advantages compared with the prior art:

[0020] 1) The in-memory computing unit provided by the present invention contains 8 transistors, one column of in-memory computing array contains 22 transistors, and eight columns of in-memory computing array contain a total of 176 transistors. Compared with the existing solutions that achieve the same function, the present invention has fewer transistors, which can save chip area and improve performance and save costs.

[0021] 2) The in-memory computing array provided by this invention can realize the matrix product of 8-bit feature vectors and 8-bit weights. Attached Figure Description

[0022] Figure 1 This is a circuit diagram of the in-memory computing unit according to an embodiment of the present invention;

[0023] Figure 2 This is a circuit diagram of an in-memory computing array based on existing technology;

[0024] Figure 3 This is a circuit diagram of an in-memory computing array according to an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0027] In order to break through the bottleneck of the separation of storage and computing in the traditional von Neumann architecture, as well as the problem of the large area of ​​existing in-memory computing units and arrays, this application discloses an in-memory computing unit and array through the following embodiments. On the one hand, it can realize the function of storage and computing integration, and on the other hand, it can save chip area, thereby improving performance and saving costs.

[0028] like Figure 1 As shown, the in-memory computing unit provided by the present invention includes: a six-transistor SRAM memory unit and a computing unit composed of two NMOS transistors, for a total of 8 transistors.

[0029] The SRAM six-transistor storage cell is used to store weighted data. In this embodiment, the SRAM six-transistor storage cell is composed of two inverters INV0 and INV1 connected end to end, two NMOS transmission transistors N0 and N1, as well as word line WL, bit line BL and bit line non-BLB.

[0030] The computing unit composed of the two NMOS transistors N2 and N3 is used for calculation. The source (or drain) of transistor N2 is connected to the input signal IN, the drain (or source) is connected to the output signal OUT, and the gate is connected to the storage node Q. The source (or drain) of transistor N3 is grounded to GND, the drain (or source) is connected to the output signal OUT, and the gate is connected to the storage node QN.

[0031] Figure 1 The truth table of the in-memory computing unit is shown in Table 1.

[0032] Table 1 Truth table of the input feature vector and the stored weights

[0033] Q(W) QN IN OUT 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1

[0034] The results in Table 1 show that when the storage node Q is 0, that is, the storage weight is 0, QN is 1, and NMOS transistor N2 is in the off state. Therefore, whether the input IN is 0 or 1, it will not affect the output OUT. Since QN is 1, NMOS transistor N3 is in the on state, and one end of N3 is connected to ground GND, which is a low level 0. Therefore, the output OUT is 0.

[0035] When the storage node Q is 1, meaning the storage weight is 1, QN is 0. NMOS transistor N2 is on, and NMOS transistor N3 is off. Since N2 is on, when the input IN is 0, OUT is 0; when the input IN is 1, OUT is 1.

[0036] As can be seen from the results in Table 1, the product of the input feature vector IN and the stored weight Q(W) satisfies the following relationship: OUT = IN × W.

[0037] Figure 2 The diagram shows a prior art in-memory computing array scheme. This array is used to perform 4-bit input IN and 4-bit weight W operations. The weight in the diagram is an SRAM six-transistor cell that stores the weight. A single-bit in-memory computing unit in this array consists of an SRAM six-transistor cell and a NOR gate. An SRAM six-transistor cell has 6 transistors and a NOR gate has 4 transistors. Therefore, the single-bit in-memory computing unit contains 10 transistors.

[0038] like Figure 3 As shown, the present invention also provides an in-memory computing array, including... Figure 1 The SRAM six-transistor memory cell in the middle has a total of 8 cells, and each SRAM six-transistor memory cell is associated with 8 transistors. Figure 1 The computing units in the array form a column of in-memory computing array, with a total of 8 columns, forming an in-memory computing array. The 8 SRAM six-transistor memory cells are controlled by the same word line signal WL. In addition, the array also contains 8 input signals IN[0]~IN[7], and the output signal is: OUT[j][i] (where j∈[0:7], i∈[0:7], and i and j are both integers).

[0039] Compared with existing solutions, the present invention has the following advantages:

[0040] like Figure 1 As shown, the in-memory computing unit of this invention contains 8 transistors. Figure 2 The in-memory computing unit shown contains 10 transistors. In comparison, the present invention saves (10-8) / 10 = 20% of the number of transistors. Therefore, while achieving the same single-bit computing function, the present invention greatly saves chip area.

[0041] Figure 2 The existing array shown is used for 4-bit input IN and 4-bit weight W operations. To implement 8-bit input IN and 8-bit weight W operations, the number of transistors required is 10 × 64 = 640. Figure 3As shown, in this invention, one SRAM six-transistor unit and eight computing units form a column, containing a total of (6 + 2 × 8) = 22 transistors. To implement the 8-bit input IN and 8-bit weight W operations, a total of eight columns are needed, totaling 22 × 8 = 176 transistors. Compared to existing solutions, this solution saves transistors by (640 - 176) / 640 = 72.5% in implementing the 8-bit input IN and 8-bit weight W operations.

[0042] Therefore, the in-memory computing unit and array provided by this invention can, on the one hand, realize the integration of storage and computing functions; on the other hand, it can save chip area, thereby improving performance and saving costs.

Claims

1. A storage-computing integrated unit, characterized in that, include: A single SRAM six-transistor (6T) memory cell is used to store data; And a computing unit consisting of two NMOS transistors, used for calculation.

2. The in-memory computing array according to claim 1, characterized in that, The number of SRAM six-transistor storage units is 8, and each SRAM six-transistor storage unit and the 8 computing units form a column of in-memory computing array.

3. The in-memory computing unit according to claim 1, characterized in that, The SRAM six-transistor memory cell includes: Two inverters connected end-to-end are used to latch data; Two NMOS transmission transistors are used to transmit data, and the data of the inverter can be read and modified. Two storage nodes, denoted as Q and QN respectively; Word lines (WL), bit lines (BL), and bit lines not connected to BLB are used for reading, writing, and storing data in SRAM.

4. The in-memory computing unit according to claim 1, characterized in that, The computing unit includes two NMOS transistors. The source (or drain) of one transistor is connected to the input signal IN, the drain (or source) is connected to the output signal OUT, and the gate is connected to the storage node Q. The source (or drain) of the other transistor is grounded to GND, the drain (or source) is connected to the output signal OUT, and the gate is connected to the storage node QN.

5. The in-memory computing array according to claim 2, characterized in that, It includes 8 input signals IN[0]~IN[7], and the output signal includes: OUT[j][i] (where j∈[0:7], i∈[0:7], and i and j are both integers).

6. The in-memory computing array according to claim 2, characterized in that, The eight SRAM six-transistor memory cells are controlled by the same word line signal WL.

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