Edge emitting semiconductor laser chip, method of manufacturing and method of failure analysis thereof

Abstract

The application provides an edge-emitting semiconductor laser chip and a preparation method and a failure analysis method thereof. The preparation method comprises the following steps: forming a light-emitting structure on one side of a semiconductor substrate layer along a first direction, wherein the light-emitting structure comprises a first cladding layer, an active layer and a second cladding layer arranged in sequence away from the semiconductor substrate layer along the first direction; the light-emitting structure comprises a ridge-shaped region; etching part of the light-emitting structure located on at least one side of the ridge-shaped region along a slow axis direction to form an opening etched through the second cladding layer and the active layer along the first direction; forming a front electrode, wherein the front electrode is located on a side of the ridge-shaped region away from the semiconductor substrate layer and connected with the ridge-shaped region, and the front electrode exposes the opening; and forming a back electrode on a side of the semiconductor substrate layer away from the light-emitting structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a side-emitting semiconductor laser chip, its fabrication method, and its failure analysis method. Background Technology

[0002] Single-mode output edge-emitting semiconductor laser chips have important applications in pumping and optical communication, and these chips typically require extremely high reliability. During long-term reliability verification and iteration, failure analysis of failed devices is crucial for identifying the causes of failure and improving reliability in a targeted manner. Summary of the Invention

[0003] The technical problem to be solved by this invention is how to improve the accuracy of failure analysis of semiconductor laser chips and reduce damage to semiconductor laser chips, thereby providing a side-emitting semiconductor laser chip, its preparation method and failure analysis method.

[0004] This application provides a method for fabricating a side-emitting semiconductor laser chip, comprising: forming a light-emitting structure on one side of a semiconductor substrate along a first direction, the light-emitting structure including a first cladding layer, an active layer, and a second cladding layer arranged sequentially in the first direction away from the semiconductor substrate; the light-emitting structure including a ridge region; etching a portion of the light-emitting structure located on at least one side of the ridge region along the slow axis direction to form an opening penetrating the second cladding layer and the active layer in the first direction; forming a front electrode located on the side of the ridge region away from the semiconductor substrate and connected to the ridge region, the front electrode exposing the opening; and forming a back electrode on the side of the semiconductor substrate away from the light-emitting structure.

[0005] Optionally, the fabrication method of the edge-emitting semiconductor laser chip further includes: forming a passivation layer on the surface of the light-emitting structure on both sides of the ridge region in the slow axis direction away from the semiconductor substrate, the passivation layer exposing the ridge region; wherein, before forming the opening, a front electrode is formed on the passivation layer and the side of the ridge region away from the semiconductor substrate; wherein, during the formation of the opening, the passivation layer and the front electrode are also etched, the opening also penetrates the passivation layer and the front electrode in the first direction, the opening is located on the side of the ridge region in the slow axis direction and extends along the cavity length direction.

[0006] Optionally, the fabrication method of the edge-emitting semiconductor laser chip further includes: forming a passivation layer on the surface of the light-emitting structure on both sides of the ridge region in the slow axis direction away from the semiconductor substrate, the passivation layer exposing the ridge region; wherein, after forming the passivation layer, the opening is formed, and during the formation of the opening, the passivation layer is also etched, the opening penetrates the passivation layer in the first direction and is located on both sides of the ridge region in the slow axis direction; the opening located on one side of the ridge region extends along the cavity length direction; on the other side of the ridge region, a plurality of openings are spaced apart along the cavity length direction and extend along the slow axis direction; wherein, the fabrication method of the edge-emitting semiconductor laser chip further includes: forming a front electrode, the front electrode being located on the side of the passivation layer around the opening away from the semiconductor substrate and on the side of the ridge region away from the semiconductor substrate.

[0007] Optionally, the method for fabricating the edge-emitting semiconductor laser chip further includes: forming a sacrificial layer in the opening before forming the front electrode; and removing the sacrificial layer after forming the front electrode.

[0008] Optionally, the opening and the ridge region are spaced 10 micrometers to 40 micrometers apart in the slow axis direction.

[0009] Optionally, the size of the opening in the slow axis direction is greater than or equal to 5 micrometers.

[0010] This application also provides a side-emitting semiconductor laser chip, comprising: a semiconductor substrate; a light-emitting structure located on one side of the semiconductor substrate along a first direction, the light-emitting structure comprising a first cladding layer, an active layer, and a second cladding layer arranged sequentially in the first direction away from the semiconductor substrate; the light-emitting structure comprising a ridge region; an opening located on at least one side of the ridge region along the slow axis direction and penetrating the second cladding layer and the active layer in the first direction; a front electrode located on the side of the ridge region away from the semiconductor substrate and connected to the ridge region, the front electrode exposing the opening; and a back electrode located on the side of the semiconductor substrate away from the light-emitting structure.

[0011] Optionally, the edge-emitting semiconductor laser chip further includes: a passivation layer, and light-emitting structures located on both sides of the ridge region in the slow axis direction facing away from the surface of the semiconductor substrate layer; wherein, the front electrode is located on the passivation layer and the side of the ridge region facing away from the semiconductor substrate layer; wherein, the opening penetrates the front electrode, the passivation layer, the second cladding layer and the active layer in a first direction, and the opening is located on the side of the ridge region in the slow axis direction and extends along the cavity length direction.

[0012] Optionally, the edge-emitting semiconductor laser chip further includes: a passivation layer, and light-emitting structures located on both sides of the ridge region in the slow axis direction facing away from the surface of the semiconductor substrate; wherein the opening penetrates the passivation layer, the second cladding layer, and the active layer in the first direction, and the opening is located on both sides of the ridge region in the slow axis direction; the opening located on one side of the ridge region extends along the cavity length direction; on the other side of the ridge region, a plurality of openings are spaced apart along the cavity length direction and extend along the slow axis direction; wherein the front electrode is located on the side of the passivation layer facing away from the semiconductor substrate around the opening and on the side of the ridge region facing away from the semiconductor substrate, and the front electrode is connected to the ridge region.

[0013] Optionally, the front electrode includes a first electrode portion and a second electrode portion spaced apart. The first electrode portion is located on the side of the ridge region away from the semiconductor substrate layer along the first direction and extends between the ridge region and the opening, as well as on the side of the ridge region away from the opening along the slow axis direction. The second electrode portion is located on the side of the opening away from the ridge region along the slow axis direction. The first electrode portion and the second electrode portion extend along the cavity length direction.

[0014] Optionally, the front electrode includes a first electrode portion, a second electrode portion, and a third electrode portion. The first electrode portion, the third electrode portion, and the second electrode portion are arranged sequentially and connected in the slow axis direction. The first electrode portion is located on the side of the ridge region away from the semiconductor substrate layer along the first direction and extends between the ridge region and the opening extending along the slow axis direction. The third electrode portion is located between adjacent openings in the cavity length direction. The second electrode portion is located on the side of the opening extending along the slow axis direction away from the first electrode portion in the slow axis direction. The first electrode portion and the second electrode portion extend along the cavity length direction.

[0015] Optionally, the opening and the ridge region are spaced 10 micrometers to 40 micrometers apart in the slow axis direction.

[0016] Optionally, the size of the opening in the slow axis direction is greater than or equal to 5 micrometers.

[0017] This application also provides a failure analysis method for a side-emitting semiconductor laser chip, comprising: placing an image acquisition device on the side of the opening away from the semiconductor substrate layer; applying a test voltage to the front electrode and the back electrode to cause the side-emitting semiconductor laser chip to emit light, wherein the light emitted by the active layer is reflected by the back electrode and then emitted from the opening; acquiring the light beam emitted from the opening through the image acquisition device to obtain a test image; and obtaining the failure point of the active layer in the ridge region based on the test image.

[0018] Optionally, the method further includes: placing the edge-emitting semiconductor laser chip on one side of the heat sink along the first direction; supporting it with a support structure on the side of the heat sink away from the edge-emitting semiconductor laser chip; translating the support structure along the cavity length direction using a translation device to move the semiconductor laser chip along the cavity length direction; and acquiring a test image by using the image acquisition device during the translation of the semiconductor laser chip along the cavity length direction.

[0019] The technical solution of this invention has the following beneficial effects: The edge-emitting semiconductor laser chip provided by this invention has a high reflectivity at the interface between the back electrode and the semiconductor substrate. Light emitted from the active layer is transmitted towards and reflected by the back electrode, and then exits through an opening. The light exiting through the opening carries information about the luminous intensity of the active layer along the cavity length. By collecting light through the opening, the luminous intensity distribution maps of the active layer in the ridge region along the slow axis and the cavity length direction can be obtained. Since the opening is located on the side of the ridge region along the slow axis, the active layer in the ridge region is not damaged during the opening formation process. Because it is not necessary to remove the back electrode and the semiconductor substrate, mechanical or chemical damage to the active layer is avoided. Through a non-destructive failure analysis method, the failure point of the edge-emitting semiconductor laser chip can be accurately located, improving the accuracy of failure analysis and reducing damage to the semiconductor laser chip. Attached Figure Description

[0020] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 A structural diagram for failure analysis of a side-emitting semiconductor laser chip; Figure 2 This is a flowchart illustrating the fabrication process of a side-emitting semiconductor laser chip according to an embodiment of this application; Figures 3 to 11 This is a structural diagram illustrating the fabrication process of an edge-emitting semiconductor laser chip according to an embodiment; Figures 12 to 17 This is a structural diagram illustrating the fabrication process of an edge-emitting semiconductor laser chip according to another embodiment; Figure 18 This is a schematic diagram illustrating the failure analysis process of a side-emitting semiconductor laser chip according to another embodiment of this application; Figure 19This is a schematic diagram illustrating the failure analysis process of a side-emitting semiconductor laser chip according to another embodiment of this application; Figure 20 This is a schematic diagram illustrating the failure analysis process of a side-emitting semiconductor laser chip according to another embodiment of this application; Figure 21 This is a schematic diagram of a test image. Detailed Implementation

[0022] Edge-emitting semiconductor laser chips typically require etching to form long ridge waveguides during wafer fabrication. These ridge waveguides are responsible for emission, and their width along the slow axis is usually less than 10 micrometers, while their size along the fast axis is around several millimeters. The most critical step in failure analysis is accurately locating the failure point within this scale. The fabrication process of edge-emitting semiconductor laser chips mainly includes: depositing an epitaxial layer responsible for emission on the surface of a semiconductor substrate; followed by cleaving, coating, and encapsulation to form the edge-emitting semiconductor laser chip. The front side of the epitaxial layer of the edge-emitting semiconductor laser chip covers a front electrode, and the back side of the semiconductor substrate covers a back electrode. The edge-emitting semiconductor laser chip is soldered onto a heat sink. Even after power-on testing for electroluminescence following failure, light absorption by the back electrode makes it difficult for light to penetrate the semiconductor substrate, thus hindering the collection of emission information and making it impossible to directly locate the corresponding failure point. This is a major challenge in the failure analysis of edge-emitting semiconductor laser chips. In this situation, one method of failure analysis is to refer to… Figure 1 Electroluminescence observation can be performed by removing the back electrode and semiconductor substrate layer. However, these methods are accompanied by chemical corrosion and physical-mechanical processes. These destructive methods often cause new damage to the edge-emitting semiconductor laser chip during sample preparation, especially damage to the active layer in the ridge region, which interferes with the determination of the initial damage location of the edge-emitting semiconductor laser chip.

[0023] Based on this, this application provides a side-emitting semiconductor laser chip, its fabrication method, and a failure analysis method. Through a non-destructive failure analysis method, the failure points of the side-emitting semiconductor laser chip are accurately located. This improves the accuracy of failure analysis for semiconductor laser chips and reduces damage to the semiconductor laser chip.

[0024] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0026] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0027] An embodiment of the present invention provides a method for fabricating a side-emitting semiconductor laser chip, comprising: S1: A light-emitting structure is formed on one side of the semiconductor substrate layer along a first direction. The light-emitting structure includes a first cladding layer, an active layer, and a second cladding layer arranged sequentially in the first direction away from the semiconductor substrate layer. The light-emitting structure includes a ridge region. S2: Etch the portion of the light-emitting structure located on at least one side of the ridge region along the slow axis direction to form an opening that penetrates the second cladding and the active layer in the first direction; S3: Form a front electrode. The front electrode is located on the side of the ridge region away from the semiconductor substrate and is connected to the ridge region. The front electrode exposes an opening. S4: A back electrode is formed on the side of the semiconductor substrate layer away from the light-emitting structure.

[0028] In this embodiment, the fabrication method of the edge-emitting semiconductor laser chip has a high reflectivity at the interface between the back electrode and the semiconductor substrate. Light emitted from the active layer is transmitted towards the back electrode and reflected by it. The reflected light exits through an opening. The light exiting through the opening carries information about the luminous intensity of the active layer along the cavity length. By collecting light through the opening, the luminous intensity distribution map of the active layer in the ridge region along the slow axis and the cavity length direction can be obtained. Since the opening is located on the side of the ridge region along the slow axis, the active layer in the ridge region is not damaged during the opening formation process. Since it is not necessary to remove the back electrode and the semiconductor substrate, mechanical or chemical damage to the active layer is avoided. By using a non-destructive failure analysis method, the failure point of the edge-emitting semiconductor laser chip can be accurately located, improving the failure analysis accuracy of the semiconductor laser chip and reducing damage to the semiconductor laser chip.

[0029] In some embodiments, the method for fabricating a side-emitting semiconductor laser chip further includes: forming a passivation layer on the surface of the light-emitting structure on both sides of the ridge region in the slow axis direction away from the semiconductor substrate, the passivation layer exposing the ridge region; wherein, before forming the opening, a front electrode is formed on the passivation layer and the side of the ridge region away from the semiconductor substrate; wherein, during the process of forming the opening, the passivation layer and the front electrode are also etched, the opening also penetrates the passivation layer and the front electrode in a first direction, the opening is located on the side of the ridge region in the slow axis direction and extends along the cavity length direction.

[0030] The following is for reference. Figures 3 to 11 This application provides a detailed description of a method for fabricating a side-emitting semiconductor laser chip according to an embodiment of the present application.

[0031] refer to Figures 3 to 4 A light-emitting structure 110 is formed on one side of the semiconductor substrate 100 along the first direction Z. The light-emitting structure 110 includes a first cladding layer 111, an active layer 112, and a second cladding layer 113 arranged sequentially away from the semiconductor substrate 100 along the first direction Z. The light-emitting structure 110 includes a ridge region J.

[0032] refer to Figure 3 A first cladding layer 111, an active layer 112, and a second initial cladding layer 113a are sequentially formed on one side of the semiconductor substrate layer 100 along the first direction Z.

[0033] The first cladding 111, the active layer 112, and the second initial cladding 113a are formed continuously in the same chamber.

[0034] The formation of the first cladding layer 111 includes forming a first confinement layer and forming a first waveguide layer, wherein the first waveguide layer is located on the side of the first confinement layer opposite to the semiconductor substrate layer 100. The formation of the second initial cladding layer 113a includes forming a second waveguide layer and forming a second confinement layer, wherein the second confinement layer is located on the side of the second waveguide layer opposite to the active layer 112. The formation of the second initial cladding layer 113a also includes forming a contact layer, which is located on the side of the second confinement layer opposite to the second waveguide layer.

[0035] In some embodiments, the semiconductor substrate 100 is an InP substrate. It should be noted that in other embodiments, the semiconductor substrate 100 may also be made of other materials.

[0036] In some embodiments, the material of the first confining layer is InP doped with conductive ions.

[0037] The first waveguide layer is made of In doped with conductive ions. x1 Ga 1-x1 As. The second confinement layer is made of InP doped with conductive ions. The second waveguide layer is made of InP doped with conductive ions. x1 Ga 1-x1As.

[0038] In some embodiments, the active layer 112 includes a barrier layer and a quantum well layer. Exemplarily, the barrier layer is made of a material including In... y Al (1-y) As, the material of the quantum well layer is In. x Ga (1-x) As.

[0039] Wherein, the first direction Z is the fast axis direction.

[0040] refer to Figure 4 The second initial cladding 113a is etched to form the second cladding 113.

[0041] Etching a portion of the second initial cladding 113a, for example, may involve etching the contact layer and the second confinement layer, or etching the contact layer, the second confinement layer, and a portion of the second waveguide layer.

[0042] The light-emitting structure 110 includes a ridge region J and non-injection regions located on both sides of the ridge region J in the slow axis direction X. The size of the non-injection regions in the first direction Z is smaller than the size of the ridge region J in the first direction Z. The ridge region J includes a portion of a first cladding 111, a portion of an active layer 112, and a portion of a second cladding 113. The non-injection regions include a portion of the first cladding 111, a portion of the active layer 112, and a portion of the second cladding 113. The size of the second cladding 113 in the non-injection region in the first direction Z is smaller than the size of the second cladding 113 in the ridge region J in the first direction Z. The non-injection regions do not include a contact layer. The ridge region J includes a contact layer.

[0043] refer to Figure 5 A passivation layer 120 is formed on the surface of the light-emitting structures 110 on both sides of the ridge region J in the slow axis direction X, away from the semiconductor substrate layer 100. The passivation layer 120 exposes the ridge region J. The passivation layer 120 also covers the sidewalls of the portion of the ridge region J that protrudes from the non-injection region.

[0044] In some embodiments, the material of the passivation layer 120 includes silicon oxide.

[0045] refer to Figure 6 A front electrode 130 is formed on the side of the passivation layer 120 and the ridge region J away from the semiconductor substrate layer 100.

[0046] The front electrode 130 is connected to the ridge region J. For example, the front electrode 130 is connected to the contact layer.

[0047] The front electrode 130 is described in detail in the following embodiment.

[0048] refer to Figures 7 to 10 , Figure 10for Figure 9 A top view of the front electrode 130 shows the portion of the light-emitting structure 110 located on the ridge region J along the slow axis direction X, forming an opening 140 that etches through the second cladding layer 113 and the active layer 112 in the first direction Z.

[0049] refer to Figure 7 A mask layer W is formed on the side of the front electrode 130 that is away from the semiconductor substrate layer 100.

[0050] In some embodiments, the process for forming the mask layer W includes a spin coating process. The material of the mask layer W includes photoresist.

[0051] refer to Figure 8 A graphical mask layer W is created, and mask openings (not shown) are formed in the mask layer W.

[0052] The process of patterned mask layer W includes: exposing mask layer W to light; and then developing mask layer W.

[0053] Continue to refer to Figure 8 Using a patterned mask layer W as a mask, the portion of the front electrode 130, passivation layer 120 and light-emitting structure 110 located on the slow axis direction X side of the ridge region J is etched to form an opening 140 that penetrates the front electrode 130, passivation layer 120, second cladding layer 113 and active layer 112 in the first direction Z.

[0054] The opening 140 is located on one side of the ridge region J in the slow axis direction X and extends along the cavity length direction Y. The opening 140 penetrates the front electrode 130, the passivation layer 120, the second cladding layer 113, and the active layer 112 in the cavity length direction Y. The size of the opening 140 in the cavity length direction Y is larger than the size of the opening 140 in the slow axis direction X.

[0055] In some embodiments, the size of the opening 140 in the slow axis direction X is greater than or equal to 5 micrometers, for example, the size of the opening 140 in the slow axis direction X is equal to 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, 9 micrometers or 10 micrometers.

[0056] In some embodiments, the opening 140 and the ridge region J are spaced 10 to 40 micrometers apart in the slow axis direction X, for example, 10 micrometers, 20 micrometers, 30 micrometers or 40 micrometers apart.

[0057] refer to Figure 9 Remove the graphical mask layer W.

[0058] The process for removing the patterned mask layer W can be an ashing process.

[0059] Figure 9 In order to be in Figure 8 A basic diagram. Figure 10 for Figure 9 Top view of the front electrode 130.

[0060] In this embodiment, the opening 140 is formed after the front electrode 130 is formed, which simplifies the process.

[0061] refer to Figure 11 , Figure 11 In order to be in Figure 9 The schematic diagram shows that a back electrode 150 is formed on the side of the semiconductor substrate 100 opposite to the light-emitting structure 110.

[0062] Another embodiment of this application provides a method for fabricating a side-emitting semiconductor laser chip. The difference between this embodiment and the previous embodiment includes: forming a passivation layer on the surface of the light-emitting structure on both sides of the ridge region in the slow axis direction away from the semiconductor substrate layer, and exposing the ridge region; wherein, after forming the passivation layer, an opening is formed, and during the process of forming the opening, the passivation layer is also etched, and the opening penetrates the passivation layer in a first direction and is located on both sides of the ridge region in the slow axis direction; the opening located on one side of the ridge region extends along the cavity length direction; on the other side of the ridge region, multiple openings are arranged at intervals along the cavity length direction and the openings extend along the slow axis direction; wherein, the method for fabricating the side-emitting semiconductor laser chip further includes: forming a front electrode, the front electrode being located on the side of the passivation layer around the opening away from the semiconductor substrate layer and on the side of the ridge region away from the semiconductor substrate layer.

[0063] refer to Figures 12 to 17 The fabrication process of a side-emitting semiconductor laser chip according to another embodiment of this application is described in detail.

[0064] refer to Figure 12 , Figure 12 In order to be in Figure 4 In the schematic diagram, a passivation layer 120 is formed on the surface of the light-emitting structures 110 on both sides of the ridge region J in the slow axis direction X, away from the semiconductor substrate layer 100. The passivation layer 120 exposes the ridge region J. The passivation layer 120 also covers the sidewalls of the portion of the ridge region J that protrudes from the non-injection region.

[0065] In some embodiments, the material of the passivation layer 120 includes silicon oxide.

[0066] refer to Figures 13 to 15 The portion of the passivation layer 120 and the light-emitting structure 110 located on both sides of the ridge region J along the slow axis direction X is etched to form an opening 140 that etches through the passivation layer 120, the second cladding layer 113 and the active layer 112 in the first direction Z.

[0067] refer to Figure 13 , Figure 13 In order to be in Figure 12The schematic diagram shows that a mask layer W is formed on the side of the passivation layer 120 and the ridge region J away from the semiconductor substrate layer 100.

[0068] In some embodiments, the process for forming the mask layer W includes a spin coating process. The material of the mask layer W includes photoresist.

[0069] refer to Figure 14 and Figure 15 , Figure 14 In order to be in Figure 13 A basic diagram. Figure 15 for Figure 14 A top view of the light-emitting structure 110, a patterned mask layer W, in which mask openings (not shown) are formed; using the patterned mask layer W as a mask, the passivation layer 120 and the portion of the light-emitting structure 110 located on both sides of the ridge region J along the slow axis direction X are etched to form an opening 140 that penetrates the passivation layer 120, the second cladding layer 113 and the active layer 112 in the first direction Z.

[0070] The process of patterned mask layer W includes: exposing mask layer W to light; and then developing mask layer W.

[0071] Openings 140 are located on both sides of the ridge region J in the slow axis direction X; the opening 140 on one side of the ridge region J extends along the cavity length direction Y. For example, the opening 140 on one side of the ridge region J penetrates the passivation layer 120, the second cladding layer 113 and the active layer 112 in the cavity length direction Y. The size of the opening 140 on one side of the ridge region J in the cavity length direction Y is larger than the size of the opening 140 in the slow axis direction X. On the other side of the ridge region J, a plurality of openings 140 are arranged at intervals in the cavity length direction Y and extend along the slow axis direction X. For example, the size of a single opening 140 on the other side of the ridge region J in the slow axis direction X is larger than the size of the opening 140 in the cavity length direction Y.

[0072] In some embodiments, the size of the opening 140 in the slow axis direction X is greater than or equal to 5 micrometers. For example, the size of the opening 140 in the slow axis direction X is equal to 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, 9 micrometers, or 10 micrometers.

[0073] In some embodiments, the opening 140 and the ridge region J are spaced 10 to 40 micrometers apart in the slow axis direction X, for example, 10 micrometers, 20 micrometers, 30 micrometers or 40 micrometers apart.

[0074] In some embodiments, the method further includes: removing the patterned mask layer W. The process for removing the patterned mask layer W can be an ashing process.

[0075] refer to Figure 16 and Figure 17 , Figure 16 In order to be in Figure 14 A basic diagram. Figure 17 for Figure 16 A top view of the front electrode 130 shows the front electrode 130 formed on the side of the passivation layer 120 surrounding the opening 140 that faces away from the semiconductor substrate layer 100, and on the side of the ridge region J that faces away from the semiconductor substrate layer 100. The front electrode 130 is connected to the ridge region J.

[0076] For example, the front electrode 130 is connected to the contact layer.

[0077] In some embodiments, the front electrode 130 is formed after the patterned mask layer W is removed.

[0078] In some embodiments, a sacrificial layer is formed in the opening 140 before the front electrode 130 is formed; the sacrificial layer is removed after the front electrode 130 is formed. The material of the sacrificial layer can be amorphous carbon. Exemplarily, the sacrificial layer is formed in the opening 140 after the patterned mask layer W is removed; the front electrode 130 is formed after the sacrificial layer is formed; the sacrificial layer is removed after the front electrode 130 is formed.

[0079] The front electrode 130 is described in detail in the following embodiment.

[0080] In this embodiment, after the opening 140 is formed, the front electrode 130 is formed. The front electrode 130 is not etched during the formation of the opening 140, so that the size difference of the opening 140 on both sides of the ridge region J in the slow axis direction X is reduced in the first direction.

[0081] Continue to refer to Figure 16 A back electrode 150 is formed on the side of the semiconductor substrate 100 opposite to the light-emitting structure 110.

[0082] Another embodiment of this application also provides a side-emitting semiconductor laser chip, see reference. Figure 11 , Figure 10 , Figure 16 and Figure 17 The edge-emitting semiconductor laser chip includes: Semiconductor substrate layer 100; A light-emitting structure 110 is located on one side of the semiconductor substrate layer 100 along the first direction Z. The light-emitting structure 110 includes a first cladding layer 111, an active layer 112, and a second cladding layer 113 arranged sequentially in the first direction Z away from the semiconductor substrate layer 100. The light-emitting structure 110 includes a ridge region J (reference). Figure 4 and Figure 12 ); An opening 140 is located on at least one side of the ridge region J along the slow axis direction X and penetrates the second cladding 113 and the active layer 112 in the first direction Z; A front electrode 130 is located on the side of the ridge region J away from the semiconductor substrate layer 100 and connected to the ridge region J, and the front electrode 130 exposes an opening 140. The back electrode 150 is located on the side of the semiconductor substrate 100 away from the light-emitting structure 110.

[0083] In this embodiment, the interface between the back electrode 150 and the semiconductor substrate 100 has a high reflectivity. Light emitted from the active layer 112 is transmitted towards the back electrode 150 and reflected by it. The light reflected by the back electrode 150 exits through the opening 140. The light exiting through the opening 140 carries information about the luminous intensity of the active layer 112 along the cavity length direction Y. By collecting light through the opening 140, the luminous intensity distribution map of the active layer 112 in the ridge region J along the slow axis direction X and the cavity length direction Y can be obtained. Since the opening 140 is located on the side of the ridge region J along the slow axis direction X, the active layer 112 of the ridge region J will not be damaged during the formation of the opening 140. Since it is not necessary to remove the back electrode 150 and the semiconductor substrate 100, mechanical or chemical damage to the active layer 112 is avoided. By using a non-destructive failure analysis method, the failure point of the edge-emitting semiconductor laser chip can be accurately located, improving the failure analysis accuracy of the semiconductor laser chip and reducing damage to the semiconductor laser chip.

[0084] In some embodiments, the semiconductor substrate 100 is an InP substrate. It should be noted that in other embodiments, the semiconductor substrate 100 may also be made of other materials.

[0085] In some embodiments, the first cladding layer 111 includes a first confinement layer and a first waveguide layer, the first waveguide layer being located on the side of the first confinement layer opposite to the semiconductor substrate layer 100; the second cladding layer 113 includes a second confinement layer and a second waveguide layer, the second confinement layer being located on the side of the second waveguide layer opposite to the active layer 112. The second cladding layer 113 may further include a contact layer, the contact layer being located on the side of the second confinement layer opposite to the second waveguide layer.

[0086] The light-emitting structure 110 includes a ridge region J and non-injection regions located on both sides of the ridge region J in the slow axis direction X. The size of the non-injection regions in the first direction Z is smaller than the size of the ridge region J in the first direction Z. The ridge region J includes a portion of a first cladding 111, a portion of an active layer 112, and a portion of a second cladding 113. The non-injection regions include a portion of the first cladding 111, a portion of the active layer 112, and a portion of the second cladding 113. The size of the second cladding 113 in the non-injection region in the first direction Z is smaller than the size of the second cladding 113 in the ridge region J in the first direction Z. The non-injection regions do not include a contact layer. The ridge region J includes a contact layer.

[0087] In some embodiments, the material of the first confinement layer is InP doped with conductive ions. The material of the first waveguide layer is InP doped with conductive ions. x1 Ga 1-x1 As. The second confinement layer is made of InP doped with conductive ions. The second waveguide layer is made of InP doped with conductive ions. x1 Ga 1-x1 As.

[0088] In some embodiments, the active layer 112 includes a barrier layer and a quantum well layer. Exemplarily, the barrier layer is made of a material including In... y Al (1-y) As, the material of the quantum well layer is In. x Ga (1-x) As.

[0089] Wherein, the first direction Z is the fast axis direction.

[0090] refer to Figure 11 and Figure 16 The edge-emitting semiconductor laser chip also includes a passivation layer 120, which is located on both sides of the ridge region J in the slow axis direction X, away from the surface of the light-emitting structure 110 of the semiconductor substrate layer 100. The passivation layer 120 also covers the sidewalls of the portion of the ridge region J that protrudes from the non-injection region. The material of the passivation layer 120 includes silicon oxide.

[0091] refer to Figure 11 and Figure 10 The front electrode 130 is located on the side of the passivation layer 120 and the ridge region J facing away from the semiconductor substrate layer 100, and is connected to the contact layer. An opening 140 penetrates the front electrode 130, passivation layer 120, second cladding layer 113, and active layer 112 in the first direction Z. The opening 140 is located on the side of the ridge region J in the slow axis direction X and extends along the cavity length direction Y. The opening 140 penetrates the front electrode 130, passivation layer 120, second cladding layer 113, and active layer 112 in the cavity length direction Y. The size of the opening 140 in the cavity length direction Y is larger than the size of the opening 140 in the slow axis direction X.

[0092] refer to Figure 10The front electrode 130 includes a first electrode portion and a second electrode portion. The first electrode portion is located on the side of the ridge region J facing away from the semiconductor substrate layer 100 along the first direction Z, and extends between the ridge region J and the opening 140, and on the side of the ridge region J facing away from the opening 140 along the slow axis direction X. The second electrode portion is located on the side of the opening 140 facing away from the ridge region J along the slow axis direction X. The first electrode portion and the second electrode portion are spaced apart. The first electrode portion extends along the cavity length direction Y, and its dimension along the cavity length direction Y is larger than its dimension along the slow axis direction X. The second electrode portion also extends along the cavity length direction Y, and its dimension along the cavity length direction Y is larger than its dimension along the slow axis direction X. A potential can be applied to the first electrode portion, and the electrical signal on the first electrode portion can apply a potential to the ridge region J.

[0093] refer to Figure 16 and Figure 17 An opening 140 penetrates the passivation layer 120, the second cladding layer 113, and the active layer 112 in the first direction Z. The opening 140 is located on both sides of the ridge region J in the slow axis direction X. The opening 140 located on one side of the ridge region J extends along the cavity length direction Y. For example, the opening 140 located on one side of the ridge region J penetrates the passivation layer 120, the second cladding layer 113, and the active layer 112 in the cavity length direction Y. The size of the opening 140 located on one side of the ridge region J in the cavity length direction Y is larger than the size of the opening 140 in the slow axis direction X. On the other side of the ridge region J, a plurality of openings 140 are arranged at intervals along the cavity length direction Y and extend along the slow axis direction X. For example, the size of a single opening 140 located on the other side of the ridge region J in the slow axis direction X is larger than the size of the opening 140 in the cavity length direction Y.

[0094] refer to Figure 16 and Figure 17 The front electrode 130 is located on the side of the passivation layer 120 surrounding the opening 140 that faces away from the semiconductor substrate layer 100, and on the side of the ridge region J that faces away from the semiconductor substrate layer 100. The front electrode 130 is connected to the contact layer.

[0095] refer to Figure 17 The front electrode 130 includes a first electrode portion 1301, a second electrode portion 1302, and a third electrode portion 1303. The first electrode portion 1301, the third electrode portion 1303, and the second electrode portion 1302 are arranged sequentially and connected in the slow axis direction X. The first electrode portion 1301 is located on the side of the ridge region J away from the semiconductor substrate layer 100 along the first direction Z and extends between the ridge region J and the opening 140 extending along the slow axis direction X. The third electrode portion 1303 is located between adjacent openings 140 in the cavity length direction Y. The second electrode portion 1302 is located on the side of the opening 140 extending along the slow axis direction X away from the first electrode portion 1301 in the slow axis direction X.

[0096] refer to Figure 17 The first electrode portion 1301 extends in the cavity length direction Y, and its dimension in the cavity length direction Y is larger than its dimension in the slow axis direction X. A plurality of third electrode portions 1303 are spaced apart in the cavity length direction Y, and their dimensions in the slow axis direction X are larger than their dimensions in the cavity length direction Y. The second electrode portion 1302 extends in the cavity length direction Y, and its dimension in the cavity length direction Y is larger than its dimension in the slow axis direction X. A potential can be applied to the second electrode portion 1302, and the electrical signal on the second electrode portion 1302 can be transmitted to the first electrode portion 1301 through the third electrode portion 1303, thereby applying a potential to the ridge region J through the first electrode portion 1301.

[0097] refer to Figure 17 The first electrode portion 1301 further extends between the ridge region J and the opening 140 extending along the cavity length direction Y. The front electrode 130 also includes a fourth electrode portion 1304, which is located on the side of the opening 140 extending along the cavity length direction Y that is opposite to the first electrode portion 1301 in the slow axis direction X. The fourth electrode portion 1304 and the first electrode portion 1301 are spaced apart.

[0098] refer to Figure 16 and Figure 17 The luminescence intensity distribution map of the active layer 112 located on the side of the ridge region J along the first direction Z can be obtained from the openings 140 on both sides of the ridge region J in the slow axis direction and cavity length direction. Multiple openings 140 arranged at intervals along the cavity direction Y are used to increase the light emission area, increase the light intensity, and optimize the observation effect.

[0099] In some embodiments, reference Figure 16 and Figure 17 The openings 140 on both sides of the ridge region J in the slow axis direction X have a size difference of less than or equal to 200 nm in the first direction Z. For example, the openings 140 on both sides of the ridge region J in the slow axis direction X have a size difference of 200 nm, 100 nm, 50 nm, 10 nm or 0 nm in the first direction Z.

[0100] In some embodiments, reference Figure 11 , Figure 10 , Figure 16 and Figure 17The spacing between the opening 140 and the ridge region J in the slow axis direction X is 10 micrometers to 40 micrometers, for example, 10 micrometers, 20 micrometers, 30 micrometers, or 40 micrometers. The spacing between the opening 140 and the ridge region J in the slow axis direction X is not too small, reducing the impact on the light emission mode of the active layer 112 in the ridge region J. The spacing between the opening 140 and the ridge region J in the slow axis direction X is not too large, allowing the opening 140 to emit light well, and enabling the image acquisition device to collect light more effectively from the opening 140.

[0101] In some embodiments, reference Figure 11 , Figure 10 , Figure 16 and Figure 17 The size of the opening 140 in the slow axis direction X is greater than or equal to 5 micrometers, ensuring a certain field of view. The emission of the active layer 112 in the ridge region J can be observed at any position along the cavity length direction Y. For example, the size of the opening 140 in the slow axis direction X is equal to 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, 9 micrometers, or 10 micrometers.

[0102] In some embodiments, reference Figure 11 , Figure 10 , Figure 16 and Figure 17 The opening 140 is spaced from the semiconductor substrate layer 100 in the first direction Z.

[0103] Another embodiment of this application also provides a failure analysis method for a side-emitting semiconductor laser chip, referring to... Figures 18 to 20 The process includes: placing an image acquisition device 210 on the side of the opening 140 away from the semiconductor substrate 100; applying a test voltage to the front electrode 130 and the back electrode 150 to cause the edge-emitting semiconductor laser chip 320 to emit light, wherein the light emitted from the active layer 112 is reflected by the back electrode 150 and then emitted from the opening 140; acquiring the light beam emitted from the opening 140 through the image acquisition device 210 to obtain a test image (see reference). Figure 21 ); The failure point of active layer 112 in ridge region J is obtained based on the test image.

[0104] The failure analysis method for edge-emitting semiconductor laser chips presented in this application is a non-destructive, visually imaging-based emission detection method. It is of great significance for accurately locating failure points, analyzing failure mechanisms, improving the reliability of edge-emitting semiconductor laser chips, and advancing process improvements.

[0105] In the obtained test images, the normal operating area of ​​the active layer 112 appears as a "bright area" due to its high luminous intensity, while areas of the active layer 112 with defects, damage, or failure appear as "dark areas" due to a sharp drop in luminous efficiency or complete absence of light. Therefore, by analyzing the morphology and location of the bright and dark distribution in the test images, the specific interval of the failure point can be accurately located along the cavity length Y, enabling intuitive and rapid diagnosis of the failure mode of the edge-emitting semiconductor laser chip.

[0106] In some embodiments, reference Figures 18 to 20 The failure analysis method for the side-emitting semiconductor laser chip further includes: placing the side-emitting semiconductor laser chip 320 on one side of the heat sink 310 along the first direction Z; using a support structure 300 to support the side of the heat sink 310 away from the side-emitting semiconductor laser chip 320; using a translation device to translate the support structure 300 along the cavity length direction Y, so that the semiconductor laser chip 320 is translated along the cavity length direction Y; during the translation of the semiconductor laser chip 320 along the cavity length direction Y, the beam emitted from the opening 140 is acquired by the image acquisition device 210 to obtain a test image.

[0107] The edge-emitting semiconductor laser chip 320 is placed on one side of the heat sink 310 along the first direction Z, and the light-emitting structure 110 is located on the side of the semiconductor substrate layer 100 opposite to the heat sink 310 along the first direction Z. The heat generated by the edge-emitting semiconductor laser chip 320 during operation is dissipated through the heat sink 310.

[0108] The image acquisition device 210 can be a CCD (Charge-Coupled Device) camera or a CMOS (Complementary Metal-Oxide-Semiconductor) camera. The optical axis of the image acquisition device 210 can be parallel to the first direction Z.

[0109] The image acquisition device 210 has a high resolution; for example, the resolution of the image acquisition device 210 is greater than or equal to 1000 PPI.

[0110] In some embodiments, an objective lens 200 and a filter may be disposed between the image acquisition device 210 and the edge-emitting semiconductor laser chip 320 to optimize the field of view, resolution, and signal-to-noise ratio. The filter may be located between the objective lens 200 and the edge-emitting semiconductor laser chip 320.

[0111] refer to Figure 18 and Figure 19 The image acquisition device 210 and the opening 140 have overlapping projections in the first direction Z, and the objective lens 200 and the opening 140 have overlapping projections in the first direction Z. (Reference) Figure 19The objective lens 200 and the openings 140 located on both sides of the ridge region have overlapping projections in the first direction Z.

[0112] In some embodiments, a preset current pulse or DC bias voltage is applied to the edge-emitting semiconductor laser chip 320 via a driving circuit, causing the active layer 112 of the edge-emitting semiconductor laser chip 320 to emit light. The image acquisition device 210 synchronously acquires test images of the edge-emitting semiconductor laser chip 320 and transmits them to a computer for image processing and analysis. For example, the computer obtains the failure points of the active layer 112 based on the test images.

[0113] To map the location of the dark area in the test image to specific coordinates on the physical structure of the side-emitting semiconductor laser chip 320, the translation device in this embodiment translates the support structure 300 along the cavity length direction Y, causing the side-emitting semiconductor laser chip 320 and the heat sink 310 to perform step translations along the cavity length direction Y, for example, performing micrometer-level precision step translations along the cavity length direction Y. By acquiring multiple test images before and after the translation and combining them with the known translation distance, the position coordinates of the failure point in the active layer 112 along the cavity length direction Y can be calculated based on the displacement of the dark area location in the test image. This method, combining displacement and image analysis, effectively achieves spatial localization of the failure point; the localization accuracy depends on the accuracy of the translation device and the image resolution.

[0114] Having accurately obtained the location information of the failure point in the edge-emitting semiconductor laser chip 320, the ridge region containing the failure point is cut to expose the failure point, which is then observed and analyzed under an electron microscope. Cutting the ridge region containing the failure point can be performed using a focused ion beam (FIB) process.

[0115] The translation device includes a first translation part 401 and a second translation part 402. The first translation part 401 is connected to the support structure 300, and the second translation part 402 is connected to the first translation part 401. The second translation part 402 can extend along a first direction Z, and the first translation part 401 can extend along a direction perpendicular to the first direction Z.

[0116] In summary, this invention, through its ingenious observation window design, overcomes the limitations of traditional edge-emitting semiconductor laser chips in terms of light emission obstruction, establishing a non-destructive, visualized electroluminescence failure analysis technique. The failure analysis process is simple, enabling rapid determination of whether a traditional edge-emitting semiconductor laser chip has failed, and more importantly, it visually reveals the distribution and morphology of failure points, providing crucial evidence for in-depth analysis of failure physical mechanisms. This failure analysis method can be widely applied in the research and development testing, production line screening, reliability assessment, and failure analysis of edge-emitting semiconductor laser chips, possessing significant practical value and promising prospects for widespread application. Failure physical mechanisms include cavity surface damage, internal defects, and uneven current distribution.

[0117] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for fabricating a side-emitting semiconductor laser chip, characterized in that, include: A light-emitting structure is formed on one side of a semiconductor substrate along a first direction. The light-emitting structure includes a first cladding layer, an active layer, and a second cladding layer arranged sequentially in the first direction away from the semiconductor substrate. The light-emitting structure includes a ridge region. A passivation layer is formed on the surface of the light-emitting structures on both sides of the ridge region in the slow axis direction away from the semiconductor substrate layer, and the passivation layer exposes the ridge region; Etch the portion of the light-emitting structure located on at least one side of the ridge region along the slow axis direction to form an opening that penetrates the second cladding and the active layer in the first direction; During the formation of the opening, a passivation layer is also etched, and the opening penetrates the passivation layer in the first direction; A front electrode is formed, the front electrode being located on the side of the ridge region away from the semiconductor substrate and connected to the ridge region, the front electrode exposing the opening; A back electrode is formed on the side of the semiconductor substrate layer opposite to the light-emitting structure; The light emitted from the active layer is reflected by the back electrode and then emitted from the opening.

2. The method for fabricating a side-emitting semiconductor laser chip according to claim 1, characterized in that, Also includes: Prior to forming the opening, a front electrode is formed on the side of the passivation layer and the ridge region opposite to the semiconductor substrate layer; In the process of forming the opening, the front electrode is also etched, and the opening also penetrates the front electrode in the first direction. The opening is located on one side of the ridge region in the slow axis direction and extends along the cavity length direction.

3. The method for fabricating a side-emitting semiconductor laser chip according to claim 1, characterized in that, The openings are located on both sides of the ridge region in the slow axis direction; the opening on one side of the ridge region extends along the length of the cavity; on the other side of the ridge region, multiple openings are spaced apart along the length of the cavity and extend along the slow axis direction. The method for fabricating a side-emitting semiconductor laser chip further includes: forming a front electrode, wherein the front electrode is located on the side of the passivation layer surrounding the opening that is away from the semiconductor substrate layer and on the side of the ridge region that is away from the semiconductor substrate layer.

4. The method for fabricating a side-emitting semiconductor laser chip according to claim 3, characterized in that, Also includes: Before forming the front electrode, a sacrificial layer is formed in the opening; After the front electrode is formed, the sacrificial layer is removed.

5. The method for fabricating a side-emitting semiconductor laser chip according to claim 1, characterized in that, The opening and the ridge region are spaced 10 to 40 micrometers apart in the slow axis direction.

6. The method for fabricating a side-emitting semiconductor laser chip according to claim 1, characterized in that, The opening has a dimension greater than or equal to 5 micrometers in the slow axis direction.

7. A side-emitting semiconductor laser chip, characterized in that, include: Semiconductor substrate layer; A light-emitting structure is located on one side of a semiconductor substrate layer along a first direction. The light-emitting structure includes a first cladding layer, an active layer, and a second cladding layer arranged sequentially in the first direction away from the semiconductor substrate layer. The light-emitting structure includes a ridge region. A passivation layer is located on the surface of the light-emitting structure on both sides of the ridge region in the slow axis direction, away from the semiconductor substrate layer. An opening is located on at least one side of the ridge region along the slow axis direction and penetrates the passivation layer, the second cladding layer, and the active layer in the first direction; A front electrode is located on the side of the ridge region opposite to the semiconductor substrate and connected to the ridge region, and the front electrode exposes the opening; The back electrode is located on the side of the semiconductor substrate layer opposite to the light-emitting structure. The light emitted from the active layer is reflected by the back electrode and then emitted from the opening.

8. The edge-emitting semiconductor laser chip according to claim 7, characterized in that, The front electrode is located on the side of the passivation layer and the ridge region that is away from the semiconductor substrate layer; The opening extends through the front electrode, passivation layer, second cladding layer and active layer in the first direction, and the opening is located on one side of the ridge region in the slow axis direction and extends along the cavity length direction.

9. The edge-emitting semiconductor laser chip according to claim 7, characterized in that, in, The opening penetrates the passivation layer, the second cladding layer, and the active layer in the first direction, and the opening is located on both sides of the ridge region in the slow axis direction; the opening located on one side of the ridge region extends along the cavity length direction; on the other side of the ridge region, multiple openings are arranged at intervals along the cavity length direction and the openings extend along the slow axis direction. The front electrode is located on the side of the passivation layer surrounding the opening that faces away from the semiconductor substrate, and the ridge region is located on the side of the ridge region that faces away from the semiconductor substrate.

10. The edge-emitting semiconductor laser chip according to claim 8, characterized in that, The front electrode includes a first electrode portion and a second electrode portion spaced apart. The first electrode portion is located on the side of the ridge region away from the semiconductor substrate layer along the first direction and extends between the ridge region and the opening, and on the side of the ridge region away from the opening along the slow axis direction. The second electrode portion is located on the side of the opening away from the ridge region along the slow axis direction. The first electrode portion and the second electrode portion extend along the cavity length direction.

11. The edge-emitting semiconductor laser chip according to claim 9, characterized in that, The front electrode includes a first electrode portion, a second electrode portion, and a third electrode portion. The first electrode portion, the third electrode portion, and the second electrode portion are arranged sequentially and connected in the slow axis direction. The first electrode portion is located on the side of the ridge region away from the semiconductor substrate layer along the first direction and extends between the ridge region and the opening extending along the slow axis direction. The third electrode portion is located between adjacent openings in the cavity length direction. The second electrode portion is located on the side of the opening extending along the slow axis direction away from the first electrode portion in the slow axis direction. The first electrode portion and the second electrode portion extend along the cavity length direction.

12. The edge-emitting semiconductor laser chip according to claim 7, characterized in that, The opening and the ridge region are spaced 10 to 40 micrometers apart in the slow axis direction.

13. The edge-emitting semiconductor laser chip according to claim 7, characterized in that, The opening has a dimension greater than or equal to 5 micrometers in the slow axis direction.

14. A failure analysis method for a side-emitting semiconductor laser chip as described in any one of claims 7 to 13, characterized in that, include: The image acquisition device is placed on the side of the opening that is away from the semiconductor substrate layer; A test voltage is applied to the front electrode and the back electrode to cause the edge-emitting semiconductor laser chip to emit light, wherein the light emitted by the active layer is reflected by the back electrode and then emitted from the opening; The test image is obtained by acquiring the light beam emitted from the opening through the image acquisition device; The failure point of the active layer in the ridge region is obtained based on the test image.

15. The failure analysis method for a side-emitting semiconductor laser chip according to claim 14, characterized in that, Also includes: The edge-emitting semiconductor laser chip is placed on one side of the heat sink along the first direction; A support structure is used to support the heat sink on the side away from the edge-emitting semiconductor laser chip; A translation device is used to translate the support structure along the cavity length, thereby translating the semiconductor laser chip along the cavity length. During the translation of the semiconductor laser chip along the cavity length, the image acquisition device acquires the beam emitted from the opening to obtain a test image.

Images