Pre-packaging module, preparation method of pre-packaging module, chip packaging structure and preparation method of chip packaging structure
By bonding the chip to a heat sink and flip-chip bonding it to an interposer in the chip packaging structure, the problems of interposer damage and warpage are solved, achieving efficient packaging and high yield, and reducing production costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING HUAFENG INTEGRATED ELECTRONICS CO LTD
- Filing Date
- 2025-12-30
- Publication Date
- 2026-05-26
AI Technical Summary
Existing chip packaging structures are prone to damage to the interposer layer during repeated thermo-pressing cycles, resulting in warping and uneven bonding due to the mismatch in thermal expansion coefficients between the chip and the interposer, which affects packaging efficiency and yield.
By using a pre-packaged module, the chip is bonded and fixed to one side of the heat sink, forming a whole flip-chip bonded to the interlayer, reducing the number of bonding steps. The chip thickness is adjusted by using the bending part of the heat sink and the adhesive layer to achieve bonding on the same horizontal plane. The alignment accuracy is improved by combining thermally conductive adhesive and alignment marks.
Reduce the probability of interposer damage, avoid warpage, improve packaging efficiency and yield, and reduce production costs.
Smart Images
Figure CN122094497A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip packaging technology, specifically to a pre-packaged module and its preparation method, and a chip packaging structure and its preparation method. Background Technology
[0002] With the development of technologies such as artificial intelligence (AI), high-performance computing (HPC), and 5G communication, the integration and power consumption of system-on-chips (SoCs) are constantly increasing. Correspondingly, the energy consumption and heat dissipation requirements of 2.5D packaging (silicon interposer / silicon bridge interconnect) and 3D packaging (TSV stacked interconnect) are becoming increasingly demanding. Therefore, current chip packaging structures generally include heat sinks. Existing packaging processes involve first bonding multiple chips to an interposer in batches using flip-chip technology, and then attaching the heat sink to the multiple chips and the interposer. There are several problems in the actual fabrication process. For example, the silicon interposer is easily damaged by thermal stress (such as microcracks) during multiple hot-press cycles of chip mounting. Also, due to the mismatch in the coefficient of thermal expansion (CTE) between the chip and the interposer material, stress can easily accumulate during multiple high-temperature processes, causing the interposer to warp. In addition, the chip thickness may vary, causing the surface of the chip away from the interposer to be on different planes. This will cause the following problems when the heat sink is attached to the chip with thermally conductive adhesive: the relatively thicker chip and the interposer corresponding to that chip location will be damaged due to excessive pressure, while the relatively thinner chip will have air gaps due to insufficient adhesion to the heat sink, resulting in a significant increase in local thermal resistance. Summary of the Invention
[0003] This application aims to address one of the technical problems in related technologies to a certain extent. To this end, this application provides a pre-packaged module and its fabrication method, as well as a chip packaging structure and its fabrication method.
[0004] To achieve the above objectives, this application adopts the following technical solution: a pre-packaged module for a chip packaging structure, the pre-packaged module including a heat sink and a chip, the chip being bonded and fixed to one side surface of the heat sink to form a structure that can be integrally flip-chip mounted in the chip packaging structure.
[0005] The application of this application has the following beneficial effects: the pre-packaged module can be flip-chip bonded to the interposer in one go, reducing the number of bonding operations between the chip and the heat sink and the interposer, thus reducing the probability of damage to the interposer and preventing warping. Furthermore, compared to the prior art's method of merging and bonding the heat sink to the chip cover, the chip bonding and fixing operation in this application is easier to align and maintains relative stability during the thermal adhesive curing process. This significantly improves packaging efficiency and yield, and reduces production costs.
[0006] Optionally, the heat dissipation cover includes a cover plate portion and a bent portion formed by extending from the edge of the cover plate portion. The surface of the cover plate portion located inside the bent portion is the inner side surface of the cover plate portion. The chip is bonded and fixed to the inner side surface of the cover plate portion, and the end face of the bent portion is used to bond and fix to the interlayer.
[0007] Optionally, there may be multiple chips.
[0008] Optionally, the plurality of said chips may include at least two different types of heterogeneous chips.
[0009] Optionally, the arrangement of the multiple chips on the heat sink includes a straight line arrangement, a grid arrangement, and a radial arrangement from the center outwards.
[0010] Optionally, the multiple chips have different thicknesses, and each chip is bonded to the heat sink by an adhesive layer; the multiple adhesive layers are configured with different thicknesses so that the surfaces of the multiple chips facing away from the heat sink are on the same horizontal plane; or, an adhesive groove is provided on one side surface of the heat sink, and the multiple chips are selectively bonded to the bottom wall of the adhesive groove so that the surfaces of the multiple chips facing away from the heat sink are on the same horizontal plane.
[0011] Optionally, the surface of the heat sink is provided with alignment marks for assisting in positioning the chip.
[0012] Optionally, the heat sink is made of metal or metal alloy or glass.
[0013] In addition, this application also provides a chip packaging structure, including a substrate, an interposer disposed on the substrate, and a pre-packaged module as described in any of the above technical solutions, wherein the pre-packaged module is flip-chip mounted on the interposer, and the chip in the pre-packaged module is electrically connected to the interposer.
[0014] The chip packaging structure provided in this application is similar to the reasoning process of the beneficial effects of the aforementioned pre-packaged module, and will not be repeated here.
[0015] Optionally, the interposer is a silicon interposer.
[0016] Furthermore, this application also provides a method for preparing a pre-packaged module, the method comprising:
[0017] Provide a heat dissipation cover;
[0018] Provide one or more chips;
[0019] The chip is bonded and fixed to one side surface of the heat sink to obtain the pre-packaged module, which is formed as an integral unit.
[0020] The preparation method of the pre-packaged module provided in this application is similar to the reasoning process of the beneficial effects of the aforementioned pre-packaged module, and will not be repeated here.
[0021] Optionally, the heat dissipation cover includes a cover plate portion and a bent portion formed by extending from the edge of the cover plate portion, wherein the surface of the cover plate portion located inside the bent portion is the inner side surface of the cover plate portion;
[0022] The step of bonding and fixing the chip to one side surface of the heat sink includes: bonding and fixing the chip to the inner side surface of the cover plate.
[0023] Furthermore, this application also provides a method for fabricating a chip packaging structure, the method comprising:
[0024] Provide a pre-packaged module as described in any of the above technical solutions;
[0025] A first substrate with a first interposer layer is provided, and the pre-packaged module is mounted onto the first interposer layer in one step using a flip-chip process, thereby electrically connecting the chip to the first interposer layer; or, a second interposer layer and a second substrate are provided, and the pre-packaged module is mounted onto the second interposer layer in one step using a flip-chip process, thereby electrically connecting the chip to the second interposer layer, to obtain an intermediate product, which is then bonded to the second substrate.
[0026] The method for preparing the chip packaging structure provided in this application is similar to the reasoning process of the beneficial effects of the aforementioned pre-packaged module, and will not be repeated here.
[0027] These features and advantages of this application will be disclosed in detail in the following specific embodiments and accompanying drawings. The best embodiments or means of this application will be shown in detail in conjunction with the accompanying drawings, but are not intended to limit the technical solutions of this application. In addition, each of these features, elements and components appearing in the following text and drawings is multiple and is labeled with different symbols or numbers for convenience, but all represent parts with the same or similar structure or function. Attached Figure Description
[0028] The following description, in conjunction with the accompanying drawings, further illustrates this application:
[0029] Figure 1 A top view of a pre-packaged module provided in Embodiment 1 of this application;
[0030] Figure 2 This is a cross-sectional view of the pre-packaged module in Embodiment 1;
[0031] Figure 3 This is a schematic diagram of the pre-packaged module flip-chip mounted on the interposer layer in Embodiment 1;
[0032] Figure 4 This is a schematic diagram of the chip packaging structure shown in Embodiment 1.
[0033] Figure 5 This is a cross-sectional view of a pre-packaged module provided in Embodiment 2.
[0034] Among them, 1. heat dissipation cover; 10. cover plate portion; 100. adhesive groove; 11. bending portion; 2. first chip; 20. first adhesive layer; 3. second chip; 30. second adhesive layer; 4. interlayer; 40. interlayer adhesive layer; 5. substrate. Detailed Implementation
[0035] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described are intended to explain this application and should not be construed as limiting it.
[0036] The terms "an embodiment," "example," or "example" used in this specification refer to a particular feature, structure, or characteristic described in connection with the embodiment itself that may be included in at least one embodiment disclosed in this application. The phrase "in an embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment.
[0037] In the description of this application, it should be understood that the terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In the description of this application, "a plurality of" means two or more, unless otherwise precisely specified.
[0038] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected," "linked," and "connected" should be interpreted broadly. For example, they can refer to a fixed connection, a connection through an intermediary, or a connection within two elements or an interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0039] Example 1: As Figure 1 and Figure 2As shown, this embodiment provides a pre-packaged module for chip packaging structures. The pre-packaged module includes a heat sink 1 and a chip, wherein the chip is bonded and fixed to one side surface of the heat sink 1, combined with… Figure 3 As shown, this forms a structure that can be flip-chip mounted as a whole into the intermediary layer 4 of the chip package structure.
[0040] The pre-packaged module provided in this embodiment can be flip-chip bonded to the interposer 4 in a single step, reducing the number of bonding operations between the chip and the heat sink 1 and the interposer 4. This reduces the probability of damage to the interposer 4 and prevents warping. Furthermore, compared to the prior art method of bonding the heat sink 1 to the chip cover, the chip bonding and fixing operation in this application is easier to align and maintains relative stability during the curing process of the thermally conductive adhesive. This significantly improves packaging efficiency and yield, and reduces production costs.
[0041] It should be noted that this embodiment shows a pre-packaged module with two chips. In other optional embodiments, the pre-packaged module may contain one, three, or more chips. Even with only one chip, the pre-packaged module can reduce the number of bonding operations relative to the interposer layer 4. Furthermore, for ease of description and distinction, the two chips in this embodiment are respectively named first chip 2 and second chip 3.
[0042] Furthermore, in this embodiment, the first chip 2 and the second chip 3 are heterogeneous chips of different types. Specifically, the first chip 2 is an HBM chip, and the second chip 3 is a CPU chip. In other optional embodiments, they can also be GPU chips or other chips. This design can meet the high-performance integration requirements of AI, HPC and other applications for different functional chips. At the same time, it is easy to achieve tight interconnection of computing, storage and other units, reduce latency and improve bandwidth.
[0043] The heat sink 1 in this embodiment includes a cover plate portion 10 and a bent portion 11 extending from the edge of the cover plate portion 10. The surface of the cover plate portion 10 located inside the bent portion 11 is the inner side surface of the cover plate portion 10. The chip is bonded and fixed to the inner side surface of the cover plate portion 10, and the end face of the bent portion 11 is used for bonding and fixing to the interposer layer 4. In this embodiment, the chip is bonded and fixed to the heat sink 1 by an adhesive layer. For ease of description and distinction, the adhesive layer corresponding to the first chip 2 is named the first adhesive layer 20, and the adhesive layer corresponding to the second chip 3 is named the second adhesive layer 30. The adhesive layer is a thermally conductive adhesive. It should be noted that... Figure 2 and Figure 3The first adhesive layer 20 and the second adhesive layer 30 shown are only for illustrating the presence of adhesive layers between the first chip 2, the second chip 3, and the heat sink 1, and do not represent that the first adhesive layer 20 and the second adhesive layer 30 and the first chip 2 and the second chip 3 achieve the thickness ratio shown in the figure. In reality, the thickness of the first adhesive layer 20 and the second adhesive layer 30 is between 15 and 80 μm.
[0044] In this embodiment, the first chip 2 and the second chip 3 have different thicknesses. To address the problem in the prior art where the chip surfaces are not coplanar due to the different thicknesses of the chips, this embodiment designs the first adhesive layer 20 and the second adhesive layer 30 to have different thicknesses, ensuring that the surfaces of the first chip 2 and the second chip 3 facing away from the heat sink 1 are on the same horizontal plane. Specifically, the thickness of the first chip 2 is smaller than that of the second chip 3, and correspondingly, the thickness of the first adhesive layer 20 is designed to be greater than that of the second adhesive layer 30. With this structural design, when the chips are bonded to the cover plate 10, since each chip is bonded sequentially to the cover plate 10, there will be no problem of excessive or insufficient pressure on any particular chip. When the pre-packaged module is flip-chip mounted onto the interposer layer 4, since the surfaces of the first chip 2 and the second chip 3 facing away from the heat sink 1 are on the same horizontal plane, there will be no problem of uneven local stress when the first chip 2 and the second chip 3 are flip-chip mounted onto the interposer layer 4. It is easy to understand that the above solution is applicable to situations where the thickness of the first chip 2 and the thickness of the second chip 3 are not significantly different. Since the thickness of the first adhesive layer 20 and the second adhesive layer 30 cannot be too large, when the thickness of the first chip 2 and the thickness of the second chip 3 are significantly different, it is not possible to make the first chip 2 and the second chip 3 coplanar by designing the difference in thickness of the first adhesive layer 20 and the second adhesive layer 30.
[0045] It should also be noted that the heat sink 1 in this embodiment has a bent portion 11. Preferably, the end face of the bent portion 11 can be set to be flush with the surfaces of the first chip 2 and the second chip 3. This facilitates the bonding of the bent portion 11 to the intermediary layer 4 through the intermediary adhesive layer 40 during the flip-chip bonding process of the first chip 2 and the second chip 3 with the intermediary layer 4. The intermediary adhesive layer 40 is also a thermally conductive adhesive. In other optional embodiments, the heat sink 1 may not have a bent portion 11, that is, the heat sink 1 is roughly flat. In this case, the heat sink 1 can be bonded and fixed to the intermediary layer 4 by applying a thicker layer of thermally conductive adhesive to the outer edge. Generally, the thermally conductive adhesive used in the intermediary adhesive layer 40 is a highly viscous adhesive, such as SE4450 adhesive. The thermally conductive adhesive used in the first adhesive layer 20 and the second adhesive layer 30 is generally a TIM adhesive with excellent thermal conductivity.
[0046] In this embodiment, the heat sink 1 is made of metal. For example, the heat sink 1 can be made of copper, which has a thermal conductivity of about 400 W / m·K, excellent thermal conductivity, and good strength. The heat sink 1 can also be made of aluminum, which has the advantages of being lightweight, low-cost, and strong, with a thermal conductivity generally between 160-220 W / m·K. In other optional embodiments, the heat sink 1 can also be made of a metal alloy, such as a copper alloy or an aluminum alloy, or it can be made of glass. Compared to the prior art method of first bonding the chip to the intermediary layer, bonding the first chip 2 and the second chip 3 in this embodiment to one side surface of the heat sink 1, which has higher flatness and better rigidity, makes alignment easier and makes it easier to ensure the stability of the first chip 2 and the second chip 3 relative to the heat sink 1 after bonding, reducing the probability of slight displacement during the curing process of the thermally conductive adhesive.
[0047] In this embodiment, the first chip 2 and the second chip 3 are arranged in a straight line. In other optional embodiments, if the number of chips is larger, the arrangement can also be a grid pattern or a radial arrangement from the center outwards. Of course, a larger number of chips can also be arranged in a straight line. Specifically, the optimal layout can be selected based on chip size, power consumption, and interconnection requirements to optimize heat distribution and signal paths within the module.
[0048] Furthermore, in this embodiment, alignment marks for assisting in chip positioning are also provided on the surface of the heat sink 1. These alignment marks can be continuous or discontinuous etched lines, or color-coded area markings, etc. Using these alignment marks reduces the difficulty of alignment and improves alignment accuracy during the bonding process, thereby ensuring the positional accuracy of the chip on the heat sink 1 and providing a good foundation for the subsequent high-precision flip-chip bonding of the pre-packaged module and the interposer layer 4.
[0049] Combination Figure 2 , Figure 3 and Figure 4 As shown, the method for preparing the pre-packaged module provided in this embodiment includes the following steps:
[0050] First, a heat dissipation cover 1 is provided; specifically, in this embodiment, the heat dissipation cover 1 includes a cover plate portion 10 and a bent portion 11 formed by extending from the edge of the cover plate portion 10, and the surface of the cover plate portion 10 located inside the bent portion 11 is the inner side surface of the cover plate portion 10.
[0051] Secondly, two chips are provided, namely chip 2 and chip 3;
[0052] Finally, the chip is bonded and fixed to one side surface of the heat sink 1 to obtain a pre-packaged module forming an integral unit; specifically in this embodiment, the first chip 2 and the second chip 3 are precisely bonded to the designated positions on the inner side of the cover plate 10 according to the alignment marks using thermally conductive adhesive.
[0053] Furthermore, in combination Figure 4 As shown, the pre-packaged module provided in this embodiment can also be applied to a chip packaging structure, which includes a substrate 5, an interposer 4 disposed on the substrate 5, and the pre-packaged module provided in this embodiment. The pre-packaged module is flip-chip mounted on the interposer 4, and the chip in the pre-packaged module is electrically connected to the interposer 4. Specifically, the interposer 4 in this embodiment is a silicon interposer 4.
[0054] The fabrication method for the above-mentioned chip packaging structure is described below:
[0055] First, a pre-packaged module is provided.
[0056] Secondly, a substrate 5 having an interposer layer 4 is provided; for ease of distinction from the following description, the substrate 5 having the interposer layer 4 is referred to as the first substrate 5, and the interposer layer 4 therein is referred to as the first interposer layer 4.
[0057] Finally, the pre-packaged module is mounted onto the first interposer 4 in one step using a flip-chip process, thereby electrically connecting the chip to the first interposer 4.
[0058] Alternatively, in the second step described above, an interposer 4 and a substrate 5 are provided respectively. For ease of distinction, they are referred to as the second interposer 4 and the second substrate 5. The pre-packaged module is then mounted onto the second interposer 4 in one step using a flip-chip process, and the chip is electrically connected to the second interposer 4 (electrical connection is achieved through microbumps), resulting in an intermediate product. Finally, the intermediate product is bonded to the second substrate 5.
[0059] The fabrication method of the chip packaging structure described above can significantly reduce damage and warpage of the interposer layer 4, greatly improving the yield. It can also significantly improve packaging efficiency and reduce production costs.
[0060] Example 2: Figure 5 As shown, this embodiment also provides a pre-packaged module. The difference between this embodiment and Embodiment 1 is that the heat sink 1 in this embodiment has an adhesive groove 100 on one side surface. Multiple chips are selectively attached to the bottom wall of the adhesive groove 100 so that the side surfaces of the multiple chips facing away from the heat sink 1 are on the same horizontal plane. That is, this embodiment solves the problem of non-coplanar surfaces of multiple chips by providing an adhesive groove 100 on the heat sink 1.
[0061] Specifically, in this embodiment, the thicker second chip 3 is provided with an adhesive groove 100, while the first chip 2 is not provided with a corresponding adhesive groove 100. In this way, part of the second chip 3 can be embedded in the adhesive groove 100, thereby making the surfaces of the first chip 2 and the second chip 3 facing away from the heat sink 1 at the same level without increasing the thickness of the first adhesive layer 20.
[0062] In other alternative embodiments, corresponding bonding grooves 100 can be provided for the first chip 2 and the second chip 3 respectively, that is, two bonding grooves 100 with different thicknesses can be provided. When there are more chips and the thickness difference is more obvious, more bonding grooves 100 can be provided. The different depths of the bonding grooves 100 can also be matched with the different thicknesses of the adhesive layer to achieve coplanarity of multiple chips.
[0063] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Those skilled in the art should understand that this application includes, but is not limited to, the contents described in the accompanying drawings and the specific embodiments above. Any modifications that do not depart from the functional and structural principles of this application will be included within the scope of the claims.
Claims
1. A pre-packaged module for chip packaging structure, characterized in that, The pre-packaged module includes a heat sink and a chip. The chip is bonded and fixed to one side surface of the heat sink to form a structure that can be flip-chip mounted as a whole in the interlayer of the chip packaging structure.
2. The pre-packaged module as described in claim 1, characterized in that, The heat dissipation cover includes a cover plate portion and a bent portion formed by extending from the edge of the cover plate portion. The surface of the cover plate portion located inside the bent portion is the inner side surface of the cover plate portion. The chip is bonded and fixed to the inner side surface of the cover plate portion, and the end face of the bent portion is used to bond and fix to the interlayer.
3. The pre-packaged module as described in claim 1 or 2, characterized in that, There are multiple chips.
4. The pre-packaged module as described in claim 3, characterized in that, The plurality of said chips include at least two different types of heterogeneous chips.
5. The pre-packaged module as described in claim 3, characterized in that, The arrangement of the chips on the heat sink includes a straight line arrangement, a grid arrangement, and a radial arrangement from the center outwards.
6. The pre-packaged module as described in claim 3, characterized in that, The chips have different thicknesses, and each chip is bonded and fixed to the heat sink by an adhesive layer; The multiple adhesive layers are configured with different thicknesses so that the surfaces of the multiple chips facing away from the heat sink are on the same horizontal plane; Alternatively, one side surface of the heat sink is provided with an adhesive groove adapted to each chip, and the multiple adhesive grooves are configured with different depth dimensions so that the side surfaces of the multiple chips facing away from the heat sink are located on the same horizontal plane.
7. The pre-packaged module as described in claim 1 or 2, characterized in that, The surface of the heat sink is provided with alignment marks to assist in positioning the chip.
8. The pre-packaged module as described in claim 1 or 2, characterized in that, The heat sink is made of metal or metal alloy or glass.
9. A chip packaging structure, characterized in that, The device includes a substrate, an interposer disposed on the substrate, and a pre-packaged module as described in any one of claims 1 to 8, wherein the pre-packaged module is flip-chip mounted on the interposer, and the chip in the pre-packaged module is electrically connected to the interposer.
10. The chip packaging structure as described in claim 9, characterized in that, The intermediate layer is a silicon intermediate layer.
11. A method for preparing a pre-packaged module, characterized in that, The preparation method includes: Provide a heat dissipation cover; Provide one or more chips; The chip is bonded and fixed to one side surface of the heat sink to obtain the pre-packaged module, which is formed as an integral unit.
12. The preparation method according to claim 11, characterized in that, The heat dissipation cover includes a cover plate portion and a bent portion formed by extending from the edge of the cover plate portion, wherein the surface of the cover plate portion located inside the bent portion is the inner side surface of the cover plate portion; The step of bonding and fixing the chip to one side surface of the heat sink includes bonding and fixing the chip to the inner side surface of the cover plate.
13. A method for fabricating a chip packaging structure, characterized in that, The preparation method includes: Provide a pre-packaged module as described in any one of claims 1 to 8; A first substrate with a first interposer layer is provided, and the pre-packaged module is mounted onto the first interposer layer in one step using a flip-chip process, thereby electrically connecting the chip to the first interposer layer; or, a second interposer layer and a second substrate are provided, and the pre-packaged module is mounted onto the second interposer layer in one step using a flip-chip process, thereby electrically connecting the chip to the second interposer layer, to obtain an intermediate product, which is then bonded to the second substrate.