A novel POP packaging structure that improves heat dissipation and reduces warpage

Abstract

This invention discloses a novel POP (Position-on-Pack) packaging structure that improves heat dissipation and reduces warpage. The structure includes: a multilayer substrate, comprising at least a bottom substrate and a top substrate; a chip; a ceramic structural layer embedded within the bottom substrate, wherein the ceramic structural layer has through-holes that allow electrical conductivity between the upper and lower layers; and an indium wafer structural layer, the lower surface of which is mounted to the upper surface of the chip, and the upper surface of which is soldered to the lower surface of the top substrate. This invention improves warpage issues caused by thermal stress during packaging by adding a ceramic structural layer inside the bottom substrate. The through-holes in the ceramic structural layer create electrical conductivity between the upper and lower layers, ensuring that the ceramic structural layer does not affect the conductivity of the bottom substrate. Furthermore, by mounting an indium wafer on the upper surface of the chip in the bottom packaging structure and adding a soldering surface to the lower surface of the top substrate for soldering to the indium wafer, the overall POP packaging achieves heat dissipation through the indium wafer's connection to the external environment.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, particularly to the field of packaging material research and development, and specifically to a novel POP packaging structure that improves heat dissipation and reduces warpage. Background Technology

[0002] Traditional point-of-place (POP) packaging structures place high demands on the compatibility of the solder balls, package, and PCB pads in the underlying package structure. Even minor warpage can lead to poor soldering during reflow soldering, resulting in open circuits or cold solder joints. Therefore, controlling the warpage of the underlying package structure is crucial for improving package yield. Currently, warpage plays a critical role in determining whether advanced packages can be successfully assembled and meet long-term reliability goals. New advancements, such as packaging compounds with improved thermal performance, advanced modeling techniques, and innovative architectures involving two packaging steps, are making warpage control more stringent and providing greater flexibility for optimizing robust multi-chip systems. Warpage is an inevitable consequence of the mismatch in thermal expansion coefficients between silicon chips, packaging compounds, copper, polyimide, and other materials. It changes throughout the assembly process and can lead to cracking or delamination failures.

[0003] In traditional POP (Package Opening) packaging, the bottom layer chip is a high-heat source. Two chips are tightly stacked, leading to heat accumulation. The heat conduction efficiency is primarily achieved through the molding compound in the middle. However, overheating can also affect chip performance and lifespan. Due to mismatched thermal expansion coefficients, long-term thermal fatigue can lead to solder joint failure. Heat dissipation refers to the process of transferring heat from one object to another. The principle of chip packaging heat dissipation is to transfer the heat generated inside the chip to the outside and release it into the environment. There are three main methods of chip packaging heat dissipation: conduction, convection, and radiation. Conduction refers to the process of transferring heat to another object through the thermal conduction of a solid material. In chip packaging heat dissipation, thermally conductive materials, such as silicone or metals with high thermal conductivity, are added between the chip and the heat sink to improve heat conduction efficiency. Convection refers to the process of transferring heat from one object to another through the flow of a fluid. In chip packaging heat dissipation, increasing airflow around the chip accelerates heat transfer. Radiation refers to the process of an object emitting electromagnetic waves or light into the surrounding space. In chip packaging heat dissipation, heat dissipation efficiency is improved by increasing the surface area of ​​the heat sink and using radioactive materials. The heat sink at the bottom of the chip is directly connected to the chip's bare pads. Heat is transferred to the PCB board and heat sink through the package's metal pins or the bottom heat sink, and then exchanges heat with the air or an external cooling system. This path has low thermal resistance and high thermal conductivity and dissipation efficiency. The plastic package at the top of the chip has poor thermal conductivity, and heat must diffuse through the chip's internal junction Tj → package shell Tc → plastic surface. Due to the high thermal resistance of the plastic, heat tends to accumulate at the top, resulting in a significantly higher temperature than at the bottom.

[0004] This invention offers higher thermal conductivity and better resistance to product warpage, achieving greater heat dissipation efficiency on the chip substrate while mitigating warpage issues caused by significant CET differences between the chip and substrate, as well as warpage between packages. Effective heat dissipation is crucial for ensuring stable chip operation, extending lifespan, and improving overall system performance. With technological advancements, chip performance continues to improve; however, high-performance chips also generate higher power consumption and heat, placing greater demands on heat dissipation technologies. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a novel POP packaging structure that improves heat dissipation and reduces warpage. This invention is applicable to achieving higher heat dissipation efficiency on the chip substrate while combating warpage issues caused by significant differences in CET between the chip and substrate, as well as warpage between packages.

[0006] To achieve the above objectives, the first technical solution adopted by the present invention is: a novel POP packaging structure that improves heat dissipation and reduces warpage, comprising: a multilayer substrate, including at least a bottom substrate and a top substrate; a chip; a ceramic structure layer embedded inside the bottom substrate, wherein the ceramic structure layer is provided with through holes to allow communication between the upper and lower layers of the ceramic structure layer; and an indium wafer structure layer, wherein the lower surface of the indium wafer is attached to the upper surface of the chip, and the upper surface of the indium wafer is soldered to the lower surface of the top substrate.

[0007] Optionally, the horizontal area of ​​the ceramic structure layer matches the horizontal area of ​​the bottom substrate, and the horizontal area of ​​the ceramic structure layer is not less than a first predetermined area size.

[0008] Optionally, the through holes in the ceramic structural layer are fabricated using laser drilling or mechanical drilling.

[0009] Optionally, the ceramic structural layer includes a ceramic plate, the horizontal area of ​​which is not less than the area of ​​the bottom substrate, and the upper and lower surfaces of the ceramic plate are respectively subjected to a roughening process.

[0010] Optionally, the ceramic structure layer further includes a core material layer, wherein the upper and lower surfaces of the ceramic plate are respectively adhered with the core material layer, the horizontal area of ​​the core material layer is not less than the horizontal area of ​​the ceramic plate, and the core material layer is used to enable electrical conduction between the upper and lower layers of the ceramic structure layer through the through hole.

[0011] Optionally, the indium wafer structure layer includes an indium wafer body, wherein the horizontal area of ​​the indium wafer body is the same as the upper surface area of ​​the chip.

[0012] Optionally, the indium sheet structure layer further includes: indium sheet branches, which are disposed around the indium sheet body and extend to the edge of the package structure.

[0013] Optionally, the thickness of the indium sheet branch is less than the thickness of the indium sheet body.

[0014] Optionally, it further includes: a first solder ball, the first solder ball being soldered between the bottom substrate and the top substrate, wherein the closest distance between the indium foil branch and the first solder ball is not less than a first preset distance.

[0015] Optionally, the top substrate further includes a welding surface, the structure of which matches the size and shape of the indium sheet structure layer.

[0016] The beneficial effects of this invention are: This invention improves warpage problems such as warping caused by thermal stress during packaging by adding a ceramic structure layer inside the bottom substrate. Through holes are set in the ceramic structure layer to form a connection between the upper and lower layers, so that the ceramic structure layer does not affect the conductivity of the bottom substrate. During the welding process between the bottom structures, the warpage can be controlled by adding a ceramic structure inside the substrate.

[0017] Meanwhile, this invention achieves heat dissipation of the package by mounting an indium sheet on the upper surface of the bottom packaging structure chip and adding a welding surface on the lower surface of the top substrate to weld it to the indium sheet. The overall POP package dissipates heat through the indium sheet and the outside environment. Attached Figure Description

[0018] Figure 1 This is a side view of the novel POP packaging structure that improves heat dissipation and reduces warpage, as per the present invention. Figure 2 This is a schematic diagram of the structure of the underlying substrate with an added ceramic structure layer according to the present invention; Figure 3 This is a schematic diagram of the indium sheet structure layer of the present invention; Figure 4 This is a schematic diagram of the overall packaging structure of the present invention; Figure 5 This is a first schematic diagram of the conventional overall packaging structure of the present invention; Figure 6 This is a second schematic diagram of the conventional overall packaging structure of the present invention; Figure 7 This is the third schematic diagram of the conventional overall packaging structure of the present invention.

[0019] Reference numerals: 1. Bottom substrate; 11. Metal layer; 12. PP layer; 13. SR layer; 2. Ceramic structure layer; 21. Ceramic plate; 22. Core material layer; 23. Through hole; 3. Chip; 4. Top substrate; 5. Indium wafer structure layer; 51. Indium wafer body; 52. Indium wafer branch; 6. First solder ball; 7. Second solder ball; 8. Third solder ball. Detailed Implementation

[0020] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0021] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0022] This invention provides a novel POP packaging structure that improves heat dissipation and reduces warpage. Warpage has become a major problem, partly due to the increasing size of chiplets, while the process windows for chiplets, redistribution layers (RDLs), substrates, and bumps of various sizes are very stringent. The relative expansion and contraction characteristics of adjacent materials depend on the difference in their CTE (Coefficient of Expansion / Temperature); CTE defines the dimensional change in ppm / °C per degree Celsius change in temperature. Chips are typically relatively large, with many I / Os, often copper pillars. Due to the very small pitch, even placing a single die on the substrate can be a significant challenge. Therefore, controlling warpage and flatness is crucial for these components. Throughout the reflow soldering process, the gap between the copper pillars and the contacts on the circuit board needs to be bridged to maintain flatness and prevent warpage. Warpage can be upward, curved at the edges, or downward, depending on the relative CTE of the materials in the stack.

[0023] In one specific embodiment of this application, the novel packaging structure includes: a multilayer substrate, comprising at least a bottom substrate 1 and a top substrate 4; a chip 3; the chip 3 is soldered onto the bottom substrate 1; a ceramic structure layer 2, embedded within the bottom substrate 1, the ceramic structure layer 2 having through holes 23 to allow communication between the upper and lower layers of the ceramic structure layer 2; and a Core+PP+ceramic plate 21+PP+Core structure, which improves warpage problems such as warpage caused by thermal stress during the packaging process.

[0024] Increased semiconductor integration means more work needs to be done in less space, generating more heat that needs to be dissipated. Managing the heat dissipation of advanced node Chip 3 and multi-chip 3 components is critical to their functionality and lifespan. While attention has largely focused on improving power efficiency to reduce power consumption growth rates, this alone is insufficient. Various technologies are needed to help move heat upwards, downwards, and outwards. The energy required for circuit operation comes from power pins, but not all energy is converted into work. Some energy is wasted as heat and must be removed from its source and released into the environment. Successful designs must balance dissipation rate and energy efficiency. But beyond power, the area of ​​heat sources within Chip 3 must also be considered. Smaller areas result in higher power density and a greater need for improved cooling strategies. Heat is primarily generated in the active silicon layer. From there, heat moves upwards, meaning in flip-chip 3 packages, heat can pass through the bulk silicon layer to the back of the package and eventually exit. Heat can also move downwards through various metal connections on the PCB, and in some cases, even laterally. The specific direction of movement depends on the application. Instead of having the entire package dissipate enough heat to handle all the hot spots, a heat sink is used to distribute the heat evenly within the package. Traditional metal heat sinks are located inside the package. This can be a separate metal block or a metal casing thermally connected to the chip.

[0025] In one specific embodiment of this application, the novel packaging structure further includes: an indium sheet structure layer 5, the lower surface of which is mounted to the upper surface of the chip 3, and the upper surface of which is soldered to the lower surface of the top substrate 4. Compared to traditional silicone grease, metal materials exhibit superior heat dissipation performance. Indium sheet, as a highly thermally conductive metal material, is often considered a replacement for traditional thermal interface adhesives in large-size packaged products. The main function of TIM adhesive is to reduce the thermal resistance between the heat source and the heat sink, thereby improving heat conduction efficiency. Typically, the thermal conductivity of TIM adhesive is approximately 3.8 W / (m·K), while the thermal conductivity of indium sheet is as high as 86 W / (m·K), making it a potentially ideal choice for efficient thermal management. The unique advantage of indium sheet lies in its ability to tightly adhere to the contact surface between the heat-generating element and the heat sink, effectively reducing thermal resistance and improving overall heat dissipation efficiency. Furthermore, the ease of integration of indium sheet in automated manufacturing processes ensures its consistency and reliability in large-scale production.

[0026] In one specific embodiment of this application, the horizontal area of ​​the ceramic structure layer 2 matches the horizontal area of ​​the bottom substrate 1, and the horizontal area of ​​the ceramic structure layer 2 is not less than the first predetermined area size, ensuring that the ceramic structure layer 2 can improve the warping deformation problem caused by thermal stress during the packaging process of the entire bottom substrate 1.

[0027] In one specific embodiment of this application, through-holes 23 are fabricated in the ceramic structural layer 2 using laser drilling or mechanical drilling. These through-holes 23 allow for electrical conductivity between the upper and lower layers of the ceramic structural layer 2, preventing any impact on the conductivity of the underlying substrate 1. In the drilling process of PCB manufacturing, laser drilling machines and mechanical drilling machines are two mainstream types of equipment, each supporting different production needs due to their distinct technical characteristics. From micro-hole processing to mass production, from cost control to precision requirements, both technologies have their advantages and disadvantages; choosing the appropriate drilling method directly affects the quality, efficiency, and manufacturing cost of the PCB. Laser drilling machines achieve drilling by instantly melting or vaporizing the substrate with a high-energy laser beam, and their core advantage lies in their precision processing capabilities. For micro-hole processing with a diameter ≤0.1mm, the precision of laser drilling can reach ±3μm, far exceeding the ±10μm of mechanical drilling, making it particularly suitable for the manufacture of high-density PCBs such as HDI boards and IC substrates. Laser drilling eliminates the need for physical contact with the substrate, avoiding the tool wear issues associated with mechanical drilling. For easily deformable materials like flexible PCBs, it reduces substrate damage caused by mechanical stress. For example, after laser drilling was applied to a flexible PCB, the substrate deformation rate decreased from 1.5% to 0.3%. However, laser drilling also has significant limitations: processing efficiency decreases as the hole diameter increases. When the hole diameter exceeds 0.3mm, the laser drilling speed is only 1 / 3 to 1 / 5 of that of mechanical drilling, making it unsuitable for large-diameter mass production. Furthermore, the high temperature of the laser can create a heat-affected zone (HAZ) on the hole wall, which, if not properly controlled, can lead to substrate carbonization. For instance, after laser drilling, a HAZ exceeding 5μm on an FR-4 substrate resulted in voids in the subsequent copper plating process. Initial equipment investment is high; a high-precision UV laser drilling machine costs approximately 3-5 times more than a mechanical drilling machine, and its high energy consumption leads to high long-term operating costs. Mechanical drilling machines, using high-speed rotating carbide or diamond drill bits to cut the substrate, demonstrate significant advantages in processing medium to large-diameter holes. The main drawbacks of mechanical drilling lie in micro-hole processing and material adaptability: the minimum drill diameter is 0.1mm, and there is a risk of tool breakage during processing. When the hole diameter is ≤0.15mm, the yield of mechanical drilling is usually below 85%. For high-hardness substrates such as ceramic-filled substrates, the drill wear rate is accelerated, requiring replacement of the drill every 1000 holes processed, leading to increased maintenance costs. Mechanical stress may cause warping of thin substrates. In one wearable device PCB, improper pressure control during mechanical drilling resulted in a substrate warping of 0.5%, affecting the accuracy of subsequent component placement. Furthermore, the hole position accuracy of mechanical drilling is affected by the table movement error, and the cumulative error may exceed 15μm in long board processing. In terms of key technical indicators, the two differ significantly: laser drilling can achieve a minimum hole diameter of 0.02mm, suitable for ultra-precision applications such as semiconductor packaging substrates; mechanical drilling has a cost advantage when the hole diameter is >0.2mm, with the processing cost per hole being only 1 / 10 to 1 / 20 of that of laser drilling.In terms of material adaptability, laser drilling has good processing results on materials such as FR-4 and PI, and is especially suitable for difficult-to-machine high-frequency materials such as polytetrafluoroethylene; mechanical drilling performs stably on ordinary FR-4 substrates, but it is more difficult to process flexible and high-hardness materials. In terms of hole shape control, laser drilling can process irregularly shaped holes, while mechanical drilling can only process circular holes.

[0028] In one specific embodiment of this application, the ceramic structural layer 2 includes a ceramic plate 21, the horizontal area of ​​which is not less than the area of ​​the bottom substrate 1, and the upper and lower surfaces of the ceramic plate 21 are respectively subjected to a roughening process. The roughening process can ensure that the upper and lower surfaces of the ceramic plate 21 can provide better gripping force during the packaging process, further improving the warping deformation problem caused by thermal stress during the packaging process.

[0029] In one specific embodiment of this application, the ceramic structure layer 2 further includes a core material layer 22. The upper and lower surfaces of the ceramic plate 21 are respectively adhered with the core material layer 22. The horizontal area of ​​the core material layer 22 is not less than the horizontal area of ​​the ceramic plate 21. The core material layer 22 is used to enable electrical conduction between the upper and lower layers of the ceramic structure layer 2 through through-holes 23. The core board is composed of copper foil, solid resin, and glass fiber, serving as the basic material for PCB manufacturing. It possesses a certain degree of hardness and thickness, and both surface layers have copper foil. When manufacturing multilayer PCB circuits, PP semi-solid sheets and core boards need to be used together. Typically, PP semi-solid sheets are selected as fillers between two core boards. After the PP semi-solid sheets are extruded, the semi-cured epoxy resin is squeezed out, begins to flow and solidify, bonding the multiple core boards together and forming a reliable insulator. The bottom substrate 1 also includes a PP layer 12, an SR layer 13, and a metal layer 11. The PP semi-solid sheet is composed of semi-solid resin material and glass fiber. Together, they primarily function as a filler, acting as an adhesive and insulating material for the inner conductive patterns of the multilayer PCB. A multilayer board is essentially formed by laminating a core board with a PP semi-solid sheet. The semi-solid sheet is sometimes simply referred to as PP sheet: it refers to an incompletely cured adhesive layer. It is mainly composed of resin-impregnated glass fiber cloth. During the lamination process of a multilayer PCB, PP is sandwiched between core boards or between the core board and the outer copper foil. Under high temperature and pressure, the resin in the PP melts, flows, and eventually completely cures, firmly bonding adjacent copper layers or core boards together while also providing insulation.

[0030] In one specific embodiment of this application, the indium wafer structure layer 5 includes an indium wafer body 51, the horizontal area of ​​which is the same as the upper surface area of ​​the chip 3. The indium wafer body 51 mainly absorbs the heat dissipated from the entire surface of the chip 3, and the heat dissipated from the chip 3 is transferred to the indium wafer body 51 through the upper surface of the chip 3.

[0031] In one specific embodiment of this application, the indium wafer structure layer 5 further includes indium wafer branches 52, which are disposed around the indium wafer body 51 and extend to the edge of the package structure. After absorbing the heat emitted by the chip 3, the indium wafer body 51 transfers the heat to the indium wafer branches 52, which then diffuse and transfer the heat to the surrounding areas.

[0032] In one specific embodiment of this application, the thickness of the indium sheet branch 52 is less than the thickness of the indium sheet body 51. The indium sheet body is used to absorb heat, so a larger thickness is more conducive to heat absorption. The indium sheet branch 52 is used to transfer and dissipate heat, so a thinner thickness is more conducive to heat dissipation.

[0033] In one specific embodiment of this application, the system further includes: a first solder ball 6, which is soldered between the bottom substrate 1 and the top substrate 4, and the closest distance between the indium wafer branch 52 and the first solder ball 6 is not less than a first preset distance. This prevents the indium wafer branch 52 from short-circuiting with the first solder ball 6 while transferring heat, thus avoiding short circuits or transferring heat to the solder ball. The system also includes a second solder ball 7 and a third solder ball 8. The second solder ball 7 is disposed between the chip 3 and the bottom substrate 1 for fixing and connecting the chip 3. The third solder ball 8 is disposed on the lower surface of the bottom substrate 1 for the epitaxial growth of the chip 3's pins.

[0034] In one specific embodiment of this application, the top substrate further includes a welding surface, the structure of which matches the size and shape of the indium wafer structure layer 5. The welding surface is correspondingly configured as the main body structure and branch structure of the chip 3, for welding to the indium wafer main body 51 and the indium wafer branch 52, respectively.

[0035] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A novel POP packaging structure for improving heat dissipation and reducing warpage, characterized in that, include: A multilayer substrate, comprising at least a bottom substrate and a top substrate; chip; A ceramic structural layer is embedded inside the bottom substrate. The ceramic structural layer is provided with through holes, which allow the upper and lower layers of the ceramic structural layer to be connected. An indium wafer structure layer, the lower surface of which is attached to the upper surface of the chip, and the upper surface of which is soldered to the lower surface of the top substrate.

2. The novel packaging structure for improving heat dissipation and reducing warpage of POP as described in claim 1, characterized in that, The horizontal area of ​​the ceramic structure layer matches the horizontal area of ​​the bottom substrate, and the horizontal area of ​​the ceramic structure layer is not less than the first predetermined area size.

3. The novel packaging structure for improving heat dissipation and reducing warpage of POP as described in claim 1, characterized in that, The through holes in the ceramic structural layer are created using laser drilling or mechanical drilling techniques.

4. The novel packaging structure for improving heat dissipation and reducing warpage of POP as described in claim 1, characterized in that, The ceramic structural layer includes: a ceramic plate, The horizontal area of ​​the ceramic plate is not less than the area of ​​the bottom substrate, and the upper and lower surfaces of the ceramic plate are respectively subjected to roughening processes.

5. The novel packaging structure for improving heat dissipation and reducing warpage of POP as described in claim 4, characterized in that, The ceramic structure layer also includes: a core material layer. The upper and lower surfaces of the ceramic plate are respectively bonded with core material layers. The horizontal area of ​​the core material layer is not less than the horizontal area of ​​the ceramic plate. The core material layer is used to enable electrical conduction between the upper and lower layers of the ceramic structure through the through holes.

6. The novel packaging structure for improving heat dissipation and reducing warpage of POP as described in claim 1, characterized in that, The indium sheet structure layer includes: an indium sheet body, The horizontal area of ​​the indium wafer body is the same as the upper surface area of ​​the chip.

7. The novel packaging structure for improving heat dissipation and reducing warpage of POP as described in claim 6, characterized in that, The indium sheet structure layer further includes: indium sheet branches. The indium sheet branches are arranged around the indium sheet body and extend to the edge of the package structure.

8. The novel packaging structure for improving heat dissipation and reducing warpage of POP as described in claim 7, characterized in that, The thickness of the indium sheet branch is less than the thickness of the indium sheet body.

9. The novel packaging structure for improving heat dissipation and reducing warpage of a POP as described in claim 1 or 7, characterized in that, It also includes: a first solder ball, which is soldered between the bottom substrate and the top substrate, and the closest distance between the indium foil branch and the first solder ball is not less than a first preset distance.

10. The novel packaging structure for improving heat dissipation and reducing warpage of POP as described in claim 1, characterized in that, The top substrate also includes: a welding surface. The structure of the welding surface matches the size and shape of the indium sheet structure layer.

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