Additive manufacturing methods for modifying wafer geometry

Abstract

A method for modifying the geometry of a wafer includes measuring the local geometry of each of a plurality of edge locations of the wafer, determining, based on the measured local geometry, an amount of additional material calculated for each of the plurality of locations of the wafer to provide a desired wafer-level geometry to the wafer, and applying the determined amount of additional material from a printing nozzle at each of the plurality of locations of the wafer to provide the desired wafer-level geometry to the wafer.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor device assemblies, and more specifically, to additive manufacturing methods for modifying wafer geometry. Background Technology

[0002] Microelectronic devices typically have dies (i.e., chips) containing integrated circuit systems with a high density of very small components. Typically, a die contains an array of very small bonding pads electrically coupled to the integrated circuit system. These bonding pads are external electrical contacts through which supply voltages, signals, etc., are transmitted to and from the integrated circuit system. After the die is formed, it is "encapsulated" to couple the bonding pads to a larger array of electrical terminals that can be more easily coupled to various power supply lines, signal lines, and ground lines. Conventional processes for encapsulating dies involve electrically coupling the bonding pads on the die to an array of leads, ball pads, or other types of electrical terminals, and encapsulating the die to protect it from environmental factors such as moisture, particles, static electricity, and physical shock.

[0003] To improve the efficiency of high-volume manufacturing, multiple dies can be formed simultaneously from a single workpiece (e.g., a semiconductor material wafer). Therefore, technologies for forming and processing semiconductor dies in wafer form are designed to benefit from improved wafer uniformity (e.g., thickness, flatness, and precise geometry) to improve compatibility with wafer handling tools (e.g., vacuum chucks and peripheral clamping tools). Attached Figure Description

[0004] Figure 1 and 2 This is a simplified schematic cross-sectional view of an example semiconductor device wafer according to various embodiments of the present technology.

[0005] Figure 3 This is a simplified schematic plan view of an example semiconductor device wafer according to various embodiments of the present technology.

[0006] Figure 4 This is a simplified schematic cross-sectional view of an example semiconductor device according to various embodiments of the present technology.

[0007] Figure 5 and 6 This is a simplified schematic cross-sectional view of an example semiconductor device wafer according to various embodiments of the present technology.

[0008] Figure 7 This is a flowchart illustrating a method for modifying the geometry of a wafer according to various embodiments of the present technology. Detailed Implementation

[0009] During the manufacture of semiconductor device assemblies, semiconductor wafers undergo a variety of additive and subtractive processes using multiple materials to achieve the complex structures required to implement the desired circuit functionality. As wafers progress through the manufacturing process, they are frequently moved from one tool or station to another and are therefore designed with standard sizes and geometries to facilitate their handling by specialized tools. One such tool for manipulating wafers is a vacuum chuck, which utilizes the planarity of the wafer's main surface to provide a mechanically secure connection between the wafer and a movable arm by applying a vacuum to the planar surface of the wafer (e.g., by pumping a gaseous medium from between the vacuum chuck and the wafer surface). For wafers that have undergone processing steps that reduce their planarity (e.g., for wafers with corrugations or recesses, or other surface features that would allow gas to enter between the vacuum chuck and the wafer surface more quickly than the applied vacuum could remove), the robust mechanical connection required for reliable wafer handling may differ. One approach to overcoming this challenge involves subtractive planarization of the wafer (e.g., removing material by polishing or grinding the wafer until flatness is restored), but this approach may be limited for thinner wafers or wafers with thin structural features near the main surface, because removing too much bulk material or active circuitry before achieving a sufficient level of flatness can negatively impact the strength or functionality of the wafer.

[0010] To address these and other drawbacks, various embodiments of this application provide methods for additively restoring or providing the flatness of the main surfaces (e.g., front or back) of a wafer via a controlled printing process. By mapping the wafer's morphology (e.g., using any of a variety of zone thickness measurement techniques well known to those skilled in the art), the amount of material in various zones of the wafer can be calculated, and replacement materials (e.g., inkjet-printable polymers or dielectrics) can be provided in thinner zones to restore the wafer to a flatness level compatible with a vacuum chuck. Similarly, for embodiments where other wafer handling tools (e.g., tools that mechanically grip edge zones or sidewalls of the wafer) are used, the wafer geometry can be adjusted to provide a good mechanical interface between the wafer and such tools by printing material in the edge (e.g., bevel) or sidewall zones of the wafer.

[0011] For example, Figure 1 This is a simplified schematic cross-sectional view of an example semiconductor device wafer with locally irregular geometry that would render the wafer incompatible with a vacuum chuck. See reference... Figure 1As can be seen, the wafer 100 includes a main surface 101 having regions 102, in which local geometry is irregular (e.g., recesses cause the wafer thickness T2 to be less than other regions where thickness T1 is greater). Instead of removing material from the wafer until the wafer thickness is the same everywhere, according to aspects of this disclosure, material can be applied at regions 102 (e.g., by inkjet printing) to planarize the main surface 101 to a degree compatible with vacuum chucks.

[0012] Instead of the two-step approach of applying additional material (more than required to restore the regular wafer-level geometry) and then subtractively planarizing the main surface 101, embodiments of this disclosure allow for the addition of a precise amount of additional material based on the measured local geometry (e.g., the measured difference in flatness at multiple locations or measurement points on the wafer). In this regard, the wafer topology can be measured to construct a wafer-level topology map using any of several measurement techniques known to those skilled in the art (e.g., optical measurement, interferometry, probe tip, etc.), from which the amount of additional material to be applied at different locations on the wafer can be calculated.

[0013] Following this calculation, according to one aspect of this disclosure, additional material 103 may be applied, such as Figure 2 As explained in the document. (See reference...) Figure 2 As can be seen, the amount of additional material 103 has been precisely determined based on the calculated volume required to restore the main surface 101 to flatness and applied (e.g., via a printer nozzle) to region 102. According to another embodiment, the additional material 103 may be applied over the entire main surface 101 of the wafer 100, wherein the amount varies depending on the location as determined by the measurement step to provide flatness across the main surface 101. However, in this example, only region 102 has been applied with the additional material 103.

[0014] The additional material applied to additively correct or modify the geometry of the wafer can be any of several materials compatible with inkjet printing processes, including, for example, dielectric materials (e.g., oxides, nitrides and / or silicides, polyimides, benzocyclobutene, polybenzoxazole, acrylates), or even, in some cases, conductive materials (e.g., copper, gold, silver, aluminum, and the like).

[0015] In some embodiments, the printed material can be rapidly dried after inkjet printing without requiring an additional heat treatment step. In other embodiments, the printed material may be subjected to a heating step to increase the rate at which the carrier liquid or solvent in the printed material is removed / evaporated.

[0016] Figure 3 This is a simplified schematic plan view of an example semiconductor device wafer according to various embodiments of the present technology. See reference... Figure 3As can be seen, the additional material 103 applied at zone 102 may overlap with one or more bare sheets 105, which are separated from each other by scribing grooves 104. Therefore, according to various embodiments of the present technology, after slicing the bare sheets along the scribing grooves 104, some of the resulting bare sheets 105 may contain a portion of the additional material at the main surface 101 and / or at one or more of its sidewalls, such as... Figure 4 The example semiconductor device 104 is illustrated in a simplified schematic cross-sectional view.

[0017] In addition to providing the desired level of flatness of the main surface of the wafer, embodiments of this disclosure may also provide other desired types of wafer-level geometry. For example, some wafer handling tools are configured to interface with wafers having a specific bevel geometry (e.g., bevel angle and / or bevel size) at the edges of their main surfaces. The ability to safely handle wafers may be included for areas where the local geometry of the edge bevels differs from the desired geometry due to previous processing steps. Therefore, embodiments of this disclosure may relate to restoring wafer-level edge geometry using additive inkjet printing methods, as described in more detail below.

[0018] Turning Figure 5 This provides a simplified schematic cross-sectional view of an example semiconductor device wafer, wherein the wafer has locally irregular geometry that would render the wafer incompatible with wafer handling tools. (See reference...) Figure 5 As can be seen, wafer 500 includes a main surface 501 with beveled edges. Wafer 500 includes regions 502 where the local geometry is irregular (e.g., where the bevel angle Θ2 differs from the regular bevel angle Θ1 at other locations on the wafer), and this would hinder compatibility with wafer handling tools that rely on a consistent bevel angle Θ1 across wafer 501. To address this issue, according to aspects of this disclosure, material can be applied at region 502 (e.g., by inkjet printing) to restore the desired bevel angle Θ1 there. To calculate the amount of additional material required, the wafer geometry can be measured using any of several measurement techniques known to those skilled in the art (e.g., optical measurement, interferometry, probe tip, etc.) to construct a wafer-level geometry model, from which the amount of additional material to be applied at different locations on the wafer can be calculated.

[0019] Following this calculation, according to one aspect of this disclosure, additional material 503 may be applied, such as Figure 6 As explained in the document. (See reference...) Figure 6 As can be seen, the amount of additional material 503 has been precisely determined based on the calculated volume required to restore the edge bevel to a consistent wafer width and applied (e.g., via a printer nozzle) to region 502.

[0020] Although in the foregoing example embodiments the wafer-level geometry has been described and depicted as relating to the flatness of the main surface or the angle and / or size of the edge bevel, in other embodiments, other wafer geometries can be similarly modified using additive printing processes with appropriate modifications.

[0021] Figure 7 This is a flowchart illustrating a method for altering the geometry of a wafer according to an embodiment of the present disclosure. The method includes measuring the local geometry of each of a plurality of locations on the wafer (block 710). The method further includes determining, based on the measured local geometry, an amount of additional material calculated for each of the plurality of locations on the wafer to provide a desired wafer-level geometry to the wafer (block 720). The method further includes applying the determined amount of additional material from a printing nozzle at each of the plurality of locations on the wafer to provide the desired wafer-level geometry to the wafer (block 730).

[0022] According to one aspect of this disclosure, reference is made to Figures 1 to 7 The semiconductor devices and wafers described and illustrated may include memory dies, such as dynamic random access memory (DRAM) dies, NAND memory dies, NOR memory dies, magnetic random access memory (MRAM) dies, phase-change memory (PCM) dies, ferroelectric random access memory (FeRAM) dies, static random access memory (SRAM) dies, or the like. According to another aspect of this disclosure, the semiconductor dies and wafers described and illustrated above may include logic dies (e.g., controller dies, processor dies, etc.), hybrids of logic dies and memory dies (e.g., in heterogeneous reconfiguration wafers), transducers (e.g., MEMS devices), communication devices, light-emitting devices, or any other solid-state / semiconductor devices capable of wafer-level fabrication.

[0023] The foregoing describes specific details of several embodiments of semiconductor devices and associated systems and methods. Those skilled in the art will recognize that the methods described herein can be performed at appropriate stages, either at the wafer level or at the die level. Therefore, depending on the context in which it is used, the term "substrate" can refer to a wafer-level substrate or a single-cut die-level substrate. Furthermore, unless the context otherwise indicates, conventional semiconductor manufacturing techniques can be used to form the structures disclosed herein. Examples of techniques for depositing materials include chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, examples of techniques for removing materials include plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0024] In other embodiments, the term "substrate" may refer to a package-level substrate on which other semiconductor devices are carried, such as a printed circuit board (PCB), an interposer, or another semiconductor device.

[0025] The devices discussed herein (including memory devices) can be formed on a semiconductor substrate or die (e.g., silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0026] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and embodiments are within the scope of this disclosure and the appended claims. Features implementing the functions may also be physically located in various locations, comprising portions distributed such that the functions are implemented at different physical locations.

[0027] As used herein, the word "or" in the claims, as in a list of items (for example, a list of items preceded by phrases such as "at least one of..." or "one or more of..."), indicates a list of inclusions such that a list of at least one of, for example, A, B, or C, implies A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a set of closing conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0028] As used herein, the terms “vertical,” “horizontal,” “up,” “down,” “above,” and “below” can refer to the relative orientation or position of a feature in a semiconductor device given the orientation shown in the figures. For example, “up” or “top” can refer to a feature positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, above / below, above / below, up / down, and left / right can be interchanged depending on the orientation.

[0029] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more of the methods can be combined.

[0030] As will be understood from the foregoing, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Rather, numerous specific details have been set forth in the foregoing description to provide a thorough and illustrative description of embodiments of the present technology. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the present technology. Generally, it should be understood that various other devices, systems, and methods besides those specific embodiments disclosed herein are also within the scope of the present technology.

Claims

1. A method for planarizing a wafer, the method comprising: Measure the surface height of each of multiple locations on the wafer; Based on the measured surface height, the amount of additional material calculated for each of the plurality of locations on the wafer to provide the desired level of flatness is determined; and At each of the plurality of locations on the wafer, the determined amount of additional material is applied from the printing nozzle to planarize the wafer to the desired level of flatness.

2. The method of claim 1, wherein measuring the surface height at one of the plurality of locations includes measuring the thickness of the wafer at that location.

3. The method of claim 1, wherein measuring the surface height at one of the plurality of locations includes measuring the distance between the surface of the wafer at that location and the measuring tool.

4. The method of claim 1, wherein determining the amount of the additional material for one of the plurality of locations includes calculating the volume of the recess at the one location.

5. The method according to claim 1, wherein the printing nozzle is composed of an inkjet printing mechanism.

6. The method of claim 1, wherein the additional material comprises a polymer or a dielectric material.

7. A method for modifying the edge geometry of a wafer, the method comprising: Measure the local geometry of each of a plurality of edge locations of the wafer; Based on the measured local geometry, determine the amount of additional material calculated for each of the plurality of edge locations of the wafer to provide the desired edge geometry; and At each of the plurality of edge locations of the wafer, the determined amount of additional material is applied from the printing nozzle to provide the wafer with the desired edge geometry.

8. The method of claim 7, wherein measuring the local geometry of one of the plurality of edge locations includes measuring the slope angle at the one location.

9. The method of claim 7, wherein the printing nozzle is composed of an inkjet printing mechanism.

10. The method of claim 7, wherein the additional material comprises a polymer or a dielectric material.

11. A semiconductor device chip, comprising: A substrate comprising a first material having a first main surface surrounded by edges; The region at the first main surface has an irregular geometry; and A second material is applied to the region to provide a wafer-level regular geometry to the semiconductor device wafer.

12. The semiconductor device wafer of claim 11, wherein the region includes a recess in the first main surface.

13. The semiconductor device wafer of claim 11, wherein the region is located on a slope adjacent to the edge.

14. The semiconductor device wafer of claim 11, wherein the second material is different from the first material.

15. The semiconductor device wafer of claim 11, wherein the second material comprises a polymer or a dielectric material.

16. The semiconductor device wafer of claim 11, wherein the irregular geometry is non-planar and the wafer-level regular geometry is planar.

17. The semiconductor device wafer of claim 11, wherein the irregular geometry is a variation of the bevel angle, and the wafer-level regular geometry includes a consistent wafer-level bevel angle.

18. The semiconductor device wafer of claim 11, wherein the irregular geometry is a variation in the size of the bevel, and the wafer-level regular geometry includes a consistent wafer-level bevel size.

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