A method for splicing a target SRAM, an electronic device and a medium

Abstract

This invention relates to the field of chip technology, and more particularly to a method, electronic device, and medium for splicing together to generate a target SRAM. The method generates a target SRAM based on a candidate SRAM, a first register, and a second register, such that the final generated target depth is equal to or greater than the target depth with an error within a preset depth difference range, and the final generated target bit width is equal to or greater than the target bit width with an error within a preset bit width difference range. This invention reduces the waste of size and area in the final generated target SRAM.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more particularly to a method for splicing together to generate a target SRAM, an electronic device, and a medium. Background Technology

[0002] SRAM (Static Random-Access Memory) is a high-speed semiconductor memory based on a flip-flop circuit structure. Its core feature is that it can retain data without refreshing, and it is widely used in the chip industry. When a target SRAM of a specific size does not exist, it is usually generated by splicing together multiple other SRAMs of fixed size. However, this method of generating a target SRAM by splicing together fixed-size SRAMs often results in a depth and / or bit width larger than the target size, causing excessive area and wasting space. Therefore, how to reduce the waste of size and area of ​​the target SRAM has become an urgent technical problem to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a method, electronic device, and medium for splicing to generate a target SRAM, thereby reducing the waste of the size and area of ​​the target SRAM.

[0004] According to a first aspect of the present invention, a method for splicing together to generate a target SRAM is provided, comprising: Select one candidate SRAM to generate the target SRAM region of the target SRAM, or select multiple candidate SRAMs and splice them together to generate the target SRAM region of the target SRAM. The absolute value of the difference between the target depth and the depth of the target SRAM region is less than a preset depth difference, the absolute value of the difference between the target bit width and the bit width of the target SRAM region is less than a preset bit width difference, the target depth is the depth of the target SRAM to be generated, and the target bit width is the bit width of the target SRAM to be generated. If the difference between the bit width of the target SRAM region and the target bit width is greater than or equal to 0 and the difference between the depth of the target SRAM region and the target depth is greater than or equal to 0, then the target SRAM region is directly generated as the target SRAM. If the difference between the target bit width and the target SRAM area bit width is greater than 0, then at least one register area composed of first registers is set up, the bit width of the register area is equal to the difference between the target bit width and the target SRAM area bit width, and the depth of the register area is equal to the depth of the target SRAM area; If the difference between the target depth and the target SRAM area depth is greater than 0, then a second register is set. The bit width of the second register is equal to the maximum value between the target bit width and the target SRAM area bit width, and the depth of the second register is equal to the difference between the target bit width and the target SRAM area bit width. If a register area and a second register exist, the target SRAM area and the register area are first spliced ​​together in the bit width direction to form a first splicing area. The bit width of the first splicing area is the target bit width, and the depth of the first splicing area is the depth of the target SRAM area. Then, the first splicing area and the second register are spliced ​​together in the depth direction to form the target SRAM. If only a register area exists, then the target SRAM area and the register area are concatenated in the bit width direction to generate the target SRAM; If only the second register exists, the target SRAM area and the second register are spliced ​​together in the depth direction to generate the target SRAM.

[0005] Furthermore, the step of selecting a candidate SRAM to generate the target SRAM region of the target SRAM or selecting multiple candidate SRAMs and splicing them together to generate the target SRAM region includes: If there exists a first candidate SRAM where the difference between depth and target depth is greater than or equal to 0 and less than a preset depth difference, and the difference between bit width and target bit width is greater than or equal to 0 and less than a preset bit width difference, then a first candidate SRAM is selected as the target SRAM region. If, in the absence of a first candidate SRAM, there exists a second candidate SRAM whose difference between depth and target depth is greater than or equal to 0, whose difference between bit width and target bit width is less than 0, and whose absolute value is less than a preset bit width difference, then a second candidate SRAM is selected as the target SRAM region. In the absence of a first candidate SRAM and a second candidate SRAM, at least one type of third candidate SRAM is obtained to form a target SRAM area with a depth equal to the target depth, a bit width difference less than 0 and an absolute value less than a preset bit width difference. If there are no first candidate SRAM, second candidate SRAM and third candidate SRAM, then at least one type of fourth SRAM is spliced ​​together to form a target SRAM region where the difference between the depth and the target depth is less than 0 and the absolute value is less than the preset depth, and the difference between the bit width and the target bit width is less than 0 and the absolute value is less than the preset bit width difference.

[0006] Furthermore, selecting a first candidate SRAM as the target SRAM region includes: The first candidate SRAM with the smallest difference from the target depth and the smallest difference from the target bit width is selected to generate the target SRAM region.

[0007] Furthermore, selecting a second candidate SRAM as the target SRAM region includes: The second candidate SRAM with the smallest difference from the target depth and the smallest absolute value of the difference from the target bit width is selected to generate the target SRAM region.

[0008] Furthermore, if the target SRAM region is to be formed by splicing together the third candidate SRAMs, the following conditions must be met in sequence: The absolute value of the difference between the target SRAM region bit width and the target bit width is taken as the minimum value; The number of third candidate SRAM types selected is the smallest; The number of third candidate SRAMs selected is the smallest.

[0009] Furthermore, if the target SRAM region is to be formed by splicing together the fourth SRAM, the following conditions must be met in sequence: The absolute value of the difference between the depth of the target SRAM region and the target depth is taken as the minimum value; The absolute value of the difference between the target SRAM region bit width and the target bit width is taken as the minimum value; The number of fourth candidate SRAM types selected is the smallest; The number of fourth candidate SRAMs selected should be small.

[0010] Furthermore, the first register and the second register are of the same SRAM port type as the candidate SRAM used to generate the target SRAM area, and their timing is consistent. The SRAM types include single-port SRAM, dual-port SRAM, and asynchronous dual-port SRAM.

[0011] Furthermore, the target SRAM region includes M×N candidate SRAMs, where M is the number of rows of SRAMs in the target SRAM region, and N is the number of columns of candidate SRAMs in the target SRAM region. Candidate SRAMs located in the same row have the same depth, and candidate SRAMs located in the same column have the same bit width. The bit width of the candidate SRAM in the m-th row and n-th column is f(mn), and the depth is g(mn). f(mn) is less than or equal to the target bit width, and g(mn) is less than or equal to the target depth. The value of m ranges from 1 to M, and the value of n ranges from 1 to N. If a first register exists, then each row of candidate SRAMs in the target SRAM region is assigned a first register, and the depth of the first register is the same as the depth of the candidate SRAM in the corresponding row. The bit width of all first registers is z. If a second register exists, then the depth of the second register is B. The method further includes: Establish a mapping relationship between the address of the r-th row in the candidate SRAM of row m and column n and the address of the P(mn)+r-th row in the target SRAM, where r ranges from 1 to R, R is the depth value of the candidate SRAM of row m and column n, and P(mn) is the address of the last row of the candidate SRAM located in row m-1 in the target SRAM area in the target SRAM. Establish a mapping relationship between the address of the r-th row of the first register in the m-th row and the address of the P(mn)+r-th row of the target SRAM; Establish a mapping relationship between the address of row b in the second register and the address of row P(MN)+b in the target SRAM, where the value of b ranges from 1 to B. Set the target data bit range of the candidate SRAM in the m-th row and n-th column to [Q(mn)+1, Q(mn)+W] bits, where Q(mn) is the target data bit corresponding to the last column of the candidate SRAM in the (n-1)-th column of the target SRAM area; Set the target data bit range of the first register in the i-th row to [Q(MN)+1, Q(MN)+z] bits of the target data; Set the target data bit range of the second register to the full range of target data bits; Access each candidate SRAM, first register, and second register based on the mapping relationship between each row address of each candidate SRAM, first register, and second register and the address of the target SRAM, as well as the target data bit range.

[0012] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.

[0013] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.

[0014] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the method, electronic device, and medium for splicing and generating target SRAM provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It has at least the following beneficial effects: This invention uses candidate SRAM, first register, and second register to concatenate and generate target SRAM, so that the final generated target depth is equal to or greater than the target depth with an error within a preset depth difference range, and the final generated target bit width is equal to or greater than the target bit width with an error within a preset bit width difference range, thereby reducing the waste of size and area of ​​the final generated target SRAM. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart of a method for splicing and generating a target SRAM according to an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the splicing of the register area, the second register, and the target SRAM area to generate the target SRAM, as provided in an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] This invention provides a method for splicing and generating a target SRAM, such as... Figure 1 As shown, it includes: Step S1: Select a candidate SRAM to generate the target SRAM area of ​​the target SRAM, or select multiple candidate SRAMs and splice them together to generate the target SRAM area of ​​the target SRAM. The absolute value of the difference between the target depth and the depth of the target SRAM area is less than a preset depth difference, and the absolute value of the difference between the target bit width and the bit width of the target SRAM area is less than a preset bit width difference.

[0019] It should be noted that the target depth refers to the expected depth of the target SRAM to be generated, and the target bit width refers to the expected bit width of the target SRAM to be generated. The actual depth of the generated target SRAM is greater than or equal to the target depth, and the actual bit width of the generated target SRAM is greater than or equal to the target bit width. The preset depth difference is a tolerable depth difference, and the specific value is set according to specific application requirements. The preset depth difference and preset bit width difference are tolerable bit width differences, and the specific value is set according to specific application requirements. By using the preset depth difference and preset bit width difference, the error between the final generated target SRAM depth and the target depth can be kept within a controllable range. The error between the final generated target SRAM bit width and the target bit width can also be kept within a controllable range.

[0020] Step S2: If the difference between the bit width of the target SRAM region and the target bit width is greater than or equal to 0 and the difference between the depth of the target SRAM region and the target depth is greater than or equal to 0, then the target SRAM region is directly generated as the target SRAM.

[0021] It should be noted that when the difference between the bit width of the target SRAM area and the target bit width is greater than or equal to 0, the target SRAM area can meet the requirements of the target SRAM, and there is no need to splice registers. Therefore, the target SRAM area is directly generated as the target SRAM.

[0022] Step S3: If the difference between the target bit width and the target SRAM area bit width is greater than 0, then set up a register area composed of at least one first register. The bit width of the register area is equal to the difference between the target bit width and the target SRAM area bit width, and the depth of the register area is equal to the depth of the target SRAM area.

[0023] Step S4: If the difference between the target depth and the target SRAM area depth is greater than 0, then set a second register. The bit width of the second register is equal to the maximum value between the target bit width and the target SRAM area bit width, and the depth of the second register is equal to the difference between the target bit width and the target SRAM area bit width.

[0024] It should be noted that the second register will eventually be spliced ​​in the depth direction. It needs to be spliced ​​with the target SRAM area above or the first splicing area after the target SRAM area is spliced ​​with the first register. Therefore, the bit width of the second register is equal to the maximum value between the target bit width and the bit width of the target SRAM area, that is, the larger value between the target bit width and the bit width of the target SRAM area.

[0025] Step S5: If a register area and a second register exist, first concatenate the target SRAM area and the register area in the bit-width direction to form a first concatenation area. The bit width of the first concatenation area is the target bit width, and the depth of the first concatenation area is the depth of the target SRAM area. Then, concatenate the first concatenation area and the second register in the depth direction to form the target SRAM. If only a register area exists, concatenate the target SRAM area and the register area in the bit-width direction to form the target SRAM. If only a second register exists, concatenate the target SRAM area and the second register in the depth direction to form the target SRAM.

[0026] It should be noted that, according to the above process, the final result may be that both the register area and the second register exist simultaneously, or only one of the register area and the second register exists, or neither the register area nor the second register exists. Different methods will be selected for splicing depending on the specific circumstances. Figure 2 An example is shown where a register area and a second register are spliced ​​together with the target SRAM area to generate the target SRAM.

[0027] As one embodiment, the first register and the second register are of the same SRAM port type as the candidate SRAM used to generate the target SRAM area, and the timing is consistent. The SRAM type includes single-port SRAM (IPS RAM), dual-port SRAM (2PS RAM), and asynchronous dual-port SRAM (2PA SRAM).

[0028] As one embodiment, in step S1, selecting a candidate SRAM to generate the target SRAM region of the target SRAM, or selecting multiple candidate SRAMs and splicing them together to generate the target SRAM region of the target SRAM, includes: Step S11: If there exists a first candidate SRAM where the difference between the depth and the target depth is greater than or equal to 0 and less than the preset depth difference, and the difference between the bit width and the target bit width is greater than or equal to 0 and less than the preset bit width difference, then select a first candidate SRAM as the target SRAM region.

[0029] It should be noted that when only one SRAM is needed to generate the target SRAM, it is preferable to use a first candidate SRAM to generate the target SRAM area. The first candidate SRAM can be used as the target SRAM area to directly generate the target SRAM without the need for subsequent register splicing.

[0030] Step S12: If, in the absence of a first candidate SRAM, there exists a second candidate SRAM whose depth minus the target depth is greater than or equal to 0, whose bit width minus the target bit width is less than 0, and whose absolute value is less than the preset bit width difference, then a second candidate SRAM is selected as the target SRAM region.

[0031] It should be noted that register splicing is required. Since the larger the register bit width, the greater the impact on the area, while the register depth has a smaller impact on the area than the register bit width, if it is not possible to select a first candidate SRAM directly as the target SRAM, it is preferable to ensure that the difference between the depth and the target depth is greater than or equal to 0. In this way, if there is a second candidate SRAM as the target SRAM area, there is no need to splice registers in the depth direction.

[0032] Step S13: In the absence of a first candidate SRAM and a second candidate SRAM, obtain at least one type of third candidate SRAM to form a target SRAM area with a depth equal to the target depth, a bit width less than 0 and an absolute value less than the preset bit width difference.

[0033] It should be noted that, assuming no first or second candidate SRAM exists, multiple SRAMs need to be selected and pieced together to generate the target SRAM region. These multiple SRAMs can be of one or more types. In this case, the condition that at least one type of third candidate SRAM must be pieced together to form a depth equal to the target depth is still prioritized, thus eliminating the need for registers to be pieced together in the depth direction.

[0034] Step S14: If there are no first candidate SRAM, second candidate SRAM and third candidate SRAM, then obtain at least one type of fourth SRAM spliced ​​together to form a target SRAM area where the difference between the depth and the target depth is less than 0 and the absolute value is less than the preset depth, and the difference between the bit width and the target bit width is less than 0 and the absolute value is less than the preset bit width difference.

[0035] It should be noted that, in the absence of a first candidate SRAM, a second candidate SRAM, and a third candidate SRAM, multiple SRAMs need to be spliced ​​together to form a target SRAM area with a depth smaller than the target depth and a bit width smaller than the target bit width. Then, the corresponding registers are spliced ​​together in the final payment direction and the depth direction.

[0036] Steps S11-S14 can obtain the optimal target SRAM region, thereby obtaining the optimal target SRAM and minimizing the waste of the size and area of ​​the final generated target SRAM.

[0037] As a preferred example, in step S11, selecting a first candidate SRAM as the target SRAM region includes: Step S111: Select the first candidate SRAM with the smallest difference from the target depth and the smallest difference from the target bit width to generate the target SRAM area.

[0038] As a preferred example, in step S12, selecting a second candidate SRAM as the target SRAM region includes: Step S121: Select the second candidate SRAM with the smallest difference from the target depth and the smallest absolute value of the difference from the target bit width to generate the target SRAM area.

[0039] As a preferred example, in step S13, if the target SRAM region is formed by splicing together the third candidate SRAM, the following conditions must be met in sequence: Condition 1: The absolute value of the difference between the target SRAM area bit width and the target bit width is the minimum.

[0040] Condition 2: The number of selected third candidate SRAM types is the smallest.

[0041] Condition 3: The number of selected third candidate SRAMs is minimized.

[0042] It should be noted that the priority of condition 1 is higher than that of condition 2, which in turn is higher than that of condition 3.

[0043] As a preferred example, in step S14, if the target SRAM region is formed by splicing together the fourth SRAM, the following conditions must be met in sequence: Condition 1: The absolute value of the difference between the depth of the target SRAM region and the target depth is the minimum.

[0044] Condition 2: The absolute value of the difference between the target SRAM area bit width and the target bit width is the minimum.

[0045] Condition 3: The number of fourth candidate SRAM types selected is the smallest.

[0046] Condition 4: The number of fourth candidate SRAMs selected is minimized.

[0047] It should be noted that the priority of condition 1 is higher than that of condition 2, which is higher than that of condition 3, which is higher than that of condition 4.

[0048] As one embodiment, the target SRAM region includes M×N candidate SRAMs, where M is the number of rows of SRAMs in the target SRAM region, and N is the number of columns of candidate SRAMs in the target SRAM region. Candidate SRAMs located in the same row have the same depth, and candidate SRAMs located in the same column have the same bit width. The bit width of the candidate SRAM in the m-th row and n-th column is f(mn), and the depth is g(mn), where f(mn) is less than or equal to the target bit width, and g(mn) is less than or equal to the target depth. The value of m ranges from 1 to M, and the value of n ranges from 1 to N. If a first register exists, then a first register is set for each row of candidate SRAMs in the target SRAM region. The depth of the first register is the same as the depth of the candidate SRAM in the corresponding row, and the bit width of all first registers is z. If a second register exists, then the depth of the second register is B.

[0049] As one embodiment, the method further includes: Step S6: Establish a mapping relationship between the address of the r-th row in the candidate SRAM (row m, column n) and the address of the P(mn)+r-th row in the target SRAM, where r ranges from 1 to R, R is the depth of the candidate SRAM (row m, column n), and P(mn) is the address of the last row of the candidate SRAM (row m-1) in the target SRAM. Establish a mapping relationship between the address of the r-th row in the first register (row m) and the address of the P(mn)+r-th row in the target SRAM. Establish a mapping relationship between the address of the b-th row in the second register and the address of the P(MN)+b-th row in the target SRAM, where b ranges from 1 to B.

[0050] Step S6, which needs to be explained, establishes the mapping relationship between the address of each candidate SRAM, each first register, and each second register of the target SRAM and the address of the target SRAM.

[0051] Step S7: Set the target data bit range of the candidate SRAM in row m and column n to [Q(mn)+1, Q(mn)+W] bits, where Q(mn) is the target data bit range corresponding to the last column of the candidate SRAM in column n-1 of the target SRAM area. Set the target data bit range of the first register in row i to [Q(MN)+1, Q(MN)+z] bits of the target data. Set the target data bit range of the second register to the entire range of the target data.

[0052] It should be noted that step S7 establishes a correspondence between each candidate SRAM, each first register, and each second register used to splice and generate the target SRAM and the bit width of the target data to be received. The target data is the data used to input into the target SRAM.

[0053] Step S8: Access each candidate SRAM, first register, and second register based on the mapping relationship between each row address of each candidate SRAM, first register, and second register and the address of the target SRAM, as well as the target data bit range.

[0054] It should be noted that once the mapping relationship between the address of each candidate SRAM, each first register, and each second register of the target SRAM is established and the address of the target SRAM is set, and the correspondence between each candidate SRAM, each first register, and each second register of the target SRAM and the bit width of the target data to be received is established, each candidate SRAM, each first register, and each second register can be accessed based on the mapping relationship between the address of each row of each candidate SRAM, each first register, and each second register and the address of the target SRAM, as well as the bit range of the target data. This enables the use of the target SRAM generated by splicing candidate SRAMs, first registers, and second registers.

[0055] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0056] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.

[0057] This invention also provides a computer-readable storage medium storing computer-executable instructions for performing the methods described in this invention.

[0058] The embodiments of the present invention use candidate SRAM, first register, and second register to splice together target SRAM, so that the final generated target depth is equal to the target depth, or greater than the target depth with an error within a preset depth difference range, and the final generated target bit width is equal to the target bit width, or greater than the target bit width with an error within a preset bit width difference range, thereby reducing the waste of size and area of ​​the final generated target SRAM.

[0059] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for splicing and generating a target SRAM, characterized in that, include: Select one candidate SRAM to generate the target SRAM region of the target SRAM, or select multiple candidate SRAMs and splice them together to generate the target SRAM region of the target SRAM. The absolute value of the difference between the target depth and the depth of the target SRAM region is less than a preset depth difference, the absolute value of the difference between the target bit width and the bit width of the target SRAM region is less than a preset bit width difference, the target depth is the depth of the target SRAM to be generated, and the target bit width is the bit width of the target SRAM to be generated. If the difference between the bit width of the target SRAM region and the target bit width is greater than or equal to 0 and the difference between the depth of the target SRAM region and the target depth is greater than or equal to 0, then the target SRAM region is directly generated as the target SRAM. If the difference between the target bit width and the target SRAM area bit width is greater than 0, then at least one register area composed of first registers is set up, the bit width of the register area is equal to the difference between the target bit width and the target SRAM area bit width, and the depth of the register area is equal to the depth of the target SRAM area; If the difference between the target depth and the target SRAM area depth is greater than 0, then a second register is set. The bit width of the second register is equal to the maximum value between the target bit width and the target SRAM area bit width, and the depth of the second register is equal to the difference between the target bit width and the target SRAM area bit width. If a register area and a second register exist, the target SRAM area and the register area are first spliced ​​together in the bit width direction to form a first splicing area. The bit width of the first splicing area is the target bit width, and the depth of the first splicing area is the depth of the target SRAM area. Then, the first splicing area and the second register are spliced ​​together in the depth direction to form the target SRAM. If only a register area exists, then the target SRAM area and the register area are concatenated in the bit width direction to generate the target SRAM; If only the second register exists, the target SRAM area and the second register are spliced ​​together in the depth direction to generate the target SRAM.

2. The method according to claim 1, characterized in that, The step of selecting a candidate SRAM to generate the target SRAM region of the target SRAM or selecting multiple candidate SRAMs and splicing them together to generate the target SRAM region includes: If there exists a first candidate SRAM where the difference between depth and target depth is greater than or equal to 0 and less than a preset depth difference, and the difference between bit width and target bit width is greater than or equal to 0 and less than a preset bit width difference, then a first candidate SRAM is selected as the target SRAM region. If, in the absence of a first candidate SRAM, there exists a second candidate SRAM whose difference between depth and target depth is greater than or equal to 0, whose difference between bit width and target bit width is less than 0, and whose absolute value is less than a preset bit width difference, then a second candidate SRAM is selected as the target SRAM region. In the absence of a first candidate SRAM and a second candidate SRAM, at least one type of third candidate SRAM is obtained to form a target SRAM area with a depth equal to the target depth, a bit width difference less than 0 and an absolute value less than a preset bit width difference. If there are no first candidate SRAM, second candidate SRAM and third candidate SRAM, then at least one type of fourth SRAM is spliced ​​together to form a target SRAM region where the difference between the depth and the target depth is less than 0 and the absolute value is less than the preset depth, and the difference between the bit width and the target bit width is less than 0 and the absolute value is less than the preset bit width difference.

3. The method according to claim 2, characterized in that, Selecting a first candidate SRAM as the target SRAM region includes: The first candidate SRAM with the smallest difference from the target depth and the smallest difference from the target bit width is selected to generate the target SRAM region.

4. The method according to claim 2, characterized in that, Selecting a second candidate SRAM as the target SRAM region includes: The second candidate SRAM with the smallest difference from the target depth and the smallest absolute value of the difference from the target bit width is selected to generate the target SRAM region.

5. The method according to claim 2, characterized in that, If the target SRAM region is to be formed by splicing together the third candidate SRAM, the following conditions must be met in sequence: The absolute value of the difference between the target SRAM region bit width and the target bit width is taken as the minimum value; The number of third candidate SRAM types selected is the smallest; The number of third candidate SRAMs selected is the smallest.

6. The method according to claim 2, characterized in that, If the target SRAM area is to be formed by splicing together the fourth SRAM, the following conditions must be met in sequence: The absolute value of the difference between the depth of the target SRAM region and the target depth is taken as the minimum value; The absolute value of the difference between the target SRAM region bit width and the target bit width is taken as the minimum value; The number of fourth candidate SRAM types selected is the smallest; The number of fourth candidate SRAMs selected should be small.

7. The method according to claim 1, characterized in that, The first register and the second register are of the same SRAM port type as the candidate SRAM used to generate the target SRAM area, and their timing is consistent. The SRAM types include single-port SRAM, dual-port SRAM and asynchronous dual-port SRAM.

8. The method according to claim 1, characterized in that, The target SRAM region includes M×N candidate SRAMs, where M is the number of rows of SRAMs in the target SRAM region and N is the number of columns of candidate SRAMs in the target SRAM region. Candidate SRAMs located in the same row have the same depth, and candidate SRAMs located in the same column have the same bit width. The bit width of the candidate SRAM in the m-th row and n-th column is f(mn), and the depth is g(mn). f(mn) is less than or equal to the target bit width, and g(mn) is less than or equal to the target depth. The value of m ranges from 1 to M, and the value of n ranges from 1 to N. If a first register exists, then each row of candidate SRAM in the target SRAM area is configured with a first register. The depth of the first register is the same as the depth of the candidate SRAM in the corresponding row, and the bit width of all first registers is z. If a second register exists, then the depth of the second register is B; The method further includes: Establish a mapping relationship between the address of the r-th row in the candidate SRAM of row m and column n and the address of the P(mn)+r-th row in the target SRAM, where r ranges from 1 to R, R is the depth value of the candidate SRAM of row m and column n, and P(mn) is the address of the last row of the candidate SRAM located in row m-1 in the target SRAM area in the target SRAM. Establish a mapping relationship between the address of the r-th row of the first register in the m-th row and the address of the P(mn)+r-th row of the target SRAM; Establish a mapping relationship between the address of row b in the second register and the address of row P(MN)+b in the target SRAM, where the value of b ranges from 1 to B. Set the target data bit range of the candidate SRAM in the m-th row and n-th column to [Q(mn)+1, Q(mn)+W] bits, where Q(mn) is the target data bit corresponding to the last column of the candidate SRAM in the (n-1)-th column of the target SRAM area; Set the target data bit range of the first register in the i-th row to [Q(MN)+1, Q(MN)+z] bits of the target data; Set the target data bit range of the second register to the full range of target data bits; Access each candidate SRAM, first register, and second register based on the mapping relationship between each row address of each candidate SRAM, first register, and second register and the address of the target SRAM, as well as the target data bit range.

9. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions that are executed by the at least one processor, the instructions being configured to perform the method of any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method of any one of claims 1-8.

Images