Chip storage fixed-point power-down test method and storage medium
By defining an interaction protocol and an abnormal power failure meter between the host and the device of the memory chip, precise point-to-point power failure testing of the memory chip is realized, which solves the problems of incomplete test coverage and poor repeatability in the existing technology, and improves the efficiency and quality of reliability verification under abnormal power failure scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 合肥康芯威存储技术有限公司
- Filing Date
- 2026-03-05
- Publication Date
- 2026-06-05
AI Technical Summary
Existing abnormal power-down testing methods for memory chips cannot accurately target critical code locations, resulting in incomplete test coverage and poor targeting. This makes it difficult to verify the power-down safety of critical locations, and the testing process is not repeatable, time-consuming, and labor-intensive, making it difficult to reproduce faults in specific scenarios.
By defining an interaction protocol between the host and the device, the abnormal power failure response mechanism and abnormal power failure meter pre-built in the device's firmware can be obtained, and power failure can be precisely controlled at specific code locations. Combined with the abnormal power failure meter, all power failure points to be tested can be systematically managed, and a controllable and repeatable fixed-point power failure test system can be built.
It enables precise point-to-point testing of memory chips under abnormal power failure scenarios, improves test coverage and repeatability, significantly enhances the efficiency and quality of reliability verification, and ensures targeted verification of key exception handling logic.
Smart Images
Figure CN122157742A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory chip technology, and more specifically to a method for testing the fixed-point power failure of a memory chip and a memory medium. Background Technology
[0002] In the field of storage devices, abnormal power loss refers to a situation where a device fails to complete the power-off process according to normal procedures during read, write, or erase operations (such as sudden power failure, accidental plugging or unplugging, or power interruption), rather than a system-initiated orderly shutdown or hibernation. For storage chips such as eMMC, UFS, SSD, and microcontrollers, it is necessary to verify data security during abnormal power loss, which requires power loss testing covering critical locations in firmware operation. Therefore, testing power loss points at various locations in the firmware of storage chip devices is relatively important.
[0003] Traditional testing, which involves random power outages or simple cyclic power interruptions on the host, can only randomly trigger arbitrary code locations during firmware execution. This fails to pinpoint specific power-down points anticipated by developers, resulting in incomplete test coverage, poor targeting, and difficulty in verifying the power-down safety of critical locations. It also struggles to cover critical code locations during firmware execution (such as erase, write, and cache refresh), leading to insufficient testing of critical exception handling logic and overlooking potential risks. Relying on manual or random power outages makes it difficult to systematically cover all important operational nodes, resulting in poor test repeatability, high time and effort consumption, and difficulty in reproducing faults in specific scenarios. Summary of the Invention
[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0005] To address the existing problems, this application provides a method for testing the fixed-point power loss of a memory chip, applied to a host computer, characterized in that the method includes: The host and device are obtained; the interaction protocol defines the host sending a power-down confirmation command to the device, and the host obtaining the status feedback from the device based on the power-down confirmation command. The host obtains the abnormal power failure response mechanism pre-built in the firmware of the device; when the abnormal power failure response mechanism is triggered, the host obtains the data ready signal of the device and sends the power failure confirmation command. Obtain the abnormal power failure meter pre-built in the firmware of the device. The abnormal power failure meter is generated based on multiple preset power failure points. The preset power failure points are set with the trigger entry of the abnormal power failure response mechanism. Based on the abnormal power failure meter, send an activation command to activate the abnormal power failure response mechanism corresponding to the target preset power failure point; Obtain the data ready signal sent by the device when the firmware runs to the target preset power-off point and triggers the abnormal power-off response mechanism; Send a specified power-down confirmation command to the device and obtain a specified status feedback from the device based on the specified power-down confirmation command; When the specified status feedback is power failure, a power-off operation is performed on the device; after the device is powered off, a preset abnormal power failure detection process is executed.
[0006] In one embodiment of this application, the execution of a preset abnormal power outage detection process includes: Power on the device and check if the device can start normally. After the device starts up normally, key data checks, device function integrity verification, and potential fault troubleshooting operations are performed.
[0007] In one embodiment of this application, the power failure confirmation command includes a command type and command parameters: The instruction type is used to identify whether the query instruction is a power failure related instruction; The instruction parameters include a target power-off point index, used to query whether the target preset power-off point meets the power-off conditions.
[0008] In one embodiment of this application, the activation instruction includes an instruction type and instruction parameters: The instruction type is used to identify whether the activation instruction is a power failure related instruction; The instruction parameters include a target power failure point index, which is used to activate the abnormal power failure response mechanism corresponding to the target preset power failure point, so that it can be triggered.
[0009] According to another aspect of this application, a method for fixed-point power-down testing of a memory chip is provided, applied to a device, characterized in that the method includes: The interaction protocol between the device and the host is obtained; the interaction protocol defines how the device obtains a power-down confirmation command sent by the host, and how the device replies with status feedback based on the power-down confirmation command; An abnormal power failure response mechanism is built into the firmware of the device; when the abnormal power failure response mechanism is triggered, a data ready signal is sent to the host, and the device waits for the host to send a power failure confirmation command. An abnormal power failure table is generated based on multiple preset power failure points in the firmware; wherein, the trigger entry point of the abnormal power failure response mechanism is set at the multiple preset power failure points in the firmware. When the firmware reaches the target preset power-down point, the abnormal power-down response mechanism is triggered, and the data ready signal is sent to the host. Obtain the power-down confirmation command sent by the host, and reply with the specified status feedback to the host according to the power-down confirmation command; The corresponding operation is executed according to the specified status feedback. When the specified status feedback is power failure, the system waits for the host to perform a power-off operation. When the specified status feedback is no power failure, the abnormal power failure response mechanism is exited, and the normal service execution of the firmware is restored.
[0010] In one embodiment of this application, the abnormal power failure meter includes a power failure confirmation command, an activation command, a power failure point index, a power failure point description, and power failure point triggering preconditions: The power outage confirmation command is used to query whether the preset power outage point meets the power outage conditions. The activation command is used to activate the abnormal power failure response mechanism corresponding to the preset power failure point, so that it can be triggered. The power-off point index is the number of the preset power-off point; The power-down point is described as the firmware code location information corresponding to the preset power-down point; The prerequisite for triggering the power failure point is the condition that the device must meet to reach the preset power failure point.
[0011] In one embodiment of this application, the status feedback includes power-off and no-power-off: When the status feedback is power failure, the device waits for the host to perform a power-off operation; When the status feedback indicates no power loss, the device terminates the abnormal power loss response mechanism and continues to execute subsequent firmware normal service code.
[0012] In one embodiment of this application, after sending a data ready signal to the host, the device enters an infinite loop waiting state, continuously listening for and waiting to receive a power-down confirmation command from the host, until it receives the power-down confirmation command and exits the infinite loop waiting state.
[0013] According to another aspect of this application, a storage medium is provided that stores a computer program, which, when executed by a processor, causes the processor to implement the above-described storage chip fixed-point power-down test method.
[0014] According to another aspect of this application, a storage medium is provided that stores a computer program, which, when executed by a processor, causes the processor to implement the above-described storage chip fixed-point power-down test method.
[0015] According to the memory chip fixed-point power-down testing method and storage medium provided by this invention, by embedding a trigger mechanism into the firmware's preset power-down point, power-down can be precisely controlled at specific code locations, ensuring targeted verification of exception handling logic and achieving accurate fixed-point testing. By systematically managing all power-down points to be tested through an abnormal power-down meter system, each preset scenario can be comprehensively and repeatedly tested, avoiding omissions and improving test coverage and repeatability. Through the combined design of preset power-down points, interaction protocols, and abnormal power-down meters, a controllable, repeatable, and fully covered fixed-point power-down testing system is constructed, significantly improving the efficiency and quality of reliability verification of memory chips under abnormal power-down scenarios. Attached Figure Description
[0016] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.
[0017] Figure 1 A schematic flowchart of a memory chip fixed-point power-down test method according to an embodiment of the present invention is shown; Figure 2 A schematic flowchart of a memory chip fixed-point power-down test method according to another embodiment of the present invention is shown; Figure 3 A schematic flowchart of a memory chip fixed-point power-down test method according to another embodiment of the present invention is shown; Figure 4 A structural block diagram of a storage medium according to an embodiment of the present invention is shown; Figure 5 A structural block diagram of a storage medium according to another embodiment of the present invention is shown. Detailed Implementation
[0018] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.
[0019] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0021] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.
[0022] To make the objectives, technical solutions, and advantages of this application more apparent, exemplary embodiments according to this application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein. Based on the embodiments of this application described herein, all other embodiments obtained by those skilled in the art without inventive effort should fall within the protection scope of this application.
[0023] In view of the aforementioned technical problems, this invention proposes a method for fixed-point power-down testing of memory chips, applied to host computers. Figure 1 , 3 A schematic flowchart of a memory chip fixed-point power-down test method according to an embodiment of the present invention is shown.
[0024] In step S100, the interaction protocol between the host and the device is obtained; the interaction protocol defines that the host sends a power-off confirmation command to the device, and the host obtains the status feedback from the device based on the power-off confirmation command.
[0025] In step S200, the abnormal power failure response mechanism pre-built in the firmware of the device is obtained; when the abnormal power failure response mechanism is triggered, the host obtains the data ready signal of the device and sends the power failure confirmation command.
[0026] In step S300, an abnormal power failure meter pre-built in the firmware of the device is obtained. The abnormal power failure meter is generated based on multiple preset power failure points, and the preset power failure points are set with the trigger entry of the abnormal power failure response mechanism.
[0027] In step S400, based on the abnormal power failure meter, an activation command is sent to activate the abnormal power failure response mechanism corresponding to the target preset power failure point.
[0028] In step S500, the data ready signal sent by the device when the firmware runs to the target preset power-off point and triggers the abnormal power-off response mechanism is obtained.
[0029] In step S600, a specified power-down confirmation command is sent to the device, and a specified status feedback is obtained from the device based on the specified power-down confirmation command.
[0030] In step S700, when the specified status feedback is power failure, a power-off operation is performed on the device; after the device is powered off, a preset abnormal power failure detection process is executed.
[0031] The memory chip fixed-point power-down testing method of this invention, by embedding a trigger mechanism into the firmware to preset power-down points, can precisely control power-down at specific code locations, ensuring targeted verification of exception handling logic and achieving accurate fixed-point testing. Through the systematic management of all power-down points to be tested using an abnormal power-down meter, each preset scenario can be comprehensively and repeatedly tested, avoiding omissions and improving test coverage and repeatability. Through the combined design of preset power-down points, interaction protocols, and abnormal power-down meters, a controllable, repeatable, and fully covered fixed-point power-down testing system is constructed, significantly improving the efficiency and quality of reliability verification of memory chips under abnormal power-down scenarios.
[0032] The host is the device that initiates storage operations, such as a mobile phone motherboard or a computer motherboard. The storage device is the storage hardware that responds to the host's instructions, including storage chips such as eMMC, UFS, SSD, and microcontrollers. eMMC (Embedded Multimedia Card) is an integrated embedded storage chip, essentially encapsulating the storage particles and control chip in a small chip, directly soldered onto the device's motherboard, and cannot be removed. UFS (Universal Flash Memory) is also embedded storage, but it uses a serial interface, significantly improving read and write speeds; it can be understood as high-speed embedded solid-state hardware. SSD (Solid State Drive) is an independent high-speed storage device, pluggable or fixedly installed, with storage capacity and read / write speeds far exceeding eMMC / UFS. A microcontroller (MCU, Microcontroller Unit) is the "brain" of an embedded device, an ultra-small computer chip integrating a CPU, memory, and peripheral interfaces (such as GPIO, UART, SPI), responsible for executing control logic and processing sensor data.
[0033] During a normal power outage, the system first stops all read and write commands, writes data from the cache to the flash memory, and updates critical metadata such as the FTL (Flash Translation Layer) to ensure the integrity of the data mapping. An abnormal power outage disrupts this process, leading to two core problems: 1. Loss of cached data: Temporary data to be written (such as data in memory cache or the device's built-in cache) is lost because it cannot be written to the flash memory in time. 2. Metadata corruption: The FTL records the mapping between logical addresses and physical flash blocks. An abnormal power outage may cause incomplete updates to the FTL table, resulting in minor issues like some data being unreadable, or even the entire storage device becoming unrecognizable.
[0034] The device is the core carrier of the test object, comprising three core components: storage media (such as NAND Flash), controller, and firmware running on the controller. The goal of the test is to verify whether the device's internal firmware can guarantee data integrity, prevent device damage, and meet data security requirements when encountering abnormal power loss at different execution stages (such as data writing, erasing, verification, cache refresh, etc.).
[0035] The different execution stages of firmware correspond to different operating states of data, metadata, and hardware status inside the storage device. Power failure at any stage may lead to risks such as data corruption and device failure, and the failure modes and impact of different power failure points vary greatly.
[0036] The differences in firmware execution phases determine the uneven distribution of power loss risks. The workflow of storage device firmware is not a single, continuous operation, but rather consists of multiple independent yet interconnected sub-phases, with vastly different consequences of power loss at different stages. Idle Phase: The device is not performing read / write operations; power loss typically only affects temporary caches, without permanent damage. Data Write Phase: This phase includes sub-steps such as cache data reception, NAND Flash programming, and metadata synchronization. If a power loss occurs when "data is already cached but not yet written to Flash," only temporary data is lost; if it occurs during "Flash programming," it may cause data corruption in the corresponding blocks; if it occurs during "metadata updates," it will damage the file system index, directly causing the device to be unable to recognize the stored data. Garbage Collection / Wear Leveling Phase: Firmware moves valid data and erases invalid blocks. Power loss at this stage is extremely prone to interrupting data migration, leading to data loss or block corruption. Only power loss testing covering all critical execution locations can fully expose the risks at different stages, avoiding the creation of hidden dangers due to overlooking a single power loss point.
[0037] The unpredictability of real-world power outages necessitates end-to-end verification. Abnormal power outages for end users (such as sudden power failures or battery depletion) occur randomly, making it impossible to predict which firmware stage the power outage occurred at. Testing only a few power outage points may miss potential risks during high-risk stages (such as metadata updates and garbage collection). These risks may not surface during routine laboratory testing but will manifest in real-world user scenarios, leading to issues like data loss, device unrecognizable features, and a sudden drop in device lifespan, severely impacting product reliability and user experience.
[0038] Verifying the fault-tolerant design of firmware logic relies on precise power-down point testing. To cope with abnormal power outages, firmware incorporates fault-tolerant mechanisms (such as power-down protection circuits, data verification, metadata backup, and breakpoint resume). The effectiveness of these fault-tolerant mechanisms must be verified at the corresponding power-down points: for example, whether the "metadata backup mechanism" can automatically restore the system to its pre-update state after a power outage during metadata updates; and whether the "breakpoint resume mechanism" can re-identify incomplete blocks and rewrite data after a "Flash programming interruption." Skipping the testing at a particular power-down point makes it impossible to confirm whether the corresponding fault-tolerant design is effective, rendering the fault-tolerant mechanism ineffective.
[0039] The current common practice is to randomly trigger external power outages on the host to randomly pinpoint the firmware's execution location. However, random power outage testing has limitations and is insufficient to support the verification of high-reliability storage devices.
[0040] First, high-risk power outages have a low probability of hitting the target. Critical risk phases in firmware (such as metadata updates, garbage collection, and critical moments for block erasure) typically have extremely short execution times. For example, metadata synchronization might only account for 1% of the entire read / write process. Random power outages are unlikely to accurately hit these phases, leading to the omission of critical vulnerabilities. Second, fault localization is difficult. If a device fails during testing, because the firmware code location corresponding to the power outage is random, it's difficult for developers to trace back what operations the firmware was performing at the time of the power outage, requiring significant additional time to reproduce and locate the root cause. Finally, test coverage cannot be quantified. Random testing lacks clear coverage targets and cannot answer the question, "Which execution phases of the firmware have been verified? Which haven't been covered?" Test completion relies entirely on the number of tests, resulting in low efficiency.
[0041] In the embodiments of this application, step S100 involves obtaining the interaction protocol between the host and the device; the interaction protocol defines how the host sends a power-down confirmation command to the device, and how the host obtains the status feedback from the device based on the power-down confirmation command.
[0042] The host and device have a master-slave collaborative relationship, interacting in an orderly manner through a pre-agreed protocol. The host is the controlling party in the communication, responsible for actively initiating commands and receiving and parsing device responses. The device is the controlled / responding party, responsible for receiving host commands, executing corresponding processing, and returning agreed-upon status data. The interaction protocol is not a general network protocol (such as TCP / IP), but rather a set of dedicated interaction rules customized for the specific scenario of abnormal power failure testing. Its core includes the following three key agreements: the structure of the power failure confirmation command, the data for status feedback, and the communication steps between the two parties.
[0043] In the embodiments of this application, the power failure confirmation instruction includes an instruction type and instruction parameters: the instruction type is used to identify the category of the query instruction as an abnormal power failure related instruction; the instruction parameters include a target power failure point index, used to query whether the target preset power failure point meets the power failure conditions.
[0044] The instruction type is used to distinguish instruction categories, essentially labeling instructions with functions. It tells the device which type of business logic the instruction belongs to, allowing the device to quickly identify the overall purpose of the instruction and avoid confusion with other function instructions. The instruction type can be customized as Cmd 60, which is a pre-agreed function identifier. Here, Cmd 60 specifically corresponds to the function of checking if the device will lose power, while Cmd 61 might be used to check the temperature.
[0045] Command parameters are used to subdivide specific functions within the same command category. They act as supplementary details under the function label, clearly indicating to the device which specific operation needs to be performed under that command category. Command parameters can be Arguments, and the power-down point index can be 0x01, 0x02, ..., 0xFF. In the Cmd 60 command type, different command parameter values distinguish different operational requirements. For example: Argument=0x01: represents "Activate power-down point 1 (data writing in progress)"; Argument=0x02: represents "Activate power-down point 2 (parameter configuration in progress)"; Argument=0xFF: represents "Inquire whether a power-down can be performed at present". Different arguments correspond to different sub-functions under the same instruction type. This eliminates the need to add more instruction types, enabling the differentiation of various related operations and simplifying the communication logic between the host and device. Power-down point indexing precisely locates the query target, ensuring the host can accurately obtain the power-down conditions for a specific power-down point and reducing instruction misjudgments.
[0046] After receiving the power failure confirmation command from the host, the device will first perform corresponding checks (such as checking its own power supply voltage, battery level, and whether the external power supply is stable), and then convert the check results into pre-agreed hexadecimal data and return them to the host. The core is to use simple binary / hexadecimal encoding to replace complex text descriptions, thereby improving communication efficiency (especially suitable for hardware communication scenarios).
[0047] For example, the status feedback returned by the device includes power off and no power off: when the status feedback returned by the device is power off, the host performs a power-off operation to disconnect the device at a preset power-off point; when the status feedback returned by the device is no power off, the host does not perform a power-off operation.
[0048] The core function of the device is to provide feedback on whether it is in a power-down ready state. Specifically, upon receiving a power-down confirmation command (Cmd 60 + dedicated Argument) from the host, it replies with a pre-defined status response based on its current state (whether it is truly ready and without anomalies). The status response can be 0xAA or 0xBB, where 0xBB represents power-down ready and 0xAA represents non-power-down ready. The host will only decide to perform a power-down operation after receiving the device's power-down ready feedback (0xBB); if it receives the device's non-power-down ready feedback (0xAA), the host will abandon the current power-down operation or wait for a later opportunity. Clearly defining the two feedback types (power-down / non-power-down) and their corresponding host operations creates a clear decision-making logic; it supports flexible control of power-down behavior based on the actual device state, avoiding forced power-down when the device does not meet the power-down conditions, and reducing unnecessary service interruptions and equipment damage.
[0049] In the embodiments of this application, in step S200, an abnormal power failure response mechanism pre-built in the firmware of the device is obtained; when the abnormal power failure response mechanism is triggered, the host obtains the data ready signal of the device and sends a power failure confirmation command.
[0050] After entering the abnormal power failure response mechanism, the device first actively sends a data ready signal to the host. The data ready signal can be "ready for data", which tells the host: "I have reached the designated position and can receive your power failure confirmation command. You can send the command type and command parameters now."
[0051] For example, after the device sends a data ready signal to the host, it waits in an infinite loop for a power-down confirmation command; when the device replies with a status indicating power failure based on the power-down confirmation command, the host performs a power-off operation; when the device replies with a status indicating no power failure based on the power-down confirmation command, the device exits the infinite loop waiting state and resumes normal firmware service execution.
[0052] After the device sends a data ready signal to the host, it then enters an infinite loop waiting state: at this time, the device will pause the execution of other normal business logic and only focus on listening to the instructions sent by the host. It will not continue to run the firmware code until the device hears the instruction type and instruction parameters sent by the host.
[0053] The device will determine the appropriate response based on the command parameters and then return either 0xAA (no power loss) or 0xBB (power loss) to the host according to the agreed-upon interaction protocol. If 0xBB is returned, the device will trigger a preset power-down process after receiving the feedback; if 0xAA is returned, the device will exit the infinite loop and resume normal firmware service execution. This infinite loop waiting mechanism ensures that the device can reliably receive power-down confirmation commands from the host, avoiding command omissions and guaranteeing the reliability of the interaction; the clearly defined exit logic after a "no power loss" feedback allows the device to quickly resume normal service execution, balancing testing needs with business continuity.
[0054] In the embodiments of this application, in step S300, an abnormal power failure meter pre-built in the firmware of the device is obtained. The abnormal power failure meter is generated based on multiple preset power failure points, and the preset power failure points are set with trigger entry points for the abnormal power failure response mechanism.
[0055] Preset power-down points refer to critical code execution phases or hardware operation nodes that R&D / testing personnel have pre-defined and prioritize for verification based on the firmware execution logic. These power-down points are not randomly selected but rather identified as high-risk, high-priority verification locations based on a deep breakdown of the firmware workflow. Power loss at these locations is most likely to cause serious problems such as data loss, device unrecognition, and block corruption. A jump code is added to each preset power-down point. When the firmware reaches this preset power-down point and it has already been activated, the abnormal power-down response mechanism is automatically triggered.
[0056] Common power-down points include: critical data operation nodes, critical metadata update nodes, and critical firmware state transition nodes. Critical data operation nodes include: the data write phase (when the cache has received host data but has not yet written it to the NAND Flash); and the moment when Flash programming is complete but the data mapping table has not been updated. The data erase phase (when the block erase command has been issued and the erase operation is halfway through). The data migration phase (during garbage collection, the moment when valid data is being moved from the old block to the new block). Metadata is the "index directory" of the storage device, recording core information such as the data storage location and block health status. Its update phase is the highest priority designated power-down point: the instant file system metadata (such as the FAT table and FTL mapping table) is written to the Flash; and the execution moment of updating the device partition table and firmware version information. Critical firmware state transition nodes include: the moment the device switches from idle mode to high-load read / write mode; the critical moment when the wear leveling algorithm starts / stops; and the transition moment when the device enters hibernation / wake-up.
[0057] The abnormal power failure meter is essentially a mapping table or lookup table, which is used by the host-side test logic for querying and applying. The trigger entry point is a location marker or function call in the firmware code. Here, the action performed by the device firmware is "prepare to receive instructions and enter a waiting loop".
[0058] Compared to random power-down testing, the core value of specified power-down point testing is its precise targeting of high-risk aspects. It solves the problem of low probability of random testing hitting critical nodes, ensuring that every high-risk power-down scenario is covered; it also makes it easier for developers to reproduce faults and locate root causes, because the power-down time is preset, and once a problem occurs, it can be directly correlated to a specific section of firmware code logic.
[0059] For example, the abnormal power loss meter includes a power loss confirmation command, an activation command, a power loss point index, a power loss point description, and power loss point triggering prerequisites: the power loss confirmation command is used to query whether the preset power loss point meets the power loss conditions; the activation command is used to activate the abnormal power loss response mechanism corresponding to the preset power loss point, so that it can be triggered; the power loss point index is the number of the preset power loss point; the power loss point description is the firmware code location information corresponding to the preset power loss point; and the power loss point triggering prerequisites are the conditions that the device needs to meet to reach the preset power loss point.
[0060] Establish a Power Loss Anomaly Table: A management table, or Power Loss Anomaly Table, is created for all preset power loss points with added abnormal power loss response mechanism entry points. The power loss point index is the power loss point's identification number, directly corresponding to the command parameters in the power loss confirmation command and activation command, used for precise matching of command interactions. The power loss point description clearly defines the device firmware code location / business scenario corresponding to the power loss point, facilitating testers' understanding of the test objectives. The power loss point description can include the different stages at which the code location of the power loss point is located, such as the NAND flash memory write stage, NAND flash memory recycling stage, table update stage, erase stage, hibernation stage, and read stage. The power loss point triggering preconditions describe what states / preliminary operations the device needs to meet in order to reach the power loss point.
[0061] The abnormal power outage meter can also include test priority and estimated time. Test priority indicates the importance of the power outage point, which facilitates test sequencing (e.g., P0 = core mandatory test, P1 = secondary sampling test); Example: P0 (core scenario of device storage, must be 100% covered by test). Estimated time records the approximate time for the test at this power outage point (including pre-operation + inspection process), which is helpful for test planning; Example: 2 minutes / test.
[0062] Abnormal power outage meters can standardize the core information of power outage points, forming a structured management carrier that facilitates quick querying and retrieval by the host; it enables precise binding of power outage points with triggering conditions and inspection processes, avoiding the problem of mismatch between testing processes and inspection requirements; it provides a foundation for batch testing and orderly scheduling of multiple power outage points, improving the systematic nature and manageability of testing.
[0063] In the embodiments of this application, in step S400, an activation command is sent to activate the abnormal power failure response mechanism corresponding to the target preset power failure point based on the abnormal power failure meter.
[0064] The power failure exception table records multiple different power failure points. Different test scenarios require verifying the exception recovery capabilities of different power failure points. The activation operation essentially selects the target power failure point to be verified in this test. Even if the code executes to a point where a power failure point is not activated, the exception power failure response mechanism will not be triggered, avoiding accidental triggering of irrelevant power failure points and ensuring the relevance of the test. The exception power failure response mechanism can only be triggered after it has been activated; if it is not activated, it cannot be triggered.
[0065] The default power-down point in the firmware is a hibernation state (not occupying system resources) and does not actively send a data ready signal. When subsequent firmware code executes to this activation power-down point, it will automatically enter the ready for data state, send a data ready signal, and begin to continuously wait for the host to send the agreed power-down confirmation command.
[0066] The host computer uses the abnormal power loss meter to identify the unique Cmd and Argument corresponding to each power loss point. The activation operation is a crucial signal from the host to the device to indicate that a specific power loss point needs to be tested. After receiving the activation command, the device records the index of the currently activated power loss point. Subsequently, when the firmware reaches that location and sends a "ready for data" signal, the host can accurately match the corresponding test procedure, avoiding communication chaos in scenarios with multiple power loss points and ensuring consistency in the interaction between the two parties.
[0067] The core of abnormal power outage testing is the expected anomaly. A power outage must be triggered only after the pre-defined test script has reached a specified stage to verify the functionality of the subsequent recovery logic. Without activation, any power outage point could be triggered, potentially causing an unintended power outage before the pre-defined test script reaches its intended stage, thus compromising the controllability of the test process. Activation adds permission verification to the power outage trigger; only activated power outage points meet the triggering conditions, ensuring the power outage operation executes within the expected rhythm of the test script.
[0068] The abnormal power loss meter is a configurable management method. Adding or modifying power loss points only requires updating the table, without changing the core firmware logic. The activation operation, as a key step in the configurable call, allows the host to flexibly select different power loss points for combined testing via scripts (such as activating multiple power loss points at once for batch verification, or switching between different power loss points according to scenarios), without re-flashing the firmware, which greatly improves testing efficiency and reduces the cost of firmware iteration and test maintenance.
[0069] In the embodiments of this application, the activation instruction includes an instruction type and instruction parameters: the instruction type is used to identify the category of the activation instruction as an abnormal power failure related instruction; the instruction parameters include a target power failure point index, which is used to activate the abnormal power failure response mechanism corresponding to the target preset power failure point so that it can be triggered.
[0070] The activation command marks the test target for the device, informing it at which power-down point it should wait for the power-down confirmation command, essentially reserving the power-down scenario in advance. The activation command has the same command type as the power-down confirmation command, but their command parameters differ. The meaning, timing, purpose, and device feedback of the command parameters are all different. Activation is the process by which the host sends a pre-agreed set of commands to the device, and the device, after receiving and parsing them, marks the corresponding power-down point as "activated."
[0071] The host sends specified command parameters, and the device marks the status of the corresponding power-down point within its firmware. Only when the firmware code executes to that power-down point will it first check the activation status of that power-down point: if it is "activated" (value = 1): a data ready signal is sent to the host, and then it waits in an infinite loop for the host's power-down confirmation command; if it is "inactive" (value = 0): normal firmware code execution continues. This ensures that the abnormal power-down response mechanism can only be triggered at the target power-down point, achieving on-demand activation and improving the targeting and accuracy of testing.
[0072] In the embodiments of this application, the data ready signal sent by the acquisition device in step S500 when the firmware runs to the target preset power-off point and triggers the abnormal power-off response mechanism is obtained.
[0073] For example, the host executes a preset test script to make the firmware run to a preset power-down point. The preset test script is an automated test script. This ensures that the firmware can stably and accurately reach the preset power-down point, improving the accuracy and repeatability of the test results.
[0074] For example, the abnormal power failure response mechanism is implemented in the device firmware as a separate task, an interrupt service routine, or a conditional loop. Multiple implementation methods are supported, allowing for flexible selection based on the firmware architecture without modifying the core firmware logic; this significantly improves the adaptability of the method, making it suitable for firmware testing scenarios of different types of memory chips and expanding its application scope.
[0075] In the embodiments of this application, in step S600, a specified power-down confirmation command is sent to the device, and a specified status feedback is obtained from the device based on the specified power-down confirmation command.
[0076] In the embodiments of this application, when the specified status feedback is power failure in step S700, a power-off operation is performed on the device; after the device is powered off, a preset abnormal power failure verification process is executed.
[0077] In the embodiments of this application, a preset abnormal power failure test process is executed, including: powering on the device and checking whether the device can start normally; after the device starts normally, performing key data checks, device functional integrity verification and potential fault troubleshooting operations.
[0078] After a power outage, the host computer executes a pre-defined abnormal power outage verification process. The core of this process is to verify whether the device's state after a sudden power failure meets expectations, ensuring product reliability. Common verification items include: powering the device back on and checking if it can start normally without crashes, errors, or other anomalies; checking critical data: such as whether data being written before the power outage is complete (or whether it follows preset error-tolerant rules, such as discarding incomplete data), and whether stored configuration parameters are not lost; verifying functional integrity: whether operations not completed before the power outage can be resumed normally after power-on, or whether abnormal states can be identified and the user notified; and troubleshooting potential faults: such as whether there are hidden problems like flash memory damage or register data corruption. The verification process is clearly structured with layered verification logic (startup status, critical data, functional integrity, and potential faults), achieving a comprehensive evaluation from startup capability to overall performance.
[0079] The test results for power loss points at different stages are as follows: 1. During data writing, if power is lost before updating the mapping table, power-on must ensure that device data may be lost; if power is lost during updating the mapping table, power-on must ensure that device data is not lost; if power is lost after updating the mapping table, power-on must ensure that device data is not lost. 2. During data writing, if power is lost after writing to the NAND chip, power-on must ensure that device data is not lost; if power is lost during writing to the NAND chip, power-on must ensure that device data is not lost; if power is lost before writing to the NAND chip, power-on must ensure that device data is not lost. 3. During data reading, if power is lost after reading from the NAND chip, power-on must ensure that device data is not lost; if power is lost during reading from the NAND chip, power-on must ensure that device data is not lost; if power is lost before reading from the NAND chip, power-on must ensure that device data is not lost.
[0080] The memory chip fixed-point power-down testing method of this invention, by embedding a trigger mechanism into the firmware to preset power-down points, can precisely control power-down at specific code locations, ensuring targeted verification of exception handling logic and achieving accurate fixed-point testing. Through the systematic management of all power-down points to be tested using an abnormal power-down meter, each preset scenario can be comprehensively and repeatedly tested, avoiding omissions and improving test coverage and repeatability. Through the combined design of preset power-down points, interaction protocols, and abnormal power-down meters, a controllable, repeatable, and fully covered fixed-point power-down testing system is constructed, significantly improving the efficiency and quality of reliability verification of memory chips under abnormal power-down scenarios.
[0081] Please see Figure 4As shown, this embodiment also proposes a computer-readable storage medium 4, which stores computer instructions 40 for using the fixed-point power-down test method of the storage chip. The computer-readable storage medium 4 can be an electronic medium, magnetic medium, optical medium, electromagnetic medium, infrared medium, or semiconductor system or propagation medium. The computer-readable storage medium 4 can also include semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and optical disk. Optical disks can include optical disc-read-only memory (CDROM), optical disc-read / write (CD-RW), and DVD.
[0082] This invention proposes a method for testing the fixed-point power loss of memory chips, applicable to equipment. Figure 2 , 3 A schematic flowchart of a memory chip fixed-point power-down test method according to another embodiment of the present invention is shown.
[0083] In step S100', the interaction protocol between the device and the host is obtained; the interaction protocol defines the device's receipt of the power-down confirmation command sent by the host, and the device's response status feedback based on the power-down confirmation command.
[0084] In step S200', an abnormal power failure response mechanism is built in the device firmware; when the abnormal power failure response mechanism is triggered, a data ready signal is sent to the host, and the device waits for the host to send a power failure confirmation command.
[0085] In step S300', an abnormal power failure table is generated based on multiple preset power failure points in the firmware; wherein, the trigger entry of the abnormal power failure response mechanism is set at multiple preset power failure points in the firmware.
[0086] In step S400', when the firmware runs to the target preset power-off point, it triggers the abnormal power-off response mechanism and sends a data ready signal to the host.
[0087] In step S500', the power-down confirmation command sent by the host is obtained, and the specified status feedback is replied to the host according to the power-down confirmation command.
[0088] In step S600', the corresponding operation is executed according to the specified status feedback. When the specified status feedback is power failure, wait for the host to perform a power-off operation; when the specified status feedback is no power failure, exit the abnormal power failure response mechanism and restore the normal service execution of the firmware.
[0089] In the embodiments of this application, the interaction protocol between the device and the host is obtained in step S100'; the interaction protocol defines the device obtaining the power-down confirmation command sent by the host, and the device replying with status feedback based on the power-down confirmation command.
[0090] For example, the power failure confirmation instruction includes an instruction type and instruction parameters: the instruction type is used to identify the category of the query instruction as an abnormal power failure related instruction; the instruction parameters include the target power failure point index, which is used to query whether the target preset power failure point meets the power failure conditions.
[0091] In the embodiments of this application, the status feedback includes power failure and no power failure: when the status feedback is power failure, the device waits for the host to perform a power-off operation; when the status feedback is no power failure, the device terminates the abnormal power failure response mechanism and continues to execute subsequent firmware normal business code.
[0092] In the embodiments of this application, step S200' involves constructing an abnormal power failure response mechanism within the device's firmware; when the abnormal power failure response mechanism is triggered, a data ready signal is sent to the host, and the system waits for the host to send a power failure confirmation command.
[0093] In the embodiments of this application, after sending a data ready signal to the host, the device enters an infinite loop waiting state, continuously listening for and waiting to receive a power-down confirmation command from the host, until it receives the power-down confirmation command and then exits the infinite loop waiting state.
[0094] In the embodiments of this application, an abnormal power failure meter is generated in step S300' based on multiple preset power failure points in the firmware; wherein, the trigger entry of the abnormal power failure response mechanism is set at multiple preset power failure points in the firmware.
[0095] In the embodiments of this application, the abnormal power failure meter includes a power failure confirmation command, an activation command, a power failure point index, a power failure point description, and power failure point triggering prerequisites: the power failure confirmation command is used to query whether a preset power failure point meets the power failure conditions; the activation command is used to activate the abnormal power failure response mechanism corresponding to the preset power failure point, so that it can be triggered; the power failure point index is the number of the preset power failure point; the power failure point description is the firmware code location information corresponding to the preset power failure point; and the power failure point triggering prerequisites are the conditions that the device needs to meet to reach the preset power failure point.
[0096] In the embodiments of this application, when the firmware runs to the target preset power-down point in step S400', the abnormal power-down response mechanism is triggered, and a data ready signal is sent to the host.
[0097] For example, the host sends an activation command based on the abnormal power failure meter to activate the abnormal power failure response mechanism corresponding to the preset power failure point. The activation command includes a command type and command parameters: the command type is used to identify the category of the activation command as an abnormal power failure related command; the command parameters include the target power failure point index, which is used to activate the abnormal power failure response mechanism corresponding to the target preset power failure point so that it can be triggered.
[0098] In the embodiments of this application, in step S500', the host sends a power-down confirmation instruction, and the host is replied with a specified status feedback according to the power-down confirmation instruction.
[0099] In the embodiments of this application, in step S600', the corresponding operation is performed according to the specified status feedback. When the specified status feedback is power failure, the host is waited to perform a power-off operation; when the specified status feedback is no power failure, the abnormal power failure response mechanism is exited and the normal service execution of the firmware is restored.
[0100] For example, the host performs a power-off operation and executes a preset abnormal power-off test process, including: the host powers on the device and checks whether the device can start normally; after the device starts normally, it checks key data, verifies the integrity of functions, and troubleshoots potential faults.
[0101] Please see Figure 5 As shown, this embodiment also proposes a computer-readable storage medium 5, which stores computer instructions 50 for using the fixed-point power-down test method of the storage chip. The computer-readable storage medium 5 can be an electronic medium, magnetic medium, optical medium, electromagnetic medium, infrared medium, or semiconductor system or propagation medium. The computer-readable storage medium 5 can also include semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and optical disk. Optical disks can include optical disc-read-only memory (CDROM), optical disc-read / write (CD-RW), and DVD.
[0102] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. A method for testing the fixed-point power loss of a memory chip, applied to a host computer, characterized in that, The method includes: The host and device are obtained; the interaction protocol defines the host sending a power-down confirmation command to the device, and the host obtaining the status feedback from the device based on the power-down confirmation command. The host obtains the abnormal power failure response mechanism pre-built in the firmware of the device; when the abnormal power failure response mechanism is triggered, the host obtains the data ready signal of the device and sends the power failure confirmation command. Obtain the abnormal power failure meter pre-built in the firmware of the device. The abnormal power failure meter is generated based on multiple preset power failure points. The preset power failure points are set with the trigger entry of the abnormal power failure response mechanism. Based on the abnormal power failure meter, send an activation command to activate the abnormal power failure response mechanism corresponding to the target preset power failure point; Obtain the data ready signal sent by the device when the firmware runs to the target preset power-off point and triggers the abnormal power-off response mechanism; Send a specified power-down confirmation command to the device and obtain a specified status feedback from the device based on the specified power-down confirmation command; When the specified status feedback is power failure, a power-off operation is performed on the device; after the device is powered off, a preset abnormal power failure detection process is executed.
2. The test method as described in claim 1, characterized in that, The execution of the preset abnormal power outage detection process includes: Power on the device and check if the device can start normally. After the device starts up normally, key data checks, device function integrity verification, and potential fault troubleshooting operations are performed.
3. The test method as described in claim 1, characterized in that, The power failure confirmation command includes a command type and command parameters: The instruction type is used to identify whether the query instruction is a power failure related instruction; The instruction parameters include a target power-off point index, used to query whether the target preset power-off point meets the power-off conditions.
4. The test method as described in claim 1, characterized in that, The activation instruction includes an instruction type and instruction parameters: The instruction type is used to identify whether the activation instruction is a power failure related instruction; The instruction parameters include a target power failure point index, which is used to activate the abnormal power failure response mechanism corresponding to the target preset power failure point, so that it can be triggered.
5. A method for testing the fixed-point power loss of a memory chip, applied to a device, characterized in that, The method includes: The interaction protocol between the device and the host is obtained; the interaction protocol defines how the device obtains a power-down confirmation command sent by the host, and how the device replies with status feedback based on the power-down confirmation command; An abnormal power failure response mechanism is built into the firmware of the device; when the abnormal power failure response mechanism is triggered, a data ready signal is sent to the host, and the device waits for the host to send a power failure confirmation command. An abnormal power failure table is generated based on multiple preset power failure points in the firmware; wherein, the trigger entry point of the abnormal power failure response mechanism is set at the multiple preset power failure points in the firmware. When the firmware reaches the target preset power-down point, the abnormal power-down response mechanism is triggered, and the data ready signal is sent to the host. Obtain the power-down confirmation command sent by the host, and reply with the specified status feedback to the host according to the power-down confirmation command; The corresponding operation is executed according to the specified status feedback. When the specified status feedback is power failure, the system waits for the host to perform a power-off operation. When the specified status feedback is no power failure, the abnormal power failure response mechanism is exited, and the normal service execution of the firmware is restored.
6. The test method as described in claim 5, characterized in that, The abnormal power failure meter includes a power failure confirmation command, an activation command, a power failure point index, a power failure point description, and preconditions for triggering the power failure point: The power outage confirmation command is used to query whether the preset power outage point meets the power outage conditions. The activation command is used to activate the abnormal power failure response mechanism corresponding to the preset power failure point, so that it can be triggered. The power-off point index is the number of the preset power-off point; The power-down point is described as the firmware code location information corresponding to the preset power-down point; The prerequisite for triggering the power failure point is the condition that the device must meet to reach the preset power failure point.
7. The test method as described in claim 5, characterized in that, The status feedback includes power failure and no power failure: When the status feedback is power failure, the device waits for the host to perform a power-off operation; When the status feedback indicates no power loss, the device terminates the abnormal power loss response mechanism and continues to execute subsequent firmware normal service code.
8. The test method as described in claim 5, characterized in that, After sending a data ready signal to the host, the device enters an infinite loop waiting state, continuously listening for and waiting to receive a power-down confirmation command from the host, until it receives the power-down confirmation command and then exits the infinite loop waiting state.
9. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, causes the processor to implement the memory chip fixed-point power-down test method as described in any one of claims 1 to 4.
10. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, causes the processor to implement the memory chip fixed-point power-down test method as described in any one of claims 5 to 8.