Semiconductor package structure
By folding the lead frame extension to the top surface of the wafer and exposing it to the outside air in the semiconductor packaging structure, the problem of low heat dissipation efficiency in the prior art is solved, and a more efficient heat dissipation effect is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHIPMOS TECH INC
- Filing Date
- 2025-02-18
- Publication Date
- 2026-06-05
Smart Images
Figure CN122161460A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a packaging structure, and more particularly to a semiconductor packaging structure. Background Technology
[0002] As the functionality and performance of electronic products continue to improve, the number of input / output (I / O) ports on semiconductor chips is also constantly increasing. When semiconductor chips are encapsulated in encapsulant, a large amount of heat generated during chip operation accumulates within the encapsulant and is difficult to dissipate, potentially leading to electrical abnormalities or failures in the semiconductor package structure. Currently, the most common heat dissipation mechanism for semiconductor packages is to add heat sinks or thermal pads to the outside of the package. However, heat sinks / pads do not directly contact the heat source (chip), limiting their heat dissipation effectiveness. Therefore, improving heat dissipation efficiency is one of the issues that engineers in related fields are eager to research. Summary of the Invention
[0003] This invention relates to a semiconductor packaging structure that can effectively improve heat dissipation efficiency.
[0004] The semiconductor packaging structure of the present invention includes a leadframe, a first wafer, and an encapsulating agent. The leadframe includes a wafer carrier, a plurality of pins, and at least one extension. The wafer carrier has two first sides opposite to each other and two second sides opposite to each other. The plurality of pins are spaced apart adjacent to the two second sides of the wafer carrier. The at least one extension connects to at least one of the two first sides of the wafer carrier. The first wafer is disposed on the wafer carrier and electrically connected to the pins. The first wafer has a first top surface remote from the wafer carrier and two first side surfaces corresponding to the two first sides. The at least one extension includes a first segment and a second segment. The first segment connects to at least one of the two first sides of the wafer carrier and is parallel to the two first side surfaces of the first wafer. The second segment connects to the first segment and extends to and is disposed on the first top surface. The encapsulating agent covers the first wafer and the leadframe and exposes the upper surface of the second segment of the at least one extension.
[0005] Based on the above, in the semiconductor packaging structure of the present invention, the lead frame has at least one extension connecting at least one of two opposite sides of the wafer carrier. The extension is folded upward so that its second section extends to and is disposed on the top surface of the wafer, while the encapsulant covers the wafer and the lead frame and exposes the upper surface of the second section of the extension. Thus, the wafer can directly conduct heat to the outside air through the extension disposed on its top surface, significantly improving the heat dissipation performance of the semiconductor packaging structure. Attached Figure Description
[0006] Figure 1 This is a three-dimensional schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention;
[0007] Figure 2A yes Figure 1 A perspective view of a semiconductor packaging structure;
[0008] Figure 2B yes Figure 1 A cross-sectional schematic diagram of a semiconductor packaging structure;
[0009] Figure 3 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention;
[0010] Figures 4A to 4F yes Figure 1 A schematic diagram of the semiconductor packaging structure fabrication process;
[0011] Figure 5A and Figure 5B This is a schematic diagram of the lead frame unit of a semiconductor packaging structure according to an embodiment of the present invention before and after the extension is bent;
[0012] Figure 5C yes Figure 5A and Figure 5B A cross-sectional schematic diagram of a semiconductor packaging structure;
[0013] Figure 6A and Figure 6B This is a schematic diagram of the lead frame unit of a semiconductor packaging structure according to an embodiment of the present invention before and after the extension is bent;
[0014] Figure 7 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention.
[0015] Explanation of reference numerals in the attached figures
[0016] 20, 20A, 20B: Conductor frame unit
[0017] 30: Connecting strip
[0018] 100, 100A, 100B, 100C: Semiconductor package structure
[0019] 110: Conductor frame
[0020] 111: Chip carrier
[0021] 112: Pin
[0022] 113, 113A, 113B, 113C: Extensions
[0023] 120, 120A, 120B, 120C: First chip
[0024] 121, 121A, 121B: First top surface
[0025] 122: First side surface
[0026] 124: First base
[0027] 130, 130': Encapsulating colloid
[0028] 140: Conductor
[0029] 150: Adhesive layer
[0030] 160: Second chip
[0031] 170: Colloid
[0032] 180: Conductive material layer
[0033] G1: Gap
[0034] L1: First Section
[0035] L2, L2a: Second section
[0036] L21, L21a, L21b: Upper surface
[0037] L22, L22a: Lower surface
[0038] LF: Conductor support bar
[0039] P1, P2: Connecting pads
[0040] P3: Bump
[0041] S1: First side
[0042] S2: Second side Detailed Implementation
[0043] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.
[0044] The directional terms used herein (e.g., up, down, right, left, front, back, top, bottom) are for reference only and are not intended to imply absolute orientation. Unless otherwise expressly stated, no method described herein is intended to be construed as requiring the steps to be performed in a particular order.
[0045] The invention is described more fully with reference to the accompanying drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, dimensions, or size of layers or regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.
[0046] Figure 1This is a three-dimensional schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention. Figure 2A yes Figure 1 A perspective view of a semiconductor packaging structure. Figure 2B yes Figure 1 A cross-sectional schematic diagram of a semiconductor package structure. It should be noted that... Figure 2A The encapsulating colloid is shown with dashed lines to clearly indicate its internal components. Figure 2B The main components to be illustrated are shown only schematically, and the pads and conductive material layers are omitted.
[0047] Please refer to Figures 1 to 2B The semiconductor packaging structure 100 of this embodiment includes a lead frame 110, a first wafer 120, and an encapsulating colloid 130. The lead frame 110 includes a wafer carrier 111, a plurality of pins 112, and at least one extension 113.
[0048] In this embodiment, the wafer carrier 111 has two first sides S1 opposite to each other and two second sides S2 opposite to each other. Pins 112 are adjacent to the two second sides S2 of the wafer carrier 111 and are spaced apart from each other.
[0049] In this embodiment, the first chip 120 is disposed on the chip carrier 111 and electrically connected to the pin 112. The first chip 120 can be fixed to the chip carrier 111 by an adhesive layer 150, wherein the adhesive layer 150 is, for example, epoxy resin, silver paste, die bond film (DAF) or other suitable encapsulation material, and the present invention is not limited thereto.
[0050] In this embodiment, the first wafer 120 has a first top surface 121 located away from the wafer carrier 111. The first wafer 120 is electrically connected to pins 112 via wires 140. Specifically, the first top surface 121 of the first wafer 120 has a plurality of pads P1, which are arranged along the two edges of the first top surface 121 corresponding to the two second sides S2. The first wafer 120 is electrically connected to the pads P1 to the pins 112 via multiple wires 140. The material of the wires 140 is, for example, gold, copper, or other suitable conductive materials, and is not limited thereto. In other embodiments, solder balls or bumps may also be used as the means of electrical connection. For example, Figure 3 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention. Please refer to... Figure 3 In one embodiment, the first chip 120A has a first bottom surface 124 relative to the first top surface 121A. The first bottom surface 124 has a plurality of pads P2. The pads P2 are arranged along the two edges of the first bottom surface 124 corresponding to the two second sides S2. The first chip 120 is electrically connected to the pads P2 to the pins 112 through a plurality of bumps P3, but the present invention is not limited thereto.
[0051] Please continue to refer to this. Figure 2A At least one extension 113 connects to at least one of the two first sides S1 of the wafer carrier 111. In this embodiment, there are two extensions 113, and the two extensions 113 are respectively connected to the two first sides S1 of the wafer carrier 111. However, the invention is not limited thereto. In other embodiments not shown, there may be only one extension 113, that is, a single extension 113 connects to one of the two first sides S1 of the wafer carrier 111. Here, the extension 113 and the wafer carrier 111 are integrally formed, and the material of the lead frame 110 is, for example, metal or metal alloy, such as copper or copper alloy, but is not limited thereto.
[0052] In detail, in this embodiment, the first wafer 120 has two first side surfaces 122 corresponding to the two first sides S1. The extension 113 includes a first section L1 and a second section L2. The first section L1 is connected to the first side S1 of the wafer carrier 111 and is parallel to the first side surface 122 of the first wafer 120. The second section L2 is connected to the first section L1 and extends to and is disposed on the first top surface 121 of the first wafer 120. In detail, the extension 113 is formed by folding upward from the first side S1 of the wafer carrier 111 to form the first section L1, and then further bending to form the second section L2 disposed on the first top surface 121 of the first wafer 120.
[0053] In this embodiment, the orthographic projection of the second section L2 of the extension 113 onto the first top surface 121 does not overlap with the pad P1, so as to avoid affecting the wire bonding operation or damaging the wire 140, but the present invention is not limited thereto.
[0054] Please refer to Figure 2B In this embodiment, the second section L2 of the extension 113 has a lower surface L22 relative to the upper surface L21. The lower surface L22 directly contacts the first top surface 121 of the first wafer 120 so that the heat of the first wafer 120 can be directly transferred to the second section L2 of the extension 113 to improve the heat dissipation efficiency. However, the present invention is not limited thereto.
[0055] Furthermore, in this embodiment, the encapsulating colloid 130 covers the first wafer 120 and the lead frame 110, exposing an upper surface L21 of the second segment L2 of the extension 113. That is, the upper surface L21 of the bent extension 113 can be exposed outside the semiconductor package structure 100. In this way, by using a lead frame 110 with high thermal conductivity, such as a copper lead frame with a thermal conductivity of approximately 394 W / m•K, to contact the first wafer 120, the heat generated during the operation of the first wafer 120 is directly conducted to the outside air, significantly improving the heat dissipation performance of the semiconductor package structure 100.
[0056] For further explanation, please refer to Figure 1 and Figure 2A In this embodiment, the encapsulating colloid 130 further exposes the bottom surface and one side surface of each pin 112, and the semiconductor package structure 100 further includes a conductive material layer 180, at least disposed on the bottom surface of each pin 112, for external connection of the semiconductor package structure 100, but the present invention is not limited thereto. In other embodiments not shown, the conductive material layer 180 may also be further disposed on the side surface of each pin 112 exposed outside the encapsulating colloid 130. Here, the semiconductor package structure 100 is, for example, a dual flat no-lead (DFN) package structure with a small package area, but is not limited thereto.
[0057] Figures 4A to 4F yes Figure 1 A schematic diagram of the semiconductor packaging structure fabrication process is shown. Regarding the fabrication method of the semiconductor packaging structure in this embodiment, please first refer to... Figure 4A A leadframe strip LF is provided. Here, the leadframe strip LF has multiple leadframe units 20 and multiple connecting strips 30 connecting the leadframe units 20. Each leadframe unit 20 includes a wafer carrier 111, multiple pins 112, and two extensions 113. The wafer carrier 111 and multiple pins 112 of each leadframe unit 20 are connected to the connecting strips 30 to be held on the leadframe strip LF. The leadframe units 20 of the leadframe strip LF are arranged in a matrix and separated by the connecting strips 30, for example. It should be noted that the leadframe strip LF shown here is only schematically depicting the upper right portion of the overall leadframe strip LF, and its actual size is not limited thereto. Furthermore, in this embodiment, each extension 113 of each leadframe unit 20 is a rectangular sheet, but the present invention does not limit the shape of the extension 113.
[0058] Next, please refer to Figure 4B Multiple first wafers 120 are respectively fixed to wafer carriers 111 of multiple lead frame units 20. Next, please refer to Figure 4C The first wafer 120 is electrically connected to pins 112 spaced apart on the two second sides S2 of the wafer carrier 111 via wire bonding. Next, please refer to... Figure 4D The two extensions 113 of the two first sides S1 of the connected chip carrier 111 are folded upward so that they extend to and are disposed on the first top surface 121 of the first chip 120.
[0059] Next, please refer to Figure 4EThe encapsulation process involves molding and potting to inject the encapsulating colloid 130 into the leadframe strip LF. In this embodiment, the encapsulating colloid 130 covers the first wafer 120 and the leadframe unit 20, exposing the upper surface L21 of the second segment L2 on the first top surface 121 where each extension 113 extends. In this embodiment, the encapsulating colloid 130 covers all leadframe units 20 on its entire surface; however, in other embodiments, please refer to... Figure 4E' The encapsulating colloid 130' can also cover each leadframe unit 20 separately. Next, the molded leadframe strip LF undergoes a monomerization process; please refer to [reference needed]. Figure 4F This forms an independent semiconductor package structure 100. Specifically, the monomerization process can be carried out in different ways depending on the molding form, for example, for... Figure 4E The full-face molding form can be divided using a cutting tool (sawn type); while for Figure 4E' For individual molded forms, punching can be used for segmentation.
[0060] Other embodiments will be listed below for illustration. It must be noted that the following embodiments use the component reference numerals and some content from the foregoing embodiments, with the same reference numerals representing the same or similar components, and descriptions of identical technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.
[0061] Figure 5A and Figure 5B This is a schematic diagram of the lead frame unit of a semiconductor packaging structure according to an embodiment of the present invention before and after bending the extension portion. Figure 5C yes Figure 5A and Figure 5B A cross-sectional schematic diagram of a semiconductor package structure. Please also refer to... Figure 4A and Figure 5A In this embodiment, each conductor frame unit 20A and Figure 4A The main difference between the various leadframe units 20 is that the extension 113A of a first side S1 of the wafer carrier 111 connecting each leadframe unit 20A includes two strip-shaped rectangular sheets. In other embodiments, the number of sheets in a single extension may be appropriately adjusted according to actual needs, and the present invention is not limited thereto.
[0062] In this embodiment, the extension 113A is folded upward and extends to and is disposed on the first top surface 121 of the first wafer 120, such as... Figure 5B As shown. Next, after forming the encapsulating colloid 130 and performing monomerization, the desired result can be obtained as shown. Figure 5C The semiconductor package structure shown is 100A. It should be noted that... Figure 5C The semiconductor packaging structure 100A and Figure 4F Another difference in the semiconductor packaging structure 100A of this embodiment is that the second segment L2a of the extension 113A has an upper surface L21a and a lower surface L22a, wherein the lower surface L22a of the second segment L2a and the first top surface 121 of the first wafer 120 have a gap G1. The second segment L2a of the extension 113A and the first top surface 121 can be connected to each other by a colloid 170 disposed in the gap G1, wherein the colloid 170 can be selected from a film, an underfill, a thermally conductive adhesive, or an encapsulating adhesive 130, and the present invention is not limited thereto. Compared with a large-width monolithic rectangular sheet, the multiple strip-shaped rectangular sheets in this embodiment make it easier to bend the extension.
[0063] Figure 6A and Figure 6B This is a schematic diagram of the lead frame unit of a semiconductor packaging structure according to an embodiment of the present invention before and after bending the extension portion. Figure 6A and Figure 6B The conductor frame unit 20B and Figure 4A and Figure 4B The main difference between the leadframe unit 20 and the other is that the rectangular sheet body of the extension 113B of the wafer carrier 111 connecting each leadframe unit 20B on one of the first sides S1 has two through holes H1, but is not limited thereto. In this embodiment, the first wafer 120B is a large-size die, such as... Figure 6B As shown, the width of the first chip 120B is greater than the width of the chip carrier 111, and it partially spans the pin 112. To improve heat dissipation efficiency, the extension 113B is also widened to match the size of the first chip 120B. However, the widened, monolithic rectangular extension 113B increases the difficulty of bending. In this embodiment, by forming a through hole H1 in the rectangular body of the extension 113B, the structural strength at the bending point is weakened, allowing the extension 113B to be bent smoothly despite its increased size.
[0064] Figure 7 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention. Please refer to... Figure 7 In this embodiment, the semiconductor package structure 100C and Figure 2B The semiconductor package structure 100C differs slightly, primarily in that it includes a second chip 160. The second chip 160 is positioned between the chip carrier 111 and the first chip 120C, and is electrically connected to pins 112. In this way, by contacting the first chip 120C through the extension 113C, heat from the heat source (the first chip 120C and the second chip 160) can be directly conducted to the outside air, effectively improving the heat dissipation efficiency of the semiconductor package structure 100C.
[0065] In summary, in the semiconductor packaging structure of the present invention, the lead frame has at least one extension connecting at least one of two opposite sides of the wafer carrier. The extension is folded upward so that its second section extends to and is disposed on the top surface of the wafer, while the encapsulant covers the wafer and the lead frame, exposing the upper surface of the second section of the extension. Thus, the wafer can directly conduct heat to the outside air through the extension disposed on its top surface, significantly improving the heat dissipation performance of the semiconductor packaging structure.
[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A semiconductor packaging structure, characterized in that, include: Conductor frame, including: The wafer carrier has two first sides facing each other and two second sides facing each other; Multiple pins are arranged at intervals adjacent to the two second sides of the wafer carrier; and At least one extension is connected to at least one of the two first sides of the wafer carrier; A first wafer, disposed on the wafer carrier and electrically connected to the plurality of pins, has a first top surface remote from the wafer carrier and two first side surfaces corresponding to the two first sides. The at least one extension includes a first segment and a second segment. The first segment connects to at least one of the two first sides of the wafer carrier and is parallel to the two first side surfaces of the first wafer. The second segment connects to the first segment and extends to and is disposed on the first top surface. An encapsulating colloid covers the first wafer and the lead frame, exposing the upper surface of the second segment of the at least one extension.
2. The semiconductor packaging structure according to claim 1, characterized in that, The second section of the at least one extension has a lower surface relative to the upper surface, the lower surface being in direct contact with the first top surface.
3. The semiconductor packaging structure according to claim 1, characterized in that, The second section of the at least one extension has a lower surface relative to the upper surface, and the lower surface has a gap with the first top surface.
4. The semiconductor packaging structure according to claim 3, characterized in that, The second section of the at least one extension is interconnected with the first top surface by an adhesive disposed in the gap, wherein the adhesive may be selected from an adhesive film, an underfill adhesive, a thermally conductive adhesive, or the encapsulating adhesive.
5. The semiconductor packaging structure according to claim 1, characterized in that, The first top surface of the first wafer has a plurality of pads, which are arranged along the two edges of the first top surface corresponding to the two second sides. The first wafer is electrically connected to the plurality of pads to the plurality of pins via a plurality of wires.
6. The semiconductor packaging structure according to claim 5, characterized in that, The orthographic projection of the second segment of the at least one extension onto the first top surface does not overlap the plurality of pads.
7. The semiconductor packaging structure according to claim 1, characterized in that, The first wafer has a first bottom surface relative to the first top surface, the first bottom surface having a plurality of pads arranged along the two edges of the first bottom surface corresponding to the two second sides, and the first wafer electrically connecting the plurality of pads to the plurality of pins via a plurality of bumps.
8. The semiconductor packaging structure according to claim 1 further includes a second wafer disposed between the wafer carrier and the first wafer, and electrically connected to the plurality of pins.
9. The semiconductor packaging structure according to claim 1, characterized in that, The at least one extension includes at least one rectangular sheet.
10. The semiconductor packaging structure according to claim 9, characterized in that, The at least one rectangular sheet has at least one through hole.