A PCB circuit online test fault node positioning method based on a time sequence diagram convolution network

Abstract

This invention relates to the field of PCB circuits and discloses a method for online testing and fault node localization of PCB circuits based on a timing graph convolutional network. The method includes mapping components to graph nodes and electrical connections between components to graph edges according to the PCB circuit design documents, constructing a graph structure representation of the PCB circuit. Timing signal data of each node under normal and fault conditions are collected using online testing equipment. The timing data is normalized to fill in missing information in the graph structure. If there are outliers, the timing data of the corresponding node is re-collected. The preprocessed graph structure and timing data are then input into the timing graph convolutional network. This invention achieves automated fault node localization, significantly improving localization efficiency and reducing the time and labor costs of manual troubleshooting. It solves the problems of low efficiency, low accuracy, and inability to meet the increasingly complex fault diagnosis needs of existing fault localization methods.

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