Automatic zeroing circuit and method for mass flow controller
By using an automatic zero-adjustment circuit and method, the zero-point drift problem of the mass flow controller was solved, achieving a fully automated and high-precision zero-adjustment effect, adapting to different sensors and scenarios, and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU RUIBAO ELECTRONIC TECH CO LTD
- Filing Date
- 2026-06-04
- Publication Date
- 2026-07-03
AI Technical Summary
In the existing technology, the sensors of mass flow controllers have a zero drift problem, which results in low zero adjustment accuracy and cannot be automated. Traditional zero adjustment methods are time-consuming and labor-intensive or cannot effectively eliminate drift.
An automatic zero-adjustment circuit is adopted, including a zero-adjustment enable signal generation unit, a start clock signal generation unit, a sensor signal zero-point judgment unit, a counter analog-to-digital converter unit, and a compensation voltage real-time adjustment unit. Automatic compensation is achieved by controlling the counter chip and R-2R network through analog signals.
It achieves fully automated zeroing, improves zeroing accuracy, preserves dynamic range, suppresses slow drift, adapts to different sensors and scenarios, and is low-cost and stable.
Smart Images
Figure CN122331633A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of instrumentation technology, and specifically to an automatic zeroing circuit and method for a mass flow controller. Background Technology
[0002] In instrumentation and precision measurement systems, sensors (such as pressure sensors, temperature sensors, strain gauges, etc.) and their pre-conditioning circuits often have non-zero initial outputs, known as "zero drift" or "bias voltage." This drift can originate from manufacturing errors in the sensor itself, temperature effects, aging, and input offset voltages of active devices such as operational amplifiers. For precision instruments like mass flow controllers, especially purely analog hardware systems, zero drift has a significant impact on the accuracy of flow control, making zeroing a crucial step in the entire system.
[0003] Currently, traditional zeroing methods are mainly divided into two categories: manual zeroing and digital zeroing.
[0004] Manual zeroing: This method involves manually adjusting the potentiometer, which is time-consuming and labor-intensive, cannot achieve system automation, and has drawbacks such as mechanical wear and environmental influence.
[0005] Digital zeroing (software subtraction): Under no-load or zero-input conditions, the zero-point value is read via an analog-to-digital converter (ADC) and subtracted from the reading in subsequent measurements. This method cannot eliminate offset in the analog link, and when the offset is large, it may saturate the preamplifier, resulting in a loss of dynamic range, and it cannot correct drift over time or temperature.
[0006] Therefore, there is an urgent need for a circuit scheme that can automatically, in real time, and with high precision compensate for the initial bias and slow drift of sensor signals in the analog domain. Summary of the Invention
[0007] This invention addresses the problems of low zero-adjustment accuracy and inability to automatically zero-adjust in traditional zero-adjustment methods by providing an automatic zero-adjustment circuit and method for mass flow controllers, which achieves automated zero-adjustment and improves zero-adjustment accuracy.
[0008] The present invention is achieved through the following technical solution.
[0009] In a first aspect, an automatic zeroing circuit for a mass flow controller is provided, the circuit comprising:
[0010] The zero-adjustment enable signal generation unit is configured to generate a zero-adjustment enable signal after entering the control idle period;
[0011] The clock signal generation unit is activated and connected to the zero-adjustment enable signal generation unit. It is configured to generate a clock signal based on the zero-adjustment enable signal output by the zero-adjustment enable signal generation unit.
[0012] The sensor signal zero-point judgment unit is configured to generate a zero-adjustment voltage change signal based on the analog output voltage of the sensor and the preset voltage value of the mass flow controller.
[0013] The counter analog-to-digital converter unit is connected to the start clock signal generation unit and the sensor signal zero point judgment unit, and is configured to generate a zero-adjustment voltage based on the zero-adjustment voltage change signal output by the sensor signal zero point judgment unit and the clock signal output by the start clock signal generation unit.
[0014] The real-time compensation voltage adjustment unit is connected to the counter analog-to-digital converter unit and is configured to compensate the analog output voltage of the mass flow controller's sensor based on the zero-adjustment voltage output by the counter analog-to-digital converter unit.
[0015] In some embodiments, the zero-adjustment enable signal generation unit includes:
[0016] A first operational amplifier, wherein the inverting input terminal of the first operational amplifier is used to input a first analog signal generated based on entering the control idle period, the non-inverting input terminal of the first operational amplifier is used to input a first reference signal, and the output terminal of the first operational amplifier is connected to the non-inverting input terminal to output the zero-adjustment enable signal.
[0017] In some embodiments, the start clock signal generating unit includes:
[0018] A NAND gate, wherein the first input terminal of the NAND gate is used to input the zero-adjustment enable signal, the second input terminal of the NAND gate is used to input the second reference signal, and the output terminal of the NAND gate is connected to the second input terminal to output the clock signal.
[0019] In some embodiments, the counter analog-to-digital converter unit includes:
[0020] At least two bidirectional counters are cascaded, wherein the clock pin of each of the at least two bidirectional counters is used to input the clock signal, and the counting direction pin is used to input the zero-adjustment voltage change signal; the preceding bidirectional counters of the at least two bidirectional counters are connected to subsequent bidirectional counters through an R-2R network to synthesize a digital-to-analog converter, and the output pins of the at least two bidirectional counters are configured as binary data output bits from low to high based on the connection order.
[0021] The output pins of the at least two bidirectional counters constitute the input branches. Each branch is connected to the network through a 2R resistor, and adjacent branches are connected by an R resistor to form the R-2R network.
[0022] In some embodiments, the real-time compensation voltage adjustment unit includes:
[0023] The second operational amplifier has an inverting input terminal used to input the output voltage of the sensor of the mass flow controller, a non-inverting input terminal used to input the zero-adjustment voltage, and an output terminal connected to the non-inverting input terminal for outputting the compensated voltage.
[0024] In some embodiments, the sensor signal zero-point determination unit includes:
[0025] The third operational amplifier has an inverting input terminal used to input the analog output voltage of the sensor of the mass flow controller, a non-inverting input terminal grounded, and an output terminal used to output the zero-adjustment voltage change signal.
[0026] Secondly, an automatic zeroing method for a mass flow controller is provided, the method comprising:
[0027] After entering the control idle period, a zero-adjustment enable signal is generated through the zero-adjustment enable signal generation unit;
[0028] By activating the clock signal generation unit, a clock signal is generated based on the zero-adjustment enable signal output by the zero-adjustment enable signal generation unit.
[0029] The zero-point judgment unit of the sensor signal generates the zero-adjustment voltage change signal based on the analog output voltage and preset voltage value of the sensor of the mass flow controller.
[0030] The counter simulates a digital-to-analog converter unit, which generates a zero-adjustment voltage based on the zero-adjustment voltage change signal and the clock signal output by the start clock signal generation unit.
[0031] The real-time compensation voltage adjustment unit compensates for the analog output voltage of the mass flow controller's sensor based on the zero-adjustment voltage output by the counter analog-to-analog converter unit, and returns to the step: the sensor signal zero-point judgment unit generates the zero-adjustment voltage change signal based on the analog output voltage of the mass flow controller's sensor and the preset voltage value.
[0032] In some embodiments, the method further includes: before generating the zero-adjustment voltage, setting the digital input pin of the highest bit of the highest bit of the most bidirectional counter in the cascaded at least two bidirectional counters in the counter analog-to-digital converter unit to a high level, and setting all other digital input pins to a low level.
[0033] In some embodiments, the clock pin of each of the at least two bidirectional counters is used to input the clock signal, and the counting direction pin is used to input the zero-adjustment voltage change signal; the output pins of the preceding bidirectional counters of the at least two bidirectional counters are connected to the subsequent bidirectional counters through an R-2R network to synthesize a digital-to-analog converter, and the output pins of the at least two bidirectional counters form binary data output bits from low to high based on the connection order, wherein the output pins of the at least two bidirectional counters form input branches, each branch is connected to the network through a 2R resistor, and adjacent branches are connected by an R resistor. The method further includes: designing the current output weight of each branch based on the binary power corresponding to the position of the binary data output bits, and calculating the zero-adjustment voltage based on the current output weight of each branch and the data output of each branch.
[0034] In some embodiments, the method further includes: after zeroing is completed and during the control idle period, continuously performing automatic zeroing on the sensor of the mass flow controller, and keeping the zeroing voltage change signal within a predetermined range centered on a voltage of 0V.
[0035] Compared with existing technologies, this invention has the following advantages and beneficial effects: In this invention, automatic zeroing is controlled by an externally input analog signal, and the system's flow control is determined based on whether the analog input is greater than 0.1V. During the zeroing enable period, the cascaded counter chip is controlled to count upwards or downwards according to the magnitude of the sensor signal. All the counting output pins of the counter chip act as analog switches, and an R-2R network is used to achieve the function of a DAC, resulting in an adjustable analog voltage for sensor signal compensation. Using an RC circuit and the counter chip as the clock signal for the frequency of the cascaded counters achieves the following technical effects:
[0036] 1. Fully automatic and intelligent: No manual intervention is required. It can automatically complete zeroing according to preset conditions, making it suitable for integration into intelligent instruments and mass flow controller systems;
[0037] 2. Analog domain compensation, preserving dynamic range: Directly cancels drift voltage at the analog front end, avoiding the risk of preamplifier saturation and improving signal-to-noise ratio and measurement resolution;
[0038] 3. High precision and iterative capability: By using multiple cascaded counters, the resolution of the compensation voltage is improved, and millivolt-level zero-adjustment accuracy can be achieved, further ensuring the reliability of the zero-adjustment effect;
[0039] 4. Suppressing slow drift: The system can periodically or conditionally trigger the automatic zeroing process to track and compensate for slow drift caused by factors such as temperature and aging in real time, thereby improving the long-term stability of the system.
[0040] 5. High flexibility: The zero-adjustment control module consists only of analog circuits, which makes it easy to adjust the zero-adjustment strategy (such as resolution, clock frequency, zero-adjustment enable, etc.) and adapt to different sensors and application scenarios;
[0041] 6. Low cost: Analog voltage is synthesized by using a counter chip with an R-2R network, which is both low cost and stable. Attached Figure Description
[0042] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0043] Figure 1 This is a schematic diagram of an automatic zeroing circuit for a mass flow controller according to an embodiment of the present invention.
[0044] Figure 2 This is a schematic diagram of the circuit structure of the zero-adjustment enable signal generation unit according to an embodiment of the present invention.
[0045] Figure 3 This is a schematic diagram of the circuit structure of the start clock signal generation unit according to an embodiment of the present invention.
[0046] Figure 4 This is a schematic diagram of the circuit structure of a counter analog-to-digital converter unit according to an embodiment of the present invention.
[0047] Figure 5 This is a schematic diagram of the circuit structure of an R-2R network according to an embodiment of the present invention.
[0048] Figure 6 This is a schematic diagram of the circuit structure of the real-time compensation voltage adjustment unit according to an embodiment of the present invention.
[0049] Figure 7 This is a schematic diagram of the circuit structure of the sensor signal zero-point determination unit according to an embodiment of the present invention.
[0050] Figure 8This is a flowchart of an automatic zeroing method for a mass flow controller according to an embodiment of the present invention.
[0051] Figure 9 This is a process for automatic zeroing of a mass flow controller according to an embodiment of the present invention. Detailed Implementation
[0052] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.
[0053] On one hand, the present invention provides an automatic zeroing circuit for a mass flow controller. Figure 1 This is a schematic diagram of an automatic zeroing circuit for a mass flow controller according to an embodiment of the present invention. (Reference) Figure 1 The automatic zeroing circuit for the mass flow controller includes: a zeroing enable signal generation unit, a start clock signal generation unit, a counter analog-to-digital converter unit, a compensation voltage real-time adjustment unit, and a sensor signal zero-point judgment unit.
[0054] A zero-adjustment enable signal generation unit is configured to generate a zero-adjustment enable signal after entering the control idle period. A start clock signal generation unit, connected to the zero-adjustment enable signal generation unit, is configured to generate a clock signal based on the zero-adjustment enable signal output by the zero-adjustment enable signal generation unit. A sensor signal zero-point judgment unit is configured to generate a zero-adjustment voltage change signal based on the analog output voltage of the mass flow controller's sensor and a preset voltage value. A counter analog-to-digital converter unit, connected to the start clock signal generation unit and the sensor signal zero-point judgment unit, is configured to generate a zero-adjustment voltage based on the zero-adjustment voltage change signal and the clock signal output by the start clock signal generation unit. A compensation voltage real-time adjustment unit, connected to the counter analog-to-digital converter unit, is configured to compensate the analog output voltage of the mass flow controller's sensor based on the zero-adjustment voltage output by the counter analog-to-digital converter unit.
[0055] In some embodiments, reference Figure 2 The zero-adjustment enable signal generation unit includes: a first operational amplifier, wherein the inverting input terminal of the first operational amplifier is used to input a first analog signal generated based on the entry control idle period, the non-inverting input terminal of the first operational amplifier is used to input a first reference signal, and the output terminal of the first operational amplifier is connected to the non-inverting input terminal for outputting a zero-adjustment enable signal.
[0056] Specifically, refer to Figure 2When the system powers on and enters the control idle period, for analog mass flow controllers, the analog input range is typically 0.1V-5V. A first operational amplifier (dual-channel, U1.2) powered by ±12V connects the analog input to the inverting input terminal 6 (the first analog signal generated during the control idle period, based on the system's operating state) through a filter circuit consisting of resistor R1 and capacitor C1. The non-inverting input terminal 5 is divided from +5V to ground by two resistors (R2, R3) to obtain 100mV, with an open-loop gain, serving as the first reference signal. The output terminal is connected to the non-inverting input terminal 5 through resistor R4. When the analog input voltage is <0.1V, it indicates that the controller is in the control idle period (because when the analog input value is valid, it indicates that the system has started flow control), and the zero-adjustment enable signal outputs a high level (+12V). This zero-adjustment enable signal serves as the input to the input terminal 2 of a NAND gate.
[0057] In some embodiments, the clock signal generation unit includes a NAND gate, wherein a first input terminal of the NAND gate is used to input a zero-adjustment enable signal, a second input terminal of the NAND gate is used to input a second reference signal, and the output terminal of the NAND gate is connected to the second input terminal for outputting a clock signal.
[0058] Specifically, refer to Figure 3 The zero-adjustment enable signal is input to the positive input of two Zener diodes connected in series through resistor R5. The negative inputs of the two Zener diodes are connected to a +5V DC voltage. A tap is provided between the two Zener diodes to connect to the first input terminal 1 of NAND gate U2 (powered by +5V; it must be a Schmitt trigger type, otherwise stable oscillation will not be possible). The second input terminal 2 of the NAND gate is connected to the filter circuit of resistor R6 and capacitor C2. The first end of R6 is connected to the output terminal of the NAND gate, and the second end is connected to the first end of C2 and the second input terminal 2 of the NAND gate. The second end of C2 is grounded. When the zero-adjustment enable signal is +12V, the signal at the first input terminal 1 is high (+5V). When the zero-adjustment enable signal is -12V, the signal at the first input terminal 1 is low (0V). When the first input terminal 1 is continuously high, the output terminal generates a continuous square wave as a clock signal. When the first input terminal 1 is continuously low, the oscillation stops, and the output port is forced to a high level. The clock signal frequency f≈1(2.2*R6*C2) (2.2 is the positive threshold voltage for a 5V CMOS Schmitt gate). RC can be adjusted according to the actual frequency requirements.
[0059] In some embodiments, the counter analog-to-digital converter unit includes: at least two cascaded bidirectional counters, wherein the clock pin of each of the at least two bidirectional counters is used to input a clock signal, and the counting direction pin is used to input a zero-adjustment voltage change signal; the output pins of the preceding bidirectional counters of the at least two bidirectional counters are connected to subsequent bidirectional counters through an R-2R network to synthesize the digital-to-analog converter, and the output pins of the at least two bidirectional counters constitute binary data output bits from low to high based on the connection order. The output pins of the at least two bidirectional counters constitute input branches, each branch is connected to the network through a 2R resistor, and adjacent branches are connected by an R resistor.
[0060] Specifically, refer to Figure 4 This demonstrates how to use two 4-bit bidirectional counters cascaded together to form an 8-bit reversible counter. The digital output pins of the counters are connected through an R-2R network to synthesize a DAC (digital-to-analog converter) module with 8-bit resolution (multiple counters can be cascaded to increase the resolution, such as cascading three 4-bit counters to synthesize a 12-bit analog DAC module).
[0061] The cascaded 8-bit counter has 8 output pins, Q0 (least significant bit) to Q7 (most significant bit), capable of counting from 0 to 255 (binary 00000000-11111111). The first 4-bit counter (low-order counter) is responsible for counting the lower 4 bits (Q0-Q3). The second 4-bit counter (high-order counter) is responsible for counting the higher 4 bits (Q4-Q7). The carry output (CARRYOUT) of the low-order counter is connected to the carry input (CARRYIN) of the high-order counter. Thus, whenever the low-order counter toggles from 1111 to 0000, a carry pulse is generated, pushing the high-order counter to increment by 1.
[0062] refer to Figure 5 The R-2R network is a resistor ladder with 8 input branches, each corresponding to one of the 8 digital bits. The counter output Q0 (least significant bit) has the smallest weight, while the counter output Q7 (most significant bit) has the largest weight. Each branch is connected to the network through a 2R resistor, and adjacent branches are connected by resistors R. Looking inward from the end of the network (closest to the operational amplifier), the contribution of each branch to the final current is a power of 2: Q7 contributes twice the current of Q6, four times that of Q5, and so on, up to 128 times that of Q0. Each counter output pin is either high (representing a digit 1, output +5V) or low (representing a digit 0, output 0V). Pins with an output of "1" inject current into the network through the corresponding 2R resistor, while pins with an output of "0" do not inject current (equivalent to grounding). These currents are superimposed in the R-2R network according to their binary weights, forming a total current Iout.
[0063] We can obtain Vout = Vref * (D / 256). Vref is the high-level voltage of the counter (+5V). D is the current value of the 8-bit counter (0~255). Thus, for every increment of the digital value D by 1, the output voltage increases by a fixed step (Vref / 256). For example, when the system powers on, the values of each digital output bit of the cascaded counter module from high to low are 10000000. Then, the output voltage Vout = 5 * (128 / 256) = 2.5V.
[0064] In some embodiments, the real-time adjustment unit for compensation voltage includes: a second operational amplifier, wherein the inverting input terminal of the second operational amplifier is used to input the output voltage of the sensor of the mass flow controller, the non-inverting input terminal of the second operational amplifier is used to input the zero-adjustment voltage, and the output terminal of the second operational amplifier is connected to the non-inverting input terminal for outputting the compensated voltage.
[0065] Specifically, refer to Figure 6 The zero-adjustment voltage, through resistor R8, is input to the non-inverting input terminal 5 of the second operational amplifier U3.2. The analog output voltage of the mass flow controller's sensor, after being processed by resistors R10 and R11, is input to the inverting input terminal 6 of the second operational amplifier U3.2. The output terminal of the second operational amplifier U3.2 is connected to the non-inverting input terminal 5 through resistor R9. (Reference) Figure 4 The cascaded counter uses its UP / DOWN pin 10 to count up and down based on the current state of the sensor signal. During the counting process, the output voltage of the analog DAC is adjusted in real time by weighting (powers of 2 above) the output pins of each counter. The output voltage of the analog DAC and the sensor signal are then added together via the second operational amplifier U3.2 to achieve automatic zeroing. If R8 = R9 and R10 = R11 at this time, then Vout = (-Vin) - (+Vin), where -Vin represents the input voltage at the inverting input terminal; +Vin represents the input voltage at the non-inverting input terminal. The output voltage of the mass flow controller's sensor can be obtained using a Wheatstone bridge based on a constant current source, and then coupled with a signal conditioning circuit to map the full-scale sensor voltage range to the analog output voltage range.
[0066] In some embodiments, the sensor signal zero-point determination unit includes: a third operational amplifier, wherein the inverting input terminal of the third operational amplifier is used to input the analog output voltage of the sensor of the mass flow controller, the non-inverting input terminal of the third operational amplifier is grounded, and the output terminal of the third operational amplifier is used to output the zero-adjustment voltage change signal.
[0067] Specifically, refer to Figure 7The inverting input 2 of the third operational amplifier U1.1 is used to input the analog output voltage of the sensor of the mass flow controller, the non-inverting input 3 is grounded, and the output 1 is used to output the zero-adjustment voltage change signal. The open-loop feedback makes the op-amp output -12V when the sensor signal is below zero and +12V when it is above zero. The output of the operational amplifier is connected to the UP / DOWN pin of the cascaded counter.
[0068] In this invention, automatic zeroing is controlled by an externally input analog signal, typically with an analog voltage in the range of 0.1-5V representing the effective input range. The analog output range is 0.1-5V, corresponding to the full-scale flow rate. Flow control is determined based on whether the analog input is greater than 0.1V. During zeroing enable, the cascaded counter chip is controlled to count upwards or downwards based on the magnitude of the sensor signal. All the counting output pins of the counter chip act as analog switches, and an R-2R network is used to achieve the function of a DAC, resulting in an adjustable analog voltage for sensor signal compensation. An RC circuit and the counter chip are used as the clock signal for the frequency of the cascaded counter. The technical solution of this invention achieves the following technical effects.
[0069] 1. Fully automatic and intelligent: No manual intervention is required. It can automatically complete zeroing according to preset conditions, making it suitable for integration into intelligent instruments and mass flow controller systems.
[0070] 2. Analog domain compensation, preserving dynamic range: Directly cancels drift voltage at the analog front end, avoiding the risk of preamplifier saturation and improving signal-to-noise ratio and measurement resolution.
[0071] 3. High precision and iterative capability: By using multiple cascaded counters, the resolution of the compensation voltage is improved, and millivolt-level zero-adjustment accuracy can be achieved, further ensuring the reliability of the zero-adjustment effect.
[0072] 4. Suppressing slow drift: The system can periodically or conditionally trigger the automatic zeroing process to track and compensate for slow drift caused by factors such as temperature and aging, thereby improving the long-term stability of the system.
[0073] 5. High flexibility: The zero-adjustment control module consists only of analog circuits, which makes it easy to adjust the zero-adjustment strategy (such as resolution, clock frequency, zero-adjustment enable, etc.) and adapt to different sensors and application scenarios.
[0074] 6. Low cost: Analog voltage is synthesized by using a counter chip with an R-2R network, which is both low cost and stable.
[0075] On the other hand, the present invention provides an automatic zeroing method for a mass flow controller. Figure 8This is a flowchart of an automatic zeroing method for a mass flow controller according to an embodiment of the present invention. Figure 9 This is a procedure for automatic zeroing of a mass flow controller according to an embodiment of the present invention. (Reference) Figure 8 and Figure 9 The automatic zeroing method for a mass flow controller includes: S10 to S50.
[0076] In S10, after entering the control idle period, a zero-adjustment enable signal is generated by the zero-adjustment enable signal generation unit. Specifically, whether to generate a zero-adjustment enable signal can be determined by whether the first analog signal (analog input) generated during the control idle period is greater than 0.1V. If it is greater than 0.1V, it indicates that the system is in a non-control idle period and zero-adjustment is not performed; otherwise, the control subsequent clock signal generation unit generates a clock signal.
[0077] In S20, a clock signal is generated by activating the clock signal generation unit and generating the clock signal based on the zero-adjustment enable signal output by the zero-adjustment enable signal generation unit.
[0078] In S30, the zero-point judgment unit generates a zero-adjustment voltage change signal based on the analog output voltage of the mass flow controller's sensor and a preset voltage value. Specifically, when the analog output voltage of the mass flow controller's sensor is greater than 0, a signal is generated that decreases the adjustment voltage; otherwise, a signal is generated that increases the adjustment voltage.
[0079] In S40, a counter is used to simulate a digital-to-analog converter unit, which generates a clock signal output by the unit based on the zero-adjustment voltage change signal and the start clock signal, thereby generating a zero-adjustment voltage.
[0080] In step S50, the analog output voltage of the mass flow controller's sensor is compensated by the real-time compensation voltage adjustment unit based on the zero-adjustment voltage output by the counter analog-to-analog converter unit. Specifically, the zero-adjustment voltage is added to the original analog output voltage to obtain the adjusted voltage, and the process returns to step S30.
[0081] In some embodiments, the automatic zeroing method for a mass flow controller further includes: before generating the zeroing voltage, setting the digital input pin of the highest-order bit of the highest-order counter in at least two cascaded bidirectional counters in the counter analog-to-digital converter unit to a high level, and setting all other digital input pins to a low level. Specifically, setting the digital input pin of the highest-order bit of the highest-order counter in the cascaded counters to a high level, and setting all other digital input pins to a low level, such that the cascaded counters are loaded with the following values when the system is powered on: the highest-order bit is 1, and the rest are all 0; the analog voltage initial output is 2.5V.
[0082] In some embodiments, the clock pin of each of the at least two bidirectional counters is used to input a clock signal, and the counting direction pin is used to input a zero-adjustment voltage change signal; the output pins of the preceding bidirectional counters of the at least two bidirectional counters are connected to the subsequent bidirectional counters through an R-2R network to synthesize a digital-to-analog converter, and the output pins of the at least two bidirectional counters form binary data output bits from low to high based on the connection order, wherein the output pins of the at least two bidirectional counters form input branches, each branch is connected to the network through a 2R resistor, and adjacent branches are connected by an R resistor. The automatic zero-adjustment method for the mass flow controller further includes: designing the current output weight of each branch based on the binary power corresponding to the position of the binary data output bits, and calculating the zero-adjustment voltage based on the current output weight of each branch and the data output of each branch.
[0083] In some embodiments, the automatic zeroing method for the mass flow controller further includes: after zeroing is completed and during a control idle period, continuously performing automatic zeroing on the sensor of the mass flow controller, and keeping the zeroing voltage change signal within a predetermined range centered on a voltage of 0V. Specifically, after zeroing is completed, the cascaded counter clock signal stops, the zeroing voltage remains at its current value, and zero-point compensation for normal high-precision measurement is completed.
[0084] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. An automatic zeroing circuit for a mass flow controller, characterized in that, The circuit includes: The zero-adjustment enable signal generation unit is configured to generate a zero-adjustment enable signal after entering the control idle period; The clock signal generation unit is activated and connected to the zero-adjustment enable signal generation unit. It is configured to generate a clock signal based on the zero-adjustment enable signal output by the zero-adjustment enable signal generation unit. The sensor signal zero-point judgment unit is configured to generate a zero-adjustment voltage change signal based on the analog output voltage of the sensor and the preset voltage value of the mass flow controller. The counter analog-to-digital converter unit is connected to the start clock signal generation unit and the sensor signal zero point judgment unit, and is configured to generate a zero-adjustment voltage based on the zero-adjustment voltage change signal output by the sensor signal zero point judgment unit and the clock signal output by the start clock signal generation unit. The real-time compensation voltage adjustment unit is connected to the counter analog-to-digital converter unit and is configured to compensate the analog output voltage of the mass flow controller's sensor based on the zero-adjustment voltage output by the counter analog-to-digital converter unit.
2. The circuit according to claim 1, characterized in that, The zero-adjustment enable signal generation unit includes: A first operational amplifier, wherein the inverting input terminal of the first operational amplifier is used to input a first analog signal generated based on entering the control idle period, the non-inverting input terminal of the first operational amplifier is used to input a first reference signal, and the output terminal of the first operational amplifier is connected to the non-inverting input terminal to output the zero-adjustment enable signal.
3. The circuit according to claim 1, characterized in that, The start clock signal generation unit includes: A NAND gate, wherein the first input terminal of the NAND gate is used to input the zero-adjustment enable signal, the second input terminal of the NAND gate is used to input the second reference signal, and the output terminal of the NAND gate is connected to the second input terminal to output the clock signal.
4. The circuit according to any one of claims 1 to 3, characterized in that, The counter analog-to-digital converter unit includes: At least two bidirectional counters are cascaded, wherein the clock pin of each of the at least two bidirectional counters is used to input the clock signal, and the counting direction pin is used to input the zero-adjustment voltage change signal; the preceding bidirectional counters of the at least two bidirectional counters are connected to subsequent bidirectional counters through an R-2R network to synthesize a digital-to-analog converter, and the output pins of the at least two bidirectional counters are configured as binary data output bits from low to high based on the connection order. The output pins of the at least two bidirectional counters constitute the input branches. Each branch is connected to the network through a 2R resistor, and adjacent branches are connected by an R resistor to form the R-2R network.
5. The circuit according to claim 1, characterized in that, The real-time adjustment unit for the compensation voltage includes: The second operational amplifier has an inverting input terminal used to input the output voltage of the sensor of the mass flow controller, a non-inverting input terminal used to input the zero-adjustment voltage, and an output terminal connected to the non-inverting input terminal for outputting the compensated voltage.
6. The circuit according to claim 1, characterized in that, The sensor signal zero-point determination unit includes: The third operational amplifier has an inverting input terminal used to input the analog output voltage of the sensor of the mass flow controller, a non-inverting input terminal grounded, and an output terminal used to output the zero-adjustment voltage change signal.
7. An automatic zeroing method for a mass flow controller, characterized in that, The method includes: After entering the control idle period, a zero-adjustment enable signal is generated through the zero-adjustment enable signal generation unit; By activating the clock signal generation unit, a clock signal is generated based on the zero-adjustment enable signal output by the zero-adjustment enable signal generation unit. The zero-point judgment unit of the sensor signal generates the zero-adjustment voltage change signal based on the analog output voltage and preset voltage value of the sensor of the mass flow controller. The counter simulates a digital-to-analog converter unit, which generates a zero-adjustment voltage based on the zero-adjustment voltage change signal and the clock signal output by the start clock signal generation unit. The real-time compensation voltage adjustment unit compensates for the analog output voltage of the mass flow controller's sensor based on the zero-adjustment voltage output by the counter analog-to-analog converter unit, and returns to the step: the sensor signal zero-point judgment unit generates the zero-adjustment voltage change signal based on the analog output voltage of the mass flow controller's sensor and the preset voltage value.
8. The method according to claim 7, characterized in that, The method further includes: before generating the zero-adjustment voltage, setting the digital input pin of the highest bit of the highest bit of the cascaded bidirectional counter in the counter analog-to-digital converter unit to a high level, and setting all other digital input pins to a low level.
9. The method according to claim 7, characterized in that, The clock pin of each of the at least two bidirectional counters is used to input the clock signal, and the counting direction pin is used to input the zero-adjustment voltage change signal. The output pins of the preceding bidirectional counters of the at least two bidirectional counters are connected to the subsequent bidirectional counters through an R-2R network to synthesize a digital-to-analog converter. The output pins of the at least two bidirectional counters form binary data output bits from low to high based on the connection order. The output pins of the at least two bidirectional counters form input branches. Each branch is connected to the network through a 2R resistor, and adjacent branches are connected by an R resistor. The method further includes: designing the current output weight of each branch based on the binary power corresponding to the position of the binary data output bits, and calculating the zero-adjustment voltage based on the current output weight of each branch and the data output of each branch.
10. The method according to claim 7, characterized in that, The method further includes: after the zeroing is completed and during the control idle period, continuously performing automatic zeroing on the sensor of the mass flow controller, and keeping the zeroing voltage change signal within a predetermined range centered on a voltage of 0V.