A fuse trimming system

Abstract

The application provides a fuse trimming system, belonging to the technical field of fuse trimming digital circuits, which comprises a data input module, a latch unlocking module, a fuse information column address module, an address scanning module, a fuse unit module and a fuse information module. The data input module generates column selection addresses and row data. The latch unlocking module generates an enable signal when the latched data matches a preset unlocking code. The fuse information column address module decodes the column selection addresses during pre-trimming when the enable signal is unlocked. The address scanning module generates fuse row addresses and column addresses during trimming. The fuse unit module writes target fuse unit according to the row addresses and column addresses and the delayed power-on reset signal, and outputs fuse state information. The fuse information module reads and latches the fuse state information according to the decoding, row data and delayed power-on reset signal. The beneficial effects are as follows: the trimming code verification and single fuse unit positioning simulation without writing during the pre-trimming stage are realized, and the chip failure caused by incorrect trimming is avoided; the three-signal interlocking trigger mechanism eliminates the risk of incorrect burning from the hardware level, and the safety, accuracy and reliability of the fuse trimming are improved.

Description

Technical Field

[0001] This invention relates to the field of fuse adjustment digital circuit technology, and in particular to a fuse adjustment system. Background Technology

[0002] The performance of chips integrated into electronic devices often directly affects whether the devices can achieve their intended functions. Errors in chip manufacturing and packaging processes can cause deviations between the chip's actual test values ​​and design values. To improve chip production yield, trimming circuits are typically added to the chip. By calculating the deviation between the actual test values ​​and design values ​​of the chip parameters, and determining the trimming step size, the trimming circuit corrects the parameter deviations to ensure that the chip still reaches the design values ​​after repeated power-ups.

[0003] However, due to the one-time programming characteristic of fuse trimming circuits, writing incorrect trimming code can easily lead to a decrease in chip yield, thereby increasing chip manufacturing costs. Summary of the Invention

[0004] To address the above technical problems, this invention provides a fuse adjustment system.

[0005] The technical problem solved by this invention can be achieved by the following technical solution: A fuse adjustment system, comprising: a data input module, used to receive a clock signal and a data signal, generate a column selection address signal and row data through a shift register, and transmit the clock signal and data signal to a latch unlocking module and a fuse information column address module; the latch unlocking module is connected to the data input module, used to latch the data signal in a register according to the clock signal, and generate an enable signal when the latched data matches a preset unlock code; the fuse information column address module is connected to both the data input module and the latch unlocking module, used to release the locked state of the fuse information column address according to the enable signal, and latch the column selection address signal. In the fuse pre-adjustment stage, the latched column selection address signal is decoded and a decoded signal is output. The address scanning module is used to generate the row address signal and column address signal of the fuse in the fuse adjustment stage according to the clock signal. The fuse unit module is connected to the address scanning module and is used to program the target fuse unit according to the row address signal and column address signal output by the address scanning module and the delayed power-on reset signal, and output fuse status information at the same time. The fuse information module is connected to the data input module, the fuse information column address module and the fuse unit module respectively, and is used to read the fuse status information output by the fuse unit module according to the decoded signal, the row data and the delayed power-on reset signal, and latch the fuse status information.

[0006] The fuse adjustment system of the present invention further includes: an initialization module, which is connected to the data input module, the latch unlocking module and the fuse information column address module respectively, for receiving the clock signal, the data signal and the power-on reset signal, and outputting a reset or set signal to the data input module, the latch unlocking module and the fuse information column address module.

[0007] The fuse adjustment system of the present invention includes an initialization module comprising: a first logic gate for performing an OR logic operation on the inverted signal of the data signal and a first signal to output a first intermediate signal; a second logic gate for performing a NAND logic operation on the first intermediate signal, the clock signal, and the power-on reset signal to output a second intermediate signal; wherein the first signal is the inverted signal of the second intermediate signal; a third logic gate for performing an OR logic operation on the data signal and the second signal to output a third intermediate signal; a fourth logic gate for performing a NAND logic operation on the third intermediate signal, the clock signal, and the power-on reset signal to output a fourth intermediate signal; wherein the second signal is the inverted signal of the fourth intermediate signal; and a fifth logic gate for performing an OR logic operation on the fourth intermediate signal and the data signal to output a reset or set signal.

[0008] The fuse adjustment system of the present invention includes a data input module comprising a shift register, wherein the shift register includes a first to an eighth D flip-flop, the data input terminal of the first D flip-flop is used to receive the data signal, the inverted output terminal of the preceding D flip-flop is connected to the data input terminal of the following D flip-flop through an inverter, the inverted output terminals of all the D flip-flops are connected to the fuse information module, and the output terminals of the first to second D flip-flops are connected to the fuse information column address module.

[0009] The fuse adjustment system of the present invention includes a latch unlocking module comprising: a ninth to a sixteenth D flip-flop, wherein the data input terminal of the ninth D flip-flop is used to receive the data signal, and the output terminal of the preceding D flip-flop is connected to the data input terminal of the following D flip-flop; a sixth logic gate, used to perform an AND logic operation on the inverted signals of the output terminals of the thirteenth to sixteenth D flip-flops to output a fifth intermediate signal; a seventh logic gate, used to perform an AND logic operation on the output terminals of the ninth to twelfth D flip-flops to output a sixth intermediate signal; an eighth logic gate, used to perform an AND logic operation on the fifth intermediate signal and the sixth intermediate signal to output a seventh intermediate signal; and a seventeenth D flip-flop, wherein the data input terminal of the seventeenth D flip-flop is connected to the seventh intermediate signal, and the output terminal of the seventeenth D flip-flop serves as the output terminal of the latch unlocking module for generating an enable signal.

[0010] The fuse adjustment system of the present invention includes a fuse information column address module comprising: a latch unit for latching a first column selection address signal and a second column selection address signal output by the data input module; and a decoder unit for decoding the column selection address signal latched by the latch unit under the action of an enable signal output by the latch unlock module.

[0011] The fuse adjustment system of the present invention includes a latch unit comprising: an eighteenth D flip-flop, the data input of which is connected to the inverted signal of an eighth intermediate signal, and the output of which is used to output the eighth intermediate signal; a nineteenth D flip-flop, the data input of which is connected to a third signal, and the output of which is used to output a ninth intermediate signal, wherein the third signal is the XOR signal of the eighth and ninth intermediate signals; a twentieth D flip-flop, the data input of which is connected to a fourth signal, and the output of which is used to output a tenth intermediate signal, wherein the fourth signal is the signal obtained by performing an AND operation on the eighth and ninth intermediate signals and then an XOR operation on the tenth intermediate signal; a ninth logic gate, used to perform an AND operation on the eighth, ninth, and tenth intermediate signals to output an eleventh intermediate signal; and a tenth logic gate, used to perform an AND operation on the eleventh intermediate signal and the enable signal. The signal undergoes a NAND logic operation, outputting the twelfth intermediate signal; the twenty-first D flip-flop has its data input connected to the fifth signal, its output used to generate the first latch signal, and its inverted output used to generate the second latch signal, wherein the fifth signal is the NOR signal of the inverted data signal and the eleventh intermediate signal; the twenty-second D flip-flop has its data input connected to the sixth signal, its output used to generate the third latch signal, and its inverted output used to generate the fourth latch signal, wherein the sixth signal is the NOR signal of the inverted first column selection address signal and the eleventh intermediate signal; the twenty-third D flip-flop has its data input connected to the seventh signal, its output used to generate the fifth latch signal, and its inverted output used to generate the sixth latch signal, wherein the seventh signal is the NOR signal of the inverted second column selection address signal and the eleventh intermediate signal.

[0012] The fuse adjustment system of the present invention includes a decoder unit comprising: an eleventh logic gate for performing a NAND logic operation on the second latch signal, the fourth latch signal, and the fifth latch signal, and outputting a thirteenth intermediate signal; a twelfth logic gate for performing a NAND logic operation on the first latch signal, the third latch signal, and the sixth latch signal, and outputting a fourteenth intermediate signal; a thirteenth logic gate for performing a NAND logic operation on the second latch signal, the third latch signal, and the sixth latch signal, and outputting a fifteenth intermediate signal; a fourteenth logic gate for performing a NOR logic operation on the second latch signal, the third latch signal, and the fifth latch signal, and outputting a sixteenth intermediate signal; a fifteenth logic gate for performing a NOR logic operation on the first latch signal, the third latch signal, and the fifth latch signal, and outputting a seventeenth intermediate signal; and a sixteenth logic gate for... The system performs a NOR operation on the inverted enable signal and the thirteenth intermediate signal to output a first decoded signal and its inverted counterpart; a seventeenth logic gate performs a NOR operation on the inverted enable signal and the fourteenth intermediate signal to output a second decoded signal and its inverted counterpart; an eighteenth logic gate performs a NOR operation on the inverted enable signal and the fifteenth intermediate signal to output a third decoded signal and its inverted counterpart; a nineteenth logic gate performs a NOR operation on the inverted enable signal and the sixteenth intermediate signal to output a fourth decoded signal and its inverted counterpart; and a twentieth logic gate performs a NOR operation on the inverted enable signal and the delayed seventeenth intermediate signal to output a fifth decoded signal and its inverted counterpart.

[0013] The fuse trimming system of the present invention includes an address scanning module comprising: a first logic unit and a second logic unit, each comprising: a twenty-first logic gate for performing an OR logic operation on the first row address signal and the second row address signal to output an eighteenth intermediate signal; a twenty-second logic gate for performing an OR logic operation on the third row address signal, the fourth row address signal, and the fifth row address signal to output a nineteenth intermediate signal; a twenty-third logic gate for performing an OR logic operation on the sixth row address signal, the seventh row address signal, and the eighth row address signal to output a twentieth intermediate signal; and a twenty-fourth logic gate for performing a NOR logic operation on the eighteenth, nineteenth, and twentieth intermediate signals to output a twenty-first intermediate signal; and a first shift register unit comprising twenty-fourth to thirty-first D flip-flops, the data input terminal of the twenty-fourth D flip-flop being connected to the first logic unit output. The 21st intermediate signal is output, the output of the preceding D flip-flop is connected to the data input of the following D flip-flop, the clock terminals of the 24th to 31st D flip-flops are all connected to clock signals, and the output terminals of the 24th to 31st D flip-flops sequentially output the first to eighth row address signals; the second shift register unit includes the 32nd to 39th D flip-flops, the data input of the 32nd D flip-flop is connected to the 21st intermediate signal output by the second logic unit, the output of the preceding D flip-flop is connected to the data input of the following D flip-flop, the clock terminals of the 32nd to 39th D flip-flops are all connected to the first row address signal, the output of the 32nd D flip-flop is used to output the first column address signal, the output of the 33rd D flip-flop is used to output the second column address signal, and the output terminals of the 34th to 39th D flip-flops sequentially output the third to eighth row address signals.

[0014] The fuse adjustment system of the present invention includes a fuse unit module comprising: a delay unit for delaying the power-on reset signal, outputting a first power-on delayed reset signal and a second power-on delayed reset signal, and outputting a third power-on delayed reset signal to the fuse information module; and a fuse unit connected to the delay unit and the address scanning module, for outputting fuse status information based on the row address signal and column address signal output by the address scanning module, the first power-on delayed reset signal and the second power-on delayed reset signal, and the output signal of the fuse information module.

[0015] The fuse adjustment system of the present invention comprises multiple fuse units, each fuse unit comprising: a 25th logic gate, used to perform an AND logic operation on the row address signal, column address signal, and output signal of the fuse information module to output a first control signal; a first on / off switch, controllably connecting the fuse to be adjusted to a first node under the action of the first power-on delay reset signal, wherein the first node outputs the fuse status information via inversion; a second on / off switch, controllably connecting the first node to a ground terminal under the action of the second power-on delay reset signal; and a third on / off switch, controllably connecting the fuse to be adjusted to the ground terminal under the action of the first control signal.

[0016] The fuse adjustment system of the present invention comprises a fuse information module consisting of multiple fuse information units arranged in an array. The array of fuse information units corresponds one-to-one with the array address of the fuse units. Each fuse information unit includes: a 26th logic gate, used to perform an OR logic operation on the inverted signal of the fuse status information and the third power-on delay reset signal, outputting a 22nd intermediate signal; a 27th logic gate, used to perform an OR logic operation on the 8th signal and the decoded signal output by the fuse information column address module, outputting a 23rd intermediate signal; a 28th logic gate, used to perform an OR logic operation on the row data output by the data input module and the inverted signal of the decoded signal, outputting a 24th intermediate signal; and a 29th logic gate, used to perform an OR logic operation on the... The twenty-third and twenty-fourth intermediate signals are subjected to NAND logic operations to output the twenty-fifth intermediate signal; the thirtieth logic gate is used to perform an OR logic operation on the fuse status information and the third power-on delay reset signal to output the twenty-sixth intermediate signal; the thirty-first logic gate is used to perform an AND logic operation on the twenty-sixth intermediate signal and the power-on reset signal to output the twenty-seventh intermediate signal; the fortieth D flip-flop has its data input terminal connected to the twenty-fifth intermediate signal, its asynchronous set terminal connected to the twenty-second intermediate signal, and its asynchronous reset terminal connected to the twenty-seventh intermediate signal. The output terminal of the fortieth D flip-flop is used to output the output signal of the fuse information module, and its inverted output terminal is used to output the eighth signal.

[0017] The advantages or beneficial effects of the technical solution of this invention are as follows: This invention realizes the shifting and registering of data signals and address generation through the data input module, combined with the code matching verification and enable control of the latch unlocking module, and the unlocking, latching and decoding functions of the fuse information column address module, so as to realize the verification of the trimming code without burning and the simulation of single fuse unit positioning in the pre-trimming stage, avoiding chip failure caused by incorrect trimming; the three-signal interlocking triggering mechanism of the address scanning module and the fuse unit module can locate and burn the target fuse, eliminating the risk of accidental burning from the hardware level; the fuse information module completes the status reading, latching and persistent output, improving the safety, accuracy and reliability of fuse trimming. Attached Figure Description

[0018] Figure 1 This is a structural block diagram of the fuse trimming system in a preferred embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the initialization module in a preferred embodiment of the present invention; Figure 3 This is a timing diagram of the initialization module in a preferred embodiment of the present invention; Figure 4 This is a schematic diagram of the data input module in a preferred embodiment of the present invention; Figure 5 This is a timing diagram of the data input module in a preferred embodiment of the present invention; Figure 6 This is a schematic diagram of the latch unlocking module in a preferred embodiment of the present invention; Figure 7 This is a timing diagram of the latch unlocking module in a preferred embodiment of the present invention; Figure 8 This is a timing diagram illustrating the selection of fuse row information in a preferred embodiment of the present invention. Figure 9 This is a schematic diagram of the structure of the fuse information column address module in a preferred embodiment of the present invention; Figure 10 This is a schematic diagram of the decoder unit in a preferred embodiment of the present invention; Figure 11 This is a timing diagram of column data selection in a preferred embodiment of the present invention; Figure 12 This is a schematic diagram of the address scanning module in a preferred embodiment of the present invention; Figure 13 This is a timing diagram of the address scanning module in a preferred embodiment of the present invention; Figure 14 This is a schematic diagram of the structure of the fuse unit module in a preferred embodiment of the present invention; Figure 15This is a schematic diagram of the structure of the fuse unit in a preferred embodiment of the present invention; Figure 16 This is a timing diagram of fuse status information reading in a preferred embodiment of the present invention; Figure 17 This is a schematic diagram of the structure of the fuse information unit in a preferred embodiment of the present invention; Figure 18 This is a timing diagram of reading a fuse (without the fuse burning) in a preferred embodiment of the present invention. Figure 19 This is a timing diagram of reading a fuse (which has been blown) in a preferred embodiment of the present invention. Figure 20 This is a timing diagram of pre-tuning in a preferred embodiment of the present invention; Figure 21 The following is a flowchart of the fuse trimming system in a preferred embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0021] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0022] In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a fuse adjustment system is provided for circuits that require the use of multiple fuses, such as... Figure 1As shown, the system includes a data input module 200, a latch unlocking module 300, a fuse information column address module 400, an address scanning module 700, a fuse unit module 600, and a fuse information module 500. The data input module 200 receives clock and data signals, generates column selection address signals and row data through a shift register, provides column selection address signals to the fuse information column address module 400, provides row address signals to the fuse information module 500, and transmits the clock and data signals to the latch unlocking module 300 and the fuse information column address module 400, providing an unlock signal to the latch unlocking module 300. The latch unlocking module 300 is connected to the data input module 200 and latches the data signal in a register according to the clock signal, generating an enable signal when the latched data matches a preset unlock code. The fuse information column address module 400 is connected to both the data input module 200 and the latch unlocking module 300, and releases the locked state of the fuse information column address according to the enable signal, allowing the fuse information column address to be unlocked. The system latches the column selection address signal and decodes it during the fuse pre-adjustment stage, outputting a decoded signal. Specifically, after the data input module 200 inputs the corresponding column selection address signal, the fuse information column address module 400 first latches it and then decodes it to make the corresponding column address signal high, providing the column address of the fuse information unit. The address scanning module 700 generates the row address signal and column address signal of the fuse during the fuse adjustment stage based on the clock signal. The fuse unit module 600... The address scanning module 700 is used to program the target fuse unit according to the row address signal and column address signal output by the address scanning module and the delayed power-on reset signal, and output fuse status information at the same time; the fuse information module 500 is connected to the data input module 200, the fuse information column address module 400 and the fuse unit module 600 respectively, and is used to read the fuse status information output by the fuse unit module 600 according to the decoding signal, row data and the delayed power-on reset signal, and latch the fuse status information.

[0023] The fuse trimming system of the present invention, such as Figure 1 As shown, it also includes: an initialization module 100, which is connected to the data input module 200, the latch unlocking module 300 and the fuse information column address module 400 respectively, for receiving the clock signal CLK, the data signal DATA and the power-on reset signal POR, and outputting a reset or set signal RST to the data input module 200, the latch unlocking module 300 and the fuse information column address module 400.

[0024] Specifically, in this embodiment, the initialization module 100 uses the clock signal CLK and the data signal DATA to output a low-pulse reset or set signal RST after power-on, combined with the power-on reset signal POR. This resets or sets each D flip-flop in the fuse adjustment system to eliminate the indeterminate state of the flip-flops in the initial power-on stage, ensuring that all modules are in the initial zero state after power-on, with no residual random data.

[0025] The fuse trimming system of the present invention, such as Figure 2As shown, the initialization module 100 includes: a first logic gate OR1, a second logic gate NAND1, a third logic gate OR2, a fourth logic gate NAND2, a fifth logic gate OR3, a first inverter INV1, a second inverter INV2, and a third inverter INV3; the first logic gate OR1 is a two-input OR gate, the first input of the first logic gate OR1 is connected to the output of the first inverter INV1, and the second input of the first logic gate OR1 is connected to the output of the second inverter INV2, used to perform an OR logic operation on the inverted signal of the data signal DATA and a first signal, and output a first intermediate signal; wherein, the inverted signal of the data signal DATA is provided by the first inverter INV1.The input of the first inverter INV1 is connected to the data signal DATA, and the output of the first inverter INV1 is used to generate the inverted signal of the data signal DATA. The second logic gate NAND1 is a three-input NAND gate. The first input of the second logic gate NAND1 is connected to the output of the first logic gate OR1, the second input of the second logic gate NAND1 is connected to the clock signal CLK, and the third input of the second logic gate NAND1 is connected to the power-on reset signal POR. This is used to AND the first intermediate signal, the clock signal CLK, and the power-on reset signal POR. The NOT logic operation outputs a second intermediate signal, where the first signal is the inverted version of the second intermediate signal. The input of the second inverter INV2 is connected to the output of the second logic gate NAND1. The output of the second inverter INV2 is used to generate the inverted version of the second intermediate signal, i.e., the first signal is connected to the first input of the first logic gate OR1. The third logic gate OR2 is a two-input OR gate. The first input of the third logic gate OR2 is connected to the data signal DATA, and the second input is connected to the output of the third inverter INV3, used to process the data signal DATA. The ATA and second signals undergo an OR logic operation to output a third intermediate signal; the fourth logic gate, NAND2, is a three-input NAND gate. The first input of NAND2 is connected to the output of the third logic gate, OR2; the second input is connected to the clock signal CLK; and the third input is connected to the power-on reset signal POR. This NAND gate performs a NAND logic operation on the third intermediate signal, CLK, and POR to output the fourth intermediate signal; the second signal is the inverted signal of the fourth intermediate signal. The input of the third inverter INV3 is connected to the output of the fourth logic gate NAND2. The output of the third inverter INV3 is used to generate the inverted signal of the fourth intermediate signal, that is, the second signal to the first input of the first logic gate OR1. The fifth logic gate OR3 is a two-input OR gate. The first input of the fifth logic gate OR3 is connected to the output of the fourth logic gate NAND2. The second input of the fifth logic gate OR3 is connected to the data signal DATA. It is used to perform OR logic operation on the fourth intermediate signal and the data signal DATA, and output a reset or set signal RST.

[0026] Specifically, the initialization trigger condition in initialization module 100 is as follows: after the system powers on, the power-on reset signal POR changes from low to high; while the clock signal CLK remains high, the data signal DATA changes from high to low, forming a falling edge signal. The initialization timing is as follows: Figure 3 As shown.

[0027] Under this triggering condition, the combinational and timing logic inside the initialization module 100 responds to the falling edge of the data signal DATA, and, combined with the high level state of the current clock signal CLK, generates a reset or set signal. This signal is synchronously output to the D flip-flops at each level in the data input module 200, latch unlocking module 300, fuse information column address module 400, and other modules, performing a unified reset or set operation on them. This forces the initial state of the flip-flops to be set to a definite high or low level, thereby avoiding abnormal operating conditions such as address misselection, latching errors, or fuse burnout caused by the uncertain state of the flip-flops after power-on, ensuring that the system can enter a controllable initial working state after power-on.

[0028] The fuse trimming system of the present invention, such as Figure 4 As shown, the data input module 200 includes a shift register, which comprises a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth D flip-flop D5, a sixth D flip-flop D6, a seventh D flip-flop D7, and an eighth D flip-flop D8. The clock terminals of the first to eighth D flip-flops are all connected to the same clock signal to achieve synchronous triggering of the flip-flops. Simultaneously, the reset / set control terminals of the first to eighth D flip-flops are all connected to the same reset or set signal RST output by the initialization module 100. By sharing the same clock signal and reset / set signal, the timing of all D flip-flops in the shift register chain can be synchronized, avoiding data shift errors and incorrect state latching caused by asynchronous clock or control signals. Furthermore, during the initialization phase, a unified reset or set signal can synchronously initialize all flip-flops, eliminating indeterminate states.

[0029] Specifically, the data input terminal of the first D flip-flop D1 is used to receive the data signal DATA. The first to eighth D flip-flops are connected in series. The inverted output terminal of the previous stage D flip-flop is connected to the data input terminal of the next stage D flip-flop through an inverter. The inverted output terminals of all D flip-flops are connected to the fuse information module, which is used to generate row data, including the first row data ROW_DATA1 generated by the first D flip-flop D1, the second row data ROW_DATA2 generated by the second D flip-flop D2, the third row data ROW_DATA3 generated by the third D flip-flop D3, and the fourth row data ROW_DATA3 generated by the fourth D flip-flop D4. The data consists of ROW_DATA4, the fifth row of data ROW_DATA5 generated by the fifth D flip-flop D5, the sixth row of data ROW_DATA6 generated by the sixth D flip-flop D6, the seventh row of data ROW_DATA7 generated by the seventh D flip-flop D7, and the eighth row of data ROW_DATA8 generated by the eighth D flip-flop D8. The outputs of the first and second D flip-flops are connected to the fuse information column address module. The output of the first D flip-flop D1 is used to generate the first column selection address signal 200_D1_Q, and the output of the second D flip-flop D2 is used to generate the second column selection address signal 200_D2_Q.

[0030] Specifically, the data input module 200 is a shift register, which is composed of D flip-flops. The clock signal CLK provides the clock for the D flip-flops, and the data signal DATA provides the data for the D flip-flops. This is used to input data to other modules of the fuse adjustment system, provide an unlock signal to the latch unlock module 300, provide a column selection address signal to the fuse information column address module 400, and simultaneously provide a fuse information row address signal to the fuse information module 500 during pre-adjustment. The row data selection timing is as follows... Figure 5 As shown.

[0031] Furthermore, the latch unlocking module 300 is configured to implement the controlled unlocking function of the fuse information column address module 400, ensuring that the column address decoder only operates in the authorized state and avoiding false triggering. The latch unlocking module 300 consists of a register and combinational logic circuitry. The register is formed by cascading multiple D flip-flops, and its data input terminal is connected to the data input module 200 to receive and serially shift and store the serial data signal output by the data input module 200. The combinational logic circuitry is configured to perform logical operations on the parallel data latched in the register to generate an enable signal that controls the fuse information column address module 400.

[0032] The specific workflow is as follows: The data input module 200 inputs the preset serial unlock code bit by bit into the latch unlock module 300. The data is serially shifted and latched into parallel data by a register composed of multiple D flip-flops. The combinational logic circuit performs a real-time logical comparison of this parallel data. Only when the latched data completely matches the preset unlock code does the combinational logic circuit output a valid high-level enable signal. This enable signal serves as the working enable signal for the fuse information column address module 400, unlocking the decoder circuit inside the fuse information column address module 400, releasing its locked state, enabling the decoder to respond to the input column address signal and output a valid level, thus allowing the fuse information column address module 400 to enter normal working state. If the input data does not match the preset unlock code, the combinational logic circuit will output an invalid low-level signal, the decoder circuit will remain locked, the column address signal will not be effective, and the fuse information column address module 400 will not work normally.

[0033] For example, in this embodiment, the unlock code is configured as the binary sequence "11110000", such as... Figure 6 As shown, the latch unlocking module 300 includes: a ninth D flip-flop D9, a tenth D flip-flop D10, an eleventh D flip-flop D11, a twelfth D flip-flop D12, a thirteenth D flip-flop D13, a fourteenth D flip-flop D14, a fifteenth D flip-flop D15, a sixteenth D flip-flop D16, a seventeenth D flip-flop D17, a sixth logic gate AND1, a seventh logic gate AND2, an eighth logic gate AND3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, and a seventh inverter INV7. In this embodiment, the ninth to seventeenth D flip-flops all share the same clock signal and a reset or set signal RST.

[0034] Specifically, the data input terminal of the ninth D flip-flop D9 is used to receive data signals. The ninth to sixteenth D flip-flops are connected in series, with the output of the previous stage connected to the data input terminal of the next stage. The sixth logic gate AND1 is a four-input AND gate. Its first input is connected to the output of the thirteenth D flip-flop D13 via the fourth inverter INV4, its second input is connected to the output of the fourteenth D flip-flop D14 via the fifth inverter INV5, its third input is connected to the output of the fifteenth D flip-flop D15 via the sixth inverter INV6, and its fourth input is connected to the output of the sixteenth D flip-flop via the seventh inverter INV7. This gate performs an AND operation on the inverted signals from the outputs of the thirteenth to sixteenth D flip-flops, outputting a fifth intermediate signal. The seventh logic gate AND2 is a four-input AND gate. The seventh logic gate AND2 has four inputs connected to the outputs of the ninth D flip-flop D9, the tenth D flip-flop D10, the eleventh D flip-flop D11, and the twelfth D flip-flop D12, respectively. It performs AND logic operations on the output signals of the ninth to twelfth D flip-flops to output the sixth intermediate signal. The eighth logic gate AND3 is a two-input AND gate. Its second input is connected to the outputs of the sixth logic gate AND1 and the seventh logic gate AND2, respectively. It performs AND logic operations on the fifth and sixth intermediate signals to output the seventh intermediate signal. The seventeenth D flip-flop D17 has its data input connected to the seventh intermediate signal. Its output serves as the output of the latch unlock module 300, generating the enable signal 300_OUT.

[0035] In this embodiment, the latch unlocking sequence is as follows: Figure 7 As shown. This latch unlocking mechanism achieves controlled opening of the column address decoder through a preset unique unlocking code, preventing unauthorized reading of fuse information or erroneous adjustment operations, thus improving the security and reliability of the fuse adjustment system.

[0036] The fuse trimming system of the present invention, such as Figure 8 As shown, the fuse information column address module 400 includes: a latch unit 410, used to latch the first column selection address signal 200_D1_Q and the second column selection address signal 200_D2_Q output by the data input module 200; and also used to reset or set the D flip-flop in the latch under the action of the reset or set signal output by the initialization module 100; and a decoder unit 420, used to decode the column selection address signal latched by the latch unit 410 under the action of the enable signal 300_OUT output by the latch unlock module 300.

[0037] Specifically, in this embodiment, the fuse information column address module 400 is used to provide column address information to the fuse information module 500 during pre-adjustment. The fuse information column address module 400 consists of a latch unit 410 and a decoder unit 420; wherein, the latch unit 410 is composed of a D flip-flop, used to latch the output signal of the data input module 200 and output it to the decoder unit 420; the decoder unit 420 is used to decode the output of the latch unit 410 into the fuse column address information and output it to the fuse information module 500.

[0038] The fuse trimming system of the present invention, such as Figure 9As shown, the latch unit 410 includes: an eighteenth D flip-flop D18, the output of which is connected to the data input of the eighteenth D flip-flop D18 via an eighth inverter INV8, the output of which is used to output an eighth intermediate signal Q0, the eighth intermediate signal Q0 is inverted by the eighth inverter INV8 and input to the data input of the eighteenth D flip-flop D18; and a nineteenth D flip-flop D19, the data input of which is connected to a third signal, the output of which is used to output a ninth intermediate signal Q1, the third signal being the eighth intermediate signal Q0 and the ninth intermediate signal Q1. The XOR signal of intermediate signal Q1; the first XOR gate XOR1, the two inputs of the first XOR gate XOR1 are respectively connected to the outputs of the eighteenth D flip-flop D18 and the nineteenth D flip-flop D19, and the output of the first XOR gate XOR1 is connected to the data input of the nineteenth D flip-flop D19, used to generate the above-mentioned third signal; the twentieth D flip-flop D20, the data input of the twentieth D flip-flop D20 is connected to the fourth signal, and the output of the twentieth D flip-flop D20 is used to output the tenth intermediate signal, the fourth signal is the signal obtained by ANDing the eighth intermediate signal Q0 and the ninth intermediate signal Q1 and then XORing it with the tenth intermediate signal; the fourth AND gate AND4. The two inputs of the fourth AND gate AND4 are connected to the outputs of the eighteenth D flip-flop D18 and the nineteenth D flip-flop D19, respectively. The output of the fourth AND gate AND4 is connected to one of the inputs of the second XOR gate XOR2, used to perform an AND logic operation on the eighth intermediate signal Q0 and the ninth intermediate signal Q1. The two inputs of the second XOR gate XOR2 are connected to the outputs of the fourth AND gate AND4 and the twentieth D flip-flop D20, respectively. The output of the second XOR gate XOR2 is connected to the data input of the twentieth D flip-flop D20, used to generate the aforementioned fourth signal. The ninth logic gate AND5 is a three-input AND gate. The three inputs of gate AND5 are connected to the outputs of the eighteenth D flip-flop D18, the nineteenth D flip-flop D19, and the twentieth D flip-flop D20, respectively, and are used to perform AND logic operations on the eighth intermediate signal Q0, the ninth intermediate signal Q1, and the tenth intermediate signal Q2 to output the eleventh intermediate signal; gate NAND3 is a two-input NAND gate, and its two inputs are connected to the outputs of gate AND5 and latch unlocking module 300, respectively, and are used to perform AND and NOT logic operations on the eleventh intermediate signal and enable signal 300_OUT to output the twelfth intermediate signal Y1;The 21st D flip-flop D21 has its data input connected to the fifth signal. Its output generates the first latch signal D21_Q, and its inverted output generates the second latch signal D21_QN. The fifth signal is the OR / NOT signal of the inverted data signal DATA and the 11th intermediate signal. The 9th inverter INV9 has its input connected to the data signal DATA, and its output generates the inverted data signal DATA. The 1st NOR gate NOR1 has its two inputs connected to the 9th inverter INV9. The outputs of gate 9 and the tenth logic gate NAND3, and the output of the first NOR gate NOR1 are connected to the data input of the twenty-first D flip-flop D21. This is used to perform NOR operations on the inverted signal of the data signal DATA and the twelfth intermediate signal Y1 to obtain the aforementioned fifth signal. The data input of the twenty-second D flip-flop D22 is connected to the sixth signal. The output of the twenty-second D flip-flop D22 is used to generate the third latch signal D22_Q, and its inverted output is used to generate the fourth latch signal D22_QN. The sixth signal is the inverted signal of the first column selection address signal 200_D1_Q and the eleventh intermediate signal. NOR signal; Tenth inverter INV10, the input of the tenth inverter INV10 is connected to the first column selection address signal 200_D1_Q, and the output of the tenth inverter INV10 is used to generate the inverted signal of the first column selection address signal 200_D1_Q; Second NOR gate NOR2, the two inputs of the second NOR gate NOR2 are respectively connected to the output of the tenth inverter INV10 and the output of the tenth logic gate NAND3, and the output of the second NOR gate NOR2 is connected to the data input of the twenty-second D flip-flop D22, used to perform NOR logic on the inverted signal of the first column selection address signal 200_D1_Q and the twelfth intermediate signal Y1. The above-mentioned sixth signal is obtained through logical operations; the twenty-third D flip-flop D23, the data input terminal of the twenty-third D flip-flop D23 is connected to the seventh signal, the output terminal of the twenty-third D flip-flop D23 is used to generate the fifth latch signal D23_Q, and the inverted output terminal is used to generate the sixth latch signal D23_QN. The seventh signal is the OR-NOT signal of the inverted signal of the second column selection address signal and the eleventh intermediate signal; the eleventh inverter INV11, the input terminal of the eleventh inverter INV11 is connected to the second column selection address signal 200_D2_Q, and the output terminal of the eleventh inverter INV11 is used to generate the inverted signal of the second column selection address signal 200_D2_Q;The third NOR gate (NOR3) has two inputs connected to the outputs of the eleventh inverter (INV11) and the tenth logic gate (NAND3), respectively. The output of the third NOR gate (NOR3) is connected to the data input of the twenty-third D flip-flop (D23). This NOR gate performs a NOR operation on the inverted signal of the second column selection address signal 200_D2_Q and the twelfth intermediate signal Y1 to obtain the aforementioned seventh signal.

[0039] The fuse trimming system of the present invention, such as Figure 10As shown, the decoder unit 420 includes: an eleventh logic gate NAND4, which is a three-input NAND gate. The three inputs of the eleventh logic gate NAND4 are respectively connected to the inverted output of the twenty-first D flip-flop D21, the inverted output of the twenty-second D flip-flop D22, and the output of the twenty-third D flip-flop D23, and are used to perform NAND logic operations on the second latch signal D21_QN, the fourth latch signal D22_QN, and the fifth latch signal D23_Q, and output the thirteenth intermediate signal; and a twelfth logic gate NAND5, which is also a three-input NAND gate. The three inputs of the eleventh logic gate NAND4 are respectively connected to the inverted output of the twenty-first D flip-flop D21, the inverted output of the twenty-second D flip-flop D22, and the output of the twenty-third D flip-flop D23, and are used to perform NAND logic operations on the second latch signal D21_QN, the fourth latch signal D22_QN, and the fifth latch signal D23_Q, and output the thirteenth intermediate signal; and a twelfth logic gate NAND5, which is a three-input NAND gate. The input terminals are respectively connected to the output terminals of the twenty-first D flip-flop D21, the twenty-second D flip-flop D22, and the inverted output terminal of the twenty-third D flip-flop D23, and are used to perform NAND logic operations on the first latch signal D21_Q, the third latch signal D22_Q, and the sixth latch signal D23_QN, outputting the fourteenth intermediate signal; the thirteenth logic gate NAND6 is a three-input NAND gate, and its three input terminals are respectively connected to the inverted output terminals of the twenty-first D flip-flop D21, the twenty-second D flip-flop D22, and the twenty-third D flip-flop D23, and are used to perform NAND logic operations on the first latch signal D21_Q, the third latch signal D22_Q, and the sixth latch signal D23_QN, outputting the fourteenth intermediate signal; The second latch signal D21_QN, the third latch signal D22_Q, and the sixth latch signal D23_QN undergo NAND logic operations to output the fifteenth intermediate signal; the fourteenth logic gate NOR4 is a three-input NOR gate. Its three inputs are connected to the inverted output of the twenty-first D flip-flop D21, the output of the twenty-second D flip-flop D22, and the output of the twenty-third D flip-flop D23, respectively, and are used to perform NOR logic operations on the second latch signal D21_QN, the third latch signal D22_Q, and the fifth latch signal D23_Q to output the sixteenth intermediate signal; the fifteenth logic gate NOR5... The fifteenth logic gate, NOR5, is a three-input NOR gate. Its three inputs are connected to the outputs of the twenty-first D flip-flop D21, the twenty-second D flip-flop D22, and the twenty-third D flip-flop D23, respectively. It performs NOR operations on the first latch signal D21_Q, the third latch signal D22_Q, and the fifth latch signal D23_Q, outputting the seventeenth intermediate signal. The twelfth inverter, INV12, has its input connected to the output of the latch unlock module 300. Its output is used to generate the inverted enable signal 300_OUT.The sixteenth logic gate, NOR6, is a two-input NOR gate. Its two inputs are connected to the outputs of the twelfth inverter, INV12, and the eleventh logic gate, NAND4, respectively. It performs NOR operations on the inverted enable signal 300_OUT and the thirteenth intermediate signal, outputting the inverted first decoded signal, !COLUMN_DATA1. The thirteenth inverter, INV13, has its inputs connected to the output of the sixteenth logic gate, NOR6. Its output generates the first decoded signal, COLUMN_DATA1. The fourteenth... Inverter INV14: The input of the fourteenth inverter INV14 is connected to the output of the latch unlock module 300. The output of the fourteenth inverter INV14 is used to generate the inverted signal of the enable signal 300_OUT. Seventeenth logic gate NOR7: NOR7 is a two-input NOR gate. Its two inputs are connected to the output of the fourteenth inverter INV14 and the output of the twelfth logic gate NAND5, respectively. It is used to perform NOR logic operations on the inverted signal of the enable signal 300_OUT and the fourteenth intermediate signal, outputting the inverted signal of the second decoded signal !COLUMN_DATA2. Fifteenth inverter INV... 15. The input of the fifteenth inverter INV15 is connected to the output of the seventeenth logic gate NOR7. The output of the fifteenth inverter INV15 is used to generate the second decoding signal COLUMN_DATA2. The sixteenth inverter INV16 has its input connected to the output of the latch unlock module 300. Its output is used to generate the inverted signal of the enable signal 300_OUT. The eighteenth logic gate NOR8 is a two-input NOR gate. Its two inputs are connected to the output of the sixteenth inverter INV16 and the thirteenth logic gate NAND6, respectively. The output terminal is used to perform NOR logic operation on the inverted signal of the enable signal 300_OUT and the fifteenth intermediate signal, and output the inverted signal of the third decoded signal !COLUMN_DATA3; the seventeenth inverter INV17, the input terminal of the seventeenth inverter INV17 is connected to the output terminal of the eighteenth logic gate NOR8, and the output terminal of the seventeenth inverter INV17 is used to generate the third decoded signal COLUMN_DATA3; the eighteenth inverter INV18, the input terminal of the eighteenth inverter INV18 is connected to the output terminal of the latch unlock module 300, and the output terminal of the eighteenth inverter INV18 is used to generate the inverted signal of the enable signal 300_OUT;The nineteenth logic gate, NOR9, is a two-input NOR gate. Its two inputs are connected to the outputs of the eighteenth inverter, INV18, and the fourteenth logic gate, NOR4, respectively. It performs NOR operations on the inverted enable signal 300_OUT and the sixteenth intermediate signal, outputting the inverted fourth decoded signal, !COLUMN_DATA4. The nineteenth inverter, INV19, has its inputs connected to the output of NOR9. Its output generates the fourth decoded signal, COLUMN_DATA4. The twentieth inverter, INV20, is... The input of inverter INV20 is connected to the output of latch unlock module 300. The output of the twentieth inverter INV20 is used to generate the inverted signal of enable signal 300_OUT. The twentieth logic gate NOR10 is a two-input NOR gate. The two inputs of the twentieth logic gate NOR10 are connected to the output of the twentieth inverter INV20 and the output of the fifteenth logic gate NOR5 through a delay unit. It is used to perform NOR logic operation on the inverted signal of enable signal 300_OUT and the delayed signal of the seventeenth intermediate signal, and output the inverted signal of the fifth decoded signal !COLUMN_DATA5. The delay unit is implemented using an even number of inverters. This embodiment uses two inverters as an example. The delay unit includes a 21st inverter INV21 and a 22nd inverter INV22. The input of the 21st inverter INV21 is connected to the output of the 15th logic gate NOR5, and the output of the 21st inverter INV21 is connected to the input of the 22nd inverter INV22. The output of the 22nd inverter INV22 is used to generate the delayed signal of the 17th intermediate signal. A 23rd inverter INV23 has its input connected to the output of the 20th logic gate NOR10, and its output is used to generate the 5th decoded signal COLUMN_DATA5.

[0040] Specifically, the type of decoder in decoder unit 420 can be determined by the number of columns required by the number of fuses. In this embodiment, a 3-8 decoder is preferably used, and the column data selection timing is as follows: Figure 11 As shown, Figure 11 The timing diagram for selecting the first column of the fuse cell array is shown.

[0041] The correspondence between the key positions in the decoder unit 420 is shown in Table 1 below.

[0042] Table 1. Correspondence between key positions in decoder unit 420

[0043] In Table 1, 6P represents the second column selection address signal 200_D2_Q; 7P represents the first column selection address signal 200_D1_Q; and 8P represents the data signal DATA. These signals are output to the decoder selection column information in the decoder unit 420 via the flip-flops in the latch unit 410. Signals 1P~5P are the output signals of the remaining flip-flops inside the data input module 200. The decoder only needs to use the above three signals to meet the existing decoding requirements. The remaining signals are not output to the fuse information column address module 400 and are all at an invalid level of 0 in Table 1.

[0044] This invention supports column address extension redundancy design. When the number of fuse arrays needs to be expanded in the future, the output signal of the data input module 200 can be added and connected to the fuse information column address module 400 to realize the expansion of column address decoding resources, thereby completing the expansion and adaptation of the number of fuse array columns.

[0045] The fuse trimming system of the present invention, such as Figure 12 As shown, the address scanning module 700 is used to provide row / column address signals to the fuse unit array in the fuse unit module 600 during fuse adjustment. It includes a first logic unit and a second logic unit, used to perform OR logic operations on the first row address signals to the eighth row address signals in batches, followed by NOR logic operations, ultimately outputting the twenty-first intermediate signal. Each of the first and second logic units includes three OR gates and one NOR gate, and the structures of the two logic units are identical. Taking the first logic unit as an example, the first logic unit includes: the twenty-first logic gate OR4, used to perform OR logic operations on the first row address signal 1_ROW_ADDRESS and the second row address signal 2_ROW_ADDRESS, outputting the eighteenth intermediate signal; the twenty-second logic gate OR5, used to perform OR logic operations on the third row address signal 3_ROW_ADDRESS, the fourth row address signal 4_ROW_ADDRESS, and the fifth row address signal 5_ROW_ADDRESS, outputting the nineteenth intermediate signal; and the twenty-third logic gate OR6, used for… The second logic unit performs an OR logic operation on the sixth row address signal 6_ROW_ADDRESS, the seventh row address signal 7_ROW_ADDRESS, and the eighth row address signal 8_ROW_ADDRESS to output the twentieth intermediate signal; the twenty-fourth logic gate NOR11 is used to perform a NOR logic operation on the eighteenth, nineteenth, and twentieth intermediate signals to output the twenty-first intermediate signal; the second logic unit includes OR gate OR7, OR gate OR8, OR gate OR9, and NOR gate NOR12, and their connection method is the same as that of the first logic unit, which will not be described again here.

[0046] The first shift register unit includes the twenty-fourth to the thirty-first D flip-flops (D24-D31). The data input of the twenty-fourth D flip-flop D24 is connected to the twenty-first intermediate signal output by the first logic unit. The output of the previous stage D flip-flop is connected to the data input of the next stage D flip-flop. The clock inputs of the twenty-fourth to the thirty-first D flip-flops (D24-D31) are all connected to clock signals. The outputs of the twenty-fourth to the thirty-first D flip-flops (D24-D31) sequentially output the first to eighth row address signals. The second shift register unit includes the thirty-second to the thirty-ninth D flip-flops (D32-D39). The thirty-second D flip-flop D34... The data input terminal of 2 is connected to the twenty-first intermediate signal output by the second logic unit. The output terminal of the previous stage D flip-flop is connected to the data input terminal of the next stage D flip-flop. The clock terminals of the thirty-second to thirty-ninth D flip-flops (D32-D39) are all connected to the first row address signal 1_ROW_ADDRESS. The output terminal of the thirty-second D flip-flop D32 is used to output the first column address signal 1_COLUMN_ADDRESS. The output terminal of the thirty-third D flip-flop D33 is used to output the second column address signal 2_COLUMN_ADDRESS. The output terminals of the thirty-fourth to thirty-ninth D flip-flops (D34-D39) sequentially output the third to eighth row address signals.

[0047] Specifically, the address scanning module 700 is provided with a clock signal CLK by the clock port of the D flip-flop, which can realize the address scan from the first row of the first column to the eighth row of the first column, then to the first row of the second column, and finally to the eighth row of the eighth column. The timing is as follows: Figure 13 As shown.

[0048] The fuse adjustment system of the present invention includes a fuse unit module 600 for controlling the programming of fuses and reading fuse status information, such as... Figure 14 As shown, it includes: a delay unit 610, used to delay the power-on reset signal, output a first power-on delayed reset signal POR_LOW_PULSE1 and a second power-on delayed reset signal POR_LOW_PULSE2, and output a third power-on delayed reset signal POR_LOW_PULSE to the fuse information module 500; and a fuse unit 620, connected to the delay unit 610 and the address scanning module 700 respectively, used to output fuse status information based on the row address signal X1_ROW_ADDRESS (X1=1,2,...,8) and column address signal X2_COLUMN_ADDRESS (X2=1,2) output by the address scanning module 700, the first power-on delayed reset signal POR_LOW_PULSE1 and the second power-on delayed reset signal POR_LOW_PULSE2, and the output signal of the fuse information module 500.

[0049] Specifically, in this embodiment, the fuse unit module 600 includes a delay unit 610 and a fuse unit 620. The delay unit 610 is configured to provide a low-pulse signal to the fuse unit 620 and the fuse information module 500 after power-on reset. There are multiple fuse units 620, arranged in an array to form a fuse unit array. The number of fuse units in the array is configured by the number of fuses to be adjusted and the number of end-position fuse units. The structure of the end-position fuse unit is completely identical to that of each fuse unit in the array, such as... Figure 15 As shown.

[0050] The termination fuse unit is located at the end of the array and serves as a safe termination marker for the fuse trimming process. During normal trimming, if the termination fuse is not programmed, the system can continue to perform subsequent trimming operations on other fuse units; once the termination fuse is programmed, the system will determine that the trimming process is complete, and no further trimming operations can be performed on any fuse unit. This achieves irreversible locking of the trimming process, preventing accidental interruption or repeated operations, and improving the safety and controllability of fuse trimming.

[0051] For example, when the circuit of this invention needs to configure 39 fuses to complete the adjustment function, an additional end-bit fuse can be added; the address of this end-bit fuse is in the fifth column and eighth row, and its adjustment method is the same as that of the other fuses. After the adjustment is completed, the end-bit fuse can be selectively programmed. Similarly, this end-bit fuse is configured as follows: Figure 17 The fuse information unit shown outputs a high-level signal when the end-bit fuse blows, thereby blocking the adjustment operation authority of the subsequent control circuit.

[0052] Specifically, this latching logic is mainly used to control the enable function of the chip's power adjustment switching. If the fuse information unit corresponding to the end-bit fuse outputs a high level, the chip cannot complete the power adjustment switching action, which in turn prevents subsequent fuses from being blown due to insufficient power supply conditions.

[0053] Since the fuse programming process requires tens of milliamps of operating current, the fuse will not blow if the supply voltage across the fuse terminals is too low. Therefore, the circuit includes an internal power switching circuit for switching the fuse supply voltage. This power switching circuit consists of only one P-type metal-oxide-semiconductor (MOSFET). The source of the MOSFET is connected to the power supply at the designated port of the chip, while the drain provides operating power to the fuse array. A control signal is connected to the gate of the MOSFET to control the on / off state of the fuse power supply path, thus adapting to the voltage and current requirements of fuse programming. The structure is simple.

[0054] The fuse trimming system of the present invention, such as Figure 15As shown, each fuse unit in the array includes: a 25th logic gate AND6, which is a three-input AND gate. The three inputs of the 25th logic gate AND6 are respectively connected to the output of the corresponding D flip-flop in the address scanning module 700 and the output of the fuse information module 500. It is used to perform AND logic operations on the row address signal X1_ROW_ADDRESS, the column address signal X2_COLUMN_ADDRESS, and the output signal 500_OUT of the fuse information module to output the first control signal; and a first on / off switch, which is implemented by a first transistor Q1. The gate of the first transistor Q1 is connected to the first output of the delay unit 610, and the source of the first transistor Q1 is connected to one end of the fuse F1 to be adjusted. The other end of the fuse F1 to be adjusted is connected to the power supply voltage VDD. Under the action of the first power-on delay reset signal POR_LOW_PULSE1, the fuse F1 to be adjusted can be controlled to be connected to the power supply voltage VDD. The first node outputs fuse status information FUSE_DATA after being inverted by the twenty-fourth inverter INV24. The second on / off switch is implemented using the second transistor Q2. The gate of the second transistor Q2 is connected to the second output terminal of the delay unit 610, the source of the second transistor Q2 is connected to the ground terminal, and the drain of the second transistor Q2 is connected to the drain of the first transistor Q1. Under the action of the second power-on delay reset signal POR_LOW_PULSE2, the first node can be controlled to be connected to the ground terminal. The third on / off switch is implemented using the third transistor Q3. The gate of the third transistor Q3 is connected to the output terminal of the twenty-fifth logic gate AND6, the source of the third transistor Q3 is connected to the ground terminal, and the drain of the third transistor Q3 is connected to the source of the first transistor Q1. Under the action of the first control signal, the fuse F1 to be adjusted can be controlled to be connected to the ground terminal. When the third on / off switch is turned on, it pulls the source potential of the first transistor Q1 low.

[0055] Specifically, in this embodiment, the fuse unit module 600 is composed of a fuse unit array, and each fuse unit in the array has the dual functions of reading fuses and writing fuses.

[0056] During the power-on phase, the power-on reset signal POR provides a pulse signal to the system, and the delay unit 610 provides two low pulse signals, namely the first power-on delay reset signal POR_LOW_PULSE1 and the second power-on delay reset signal POR_LOW_PULSE2. Under the control of the power-on delay reset signal, each fuse unit completes the fuse status reading operation: if the fuse to be repaired has burned out, the fuse unit outputs a high-level FUSE_DATA signal to the fuse information module 500; otherwise, if the fuse has not burned out, it outputs a low-level signal to the fuse information module 500.

[0057] The timing sequence for reading fuse status information is as follows: Figure 16As shown, FUSE_DATA1 indicates that the fuse to be repaired has not burned out, and FUSE_DATA2 indicates that the fuse to be repaired has burned out.

[0058] After the pre-adjustment phase, the fuse adjustment phase begins. During this phase, the address scanning module 700 provides row and column address signals COLUMN_ADDRESS and ROW_ADDRESS to select and locate the target fuse cell. Simultaneously, the fuse information module 500 outputs a corresponding selection signal based on the pre-adjustment results. The internal programming control logic of the fuse cell is only triggered when the row and column address signals of the fuse cell and the output signal of the fuse information module 500 are all high, initiating the fuse programming operation. The duration of the programming process is controlled by the high-level duration of the clock signal CLK from the address scanning module, ensuring that the fuse stably blows under the set high current.

[0059] When the address scanning module 700 scans to the corresponding target fuse unit, making the COLUMN_ADDRESS and ROW_ADDRESS signals high at the same time, and the pre-adjustment logic also selects the fuse, the third transistor Q3 inside the fuse unit is turned on, and a large current flows through the two ends of the fuse to be adjusted F1, causing the fuse to be adjusted F1 to burn out, thereby completing the irreversible fuse adjustment operation.

[0060] In the fuse adjustment system of the present invention, the fuse information module 500 is composed of multiple fuse information units arranged in an array, and the array of fuse information units corresponds one-to-one with the array address of the fuse units, such as... Figure 17As shown, each fuse information unit includes: a 25th inverter INV25, whose input is connected to the output of the 24th inverter INV24, and whose output is used to generate the inverted signal of fuse status information FUSE_DATA; a 26th logic gate OR10, which is a two-input OR gate, whose two inputs are connected to the output of the 25th inverter INV25 and the third output of the delay unit 610, respectively, and is used to perform an OR logic operation on the inverted signal of fuse status information FUSE_DATA and the third power-on delay reset signal POR_LOW_PULSE, and output the 22nd intermediate signal to the asynchronous set terminal of the 40th D flip-flop D40; and a 27th logic gate OR11, which is a two-input OR gate, whose two inputs are connected to the inverted output of the 40th D flip-flop D40 and the output of the fuse information column address module 400, respectively, and is used to process the 8th signal! The decoded signal COLUMN_DATA output from the OUT and fuse information column address modules 400 is ORed to output the 23rd intermediate signal; the 28th logic gate OR12, a two-input OR gate, is used to OR the row data ROW_DATA and the inverted signal COLUMN_DATA output from the data input module 200 to output the 24th intermediate signal; the 29th logic gate NAND7, a two-input NAND gate, has its two inputs connected to the outputs of the 27th logic gate OR11 and the 28th logic gate OR12, respectively, to perform NAND operations on the 23rd and 24th intermediate signals to output the 25th intermediate signal; the 30th logic gate OR13, a two-input OR gate, has its two inputs connected to the outputs of the 27th logic gate OR11 and the 28th logic gate OR12, respectively, to perform NAND operations on the 23rd and 24th intermediate signals to output the 25th intermediate signal; and the 30th logic gate OR13, a two-input OR gate, has its two inputs connected to the outputs of the 27th logic gate OR11 and the 28th logic gate OR12, respectively. The output of inverter INV25 (25) and the third output of delay unit 610 are used to perform an OR logic operation on the fuse status information FUSE_DATA and the third power-on delay reset signal POR_LOW_PULSE to output the 26th intermediate signal; the 31st logic gate AND7 is a two-input AND gate, and its two inputs are connected to the output of the 30th logic gate OR13 and the power-on reset signal POR, respectively, to perform an AND logic operation on the 26th intermediate signal and the power-on reset signal POR to output the 27th intermediate signal;The data input of the 40th D flip-flop D40 is connected to the output of the 29th logic gate NAND7 to receive the 25th intermediate signal. Its clock input is connected to the clock signal CLK. The asynchronous set input D40 is connected to the 26th logic gate OR10 to receive the 22nd intermediate signal. The asynchronous reset input is connected to the output of the 31st logic gate AND7 to receive the 27th intermediate signal. The output of the 40th D flip-flop D40 is used to output the fuse information module's output signal 500_OUT. The inverted output is used to output the 8th signal to the input of the 27th logic gate OR11.

[0061] Specifically, in this embodiment, the fuse information module 500 is mainly used to read and latch the pre-adjustment information and the actual fuse adjustment information, and at the same time outputs the latched fuse information to the fuse unit module 600 and other circuits in the system that need adjustment to adjust the circuit parameters and functions.

[0062] The fuse information module consists of multiple fuse information units, which are arranged in an array to form a fuse information unit array. Each fuse information unit is mainly composed of combinational logic circuits and D flip-flops. The fuse information unit array corresponds one-to-one with the fuse unit array inside the fuse unit module 600 in terms of address, realizing precise matching and addressing by row and column address.

[0063] After the system powers on, the fuse unit module 600 reads the FUSE_DATA signal generated by each fuse unit 620, determines the actual fuse-broken state, and outputs the fuse information to the corresponding fuse information unit with the matching address in the fuse information module 500. The timing sequence for reading the fuse (fuse not blown) is as follows: Figure 18 As shown, if the fuse at the corresponding position is not blown, FUSE_DATA is a low pulse signal. The corresponding fuse information unit is then latched and outputs a low level, which is sent to the relevant circuit for parameter adjustment. Conversely, the timing for reading the fuse (if the fuse is blown) is as follows: Figure 19 As shown, if the fuse at the corresponding position has blown, FUSE_DATA will be a high-level signal. The corresponding fuse information unit will then synchronously latch and output the corresponding level to the back-end circuit. Taking the position of the first row of the first column in the array as an example, when the fuse in the first row of the first column has blown, the fuse information unit at the same address in the fuse information unit array will latch the status signal and output a high level.

[0064] This invention supports a pre-adjustment working mode. Pre-adjustment refers to using external ports and internal logic to control the state level of the corresponding fuse information unit before the fuse is actually blown, simulating the output effect after the fuse is blown. This tests whether the fuse adjustment logic can meet preset performance and parameter requirements, preventing incorrect adjustment codes from being written to the fuse and causing chip failure. During pre-adjustment, the column address module 400 and data input module 200 output column and row address signals to select the corresponding target fuse information unit in the array, causing the selected target fuse information unit to also output a high level. The pre-adjustment simulation operation can only be performed normally if the original fuse at the corresponding address is not blown. If the fuse at the corresponding address has actually blown, the fuse information unit will always maintain a high level output and will no longer be subject to pre-adjustment addressing control. The pre-adjustment timing is as follows: Figure 20 As shown.

[0065] The working process of the fuse trimming system of this invention is as follows: Figure 21 As shown, the specific steps are as follows: Step 1: The circuit is powered on. At this time, the power-on reset signal POR completes the full circuit reset. Each functional module (data input module, latch unlocking module, fuse information column address module, address scanning module, fuse unit module and fuse information module) enters the initial standby state, eliminating the indeterminate state of each D flip-flop. Step 2, test whether the circuit meets the requirements: if it does, then blow the last fuse, that is, control the fuse unit module to blow the end fuse at the end of the fuse unit array, complete the entire fuse adjustment process, lock the adjustment state, and no further adjustment operations will be performed; if it does not meet the requirements, proceed to step 3 to execute the pre-adjustment / adjustment data configuration process. Step 3, pre-adjustment / adjustment data configuration, involves inputting a preset unlock code through the data input module 200 and coordinating with clock signal synchronization control to complete initialization, unlocking, address selection, and other operations. This includes the following sub-steps: Step 3.1, initialize the tuning circuit. The initialization trigger condition is: while the clock signal CLK is held at a high level, the data signal DATA receives a falling edge signal, and then the clock signal CLK and the data signal DATA are synchronously set to high to complete the circuit initialization. Step 3.2: The latch unlocking module is unlocked. The clock signal CLK is used as the synchronous clock. The preset unlocking code "111100000" is input through the data signal DATA. After the internal register shifting and latching of the latch unlocking module and the combinational logic comparison and verification, the decoder circuit inside the fuse information column address module is unlocked, and the column address signal becomes effective. Step 3.3: Encode the column data. Use the clock signal CLK as the synchronization clock and input the column address code "00000xxx0" (where "xxx" is the column address selection bit) through the data signal DATA. For example, when the data signal DATA inputs "000001000", the first column of the fuse unit array and fuse information unit array is selected, and the latch unit is triggered to latch the column address code to ensure that the column address is valid.

[0066] Step 3.4: Input row data encoding. Use the clock signal CLK as the synchronization clock and input the row address encoding "xxxxxxxx0" through the data signal DATA (where "xxxxxxxx" is the row address selection bit). For example, when the data signal DATA inputs "001000000", the third row of the fuse unit array and fuse information unit array is selected, and the row and column address selection of the target adjustment unit is completed.

[0067] Step 4: Test again to see if it meets the requirements: If it does not meet the requirements, return to Step 3 and re-execute the pre-adjustment / adjustment data configuration process to adjust the row and column addresses and adjustment parameters; if it meets the requirements, proceed to Step 5 and execute the pre-adjustment process. Step 5: Pre-tuning, completing the programming control of the target fuse, specifically including the following sub-steps: Step 5.1: Initialize the tuning circuit. The initialization trigger condition is the same as in Step 3.1. While the clock signal CLK is held high, the data signal DATA receives a falling edge signal. Then, the clock signal CLK and the data signal DATA are synchronously set high to complete the secondary initialization of the tuning circuit. Step 5.2: Unlock the latch unlock module. Use the clock signal CLK as the synchronous clock and input the preset unlock code "111100000" again through the data signal DATA to ensure that the decoder circuit of the fuse information column address module remains unlocked and that the column address signal is effective. Step 5.3: Encode the input column data. Use the clock signal CLK as the synchronization clock and input the target column address code "000001000" through the data signal DATA. Select the first column of the fuse unit array and fuse information unit array to provide column address positioning for subsequent fuse programming. Step 5.4: Encode the incoming row data, using the clock signal CLK as the synchronization clock, and input the target row address code "001000000" through the data signal DATA to accurately select the 3rd row of the fuse unit array and fuse information unit array, thus completing the final addressing of the target fuse unit; Step 5.5: Initialize the tuning circuit. The initialization trigger condition is the same as in Steps 3.1 and 5.1: While the clock signal CLK is held high, the data signal DATA receives a falling edge signal. Then, the clock signal CLK and the data signal DATA are synchronously set high, completing the last initialization before fuse burning. Step 5.6: Fuse address scanning. The clock signal CLK is used as the scanning clock to provide a synchronous trigger signal for the address scanning module. At the same time, the data signal DATA provides working power for the adjustment circuit. The address scanning module scans the target fuse unit according to the preset timing sequence, triggering the fuse unit module to perform the fuse writing operation, completing the irreversible blowing of the target fuse, and realizing the final calibration of the circuit parameters.

[0068] The fuse trimming system of this invention can control the programming of multiple fuses, is easy to operate, has strong scalability, and high reliability. The system adopts a control circuit with pre-trimming and trimming functions, realizing trimming after wafer flipping, reducing costs, improving trimming accuracy, and avoiding the high cost and accuracy deviation of trimming before packaging.

[0069] The present invention also provides a chip that integrates the above-mentioned fuse adjustment system. By integrating the fuse adjustment system with the chip body, the internal parameters of the chip can be autonomously adjusted and calibrated without the need for additional external adjustment circuits. This simplifies the overall structure of the chip, reduces chip packaging and application costs, and improves the stability and consistency of the chip.

[0070] The chip integrating the fuse adjustment system of the present invention has four stages in its overall working process: power-on initialization stage, pre-adjustment verification stage, formal fuse adjustment stage, and post-adjustment locking stage.

[0071] During the power-on initialization phase, after the circuit is powered on, the initialization module simultaneously receives three input signals: the power-on reset signal POR, the external clock signal CLK, and the external data signal DATA. It performs a unified reset or set operation on all D flip-flops inside the circuit, including the shift registers set in the data input module, the fuse information units set in the fuse information module, and the latches set in the latch unlocking module. This ensures that all functional modules are stably in the initial zero-position state after power-on, clearing the random residual state data generated at the moment of power-on. This lays a reliable timing and state foundation for subsequent adjustment of the encoding input, as well as fuse addressing, reading, and programming operations.

[0072] During the pre-tuning verification phase, the correctness of the tuning code can be verified without actually writing the fuse, thus preventing permanent chip failure caused by incorrect tuning codes being written to the fuse. This phase begins with unlocking preparation. The external tuning code is sent to the data input module via the data signal DATA. This data input module uses a serial-in parallel-out shift register structure composed of D flip-flops. The external clock signal CLK provides synchronous timing drive for the shift register. The data input module transmits a preset unlock code to the latch unlock module. After verifying and matching the received unlock code, the latch unlock module outputs a valid unlock signal to the fuse information column address module, releasing the hardware lock state of the fuse information column address module. Subsequently, address positioning is performed. The data input module continues to output column address signals to the fuse information column address module, and simultaneously outputs row address signals. The fuse information column address module latches the column address signals using an internal latch. The system supports the output of a high-level column address signal after decoding by the built-in decoder. This signal, in conjunction with the row address signal, uniquely corresponds to the fuse information unit in the selected fuse information module that matches the fuse to be repaired. Finally, a simulation verification is performed. The fuse information unit uniquely addressed by the row and column addresses responds to the address validity signal by undergoing an internal level flip and outputting a high level, electrically simulating the state after the fuse has blown. Simultaneously, a pre-repair configuration level is output to the circuit to be repaired inside the chip, thereby checking whether the key electrical parameters of the chip meet the design specifications. If the parameters do not meet the design standards, the external repair code can be directly changed and the above pre-repair process can be repeated. The entire verification process does not require any action on the actual fuse hardware, has no hardware loss, and can iteratively complete the optimal matching of the repair code.

[0073] During the formal fuse tuning phase, this invention employs a three-signal phase and high-level triggering mechanism to avoid address crosstalk and false triggering that could lead to incorrect fuse writing, thus achieving precise and controllable fuse writing. Once the pre-tuning verification confirms the tuning code matching is valid and the chip's electrical parameters meet design requirements, the formal fuse writing process begins: First, the address scanning module responds to external control logic, outputting high-level valid row and column address signals to the fuse array within the fuse unit module to locate the target single fuse to be written. Simultaneously, the corresponding fuse information unit locked by the pre-tuning verification in the fuse information module maintains a high-level output state and synchronously transmits this state to the fuse unit module as a tuning enable condition. The fuse unit module only responds when the row address signal and column address signal are valid. The internal path is activated to initiate the target fuse programming operation only when the address signal, the fuse information unit output status signal, and the address scanning module's clock signal CLK are all at a high level. The duration of the fuse programming operation is precisely controlled by maintaining a high level for the duration of the clock signal CLK, ensuring that the fuse is completely blown without overburning. After the fuse programming is completed, the fuse unit module collects the actual blown status of the fuse in real time. If the fuse is blown, it outputs a high level; if it is not blown, it outputs a low level. The collected fuse status information is then sent back to the corresponding fuse information unit in the fuse information module to complete the status refresh.

[0074] During the post-adjustment locking phase, after the fuse is formally adjusted, the circuit enters a locked state to prevent the adjustment result from being tampered with externally, ensuring the stability and immutability of the adjustment result. Specifically, after the fuse is formally adjusted, the fuse information module receives the actual fuse state returned by the fuse unit module and permanently latches and solidifies the fuse state through an internal latching timing circuit. Subsequent power-ups do not require re-entering the adjustment code; the fuse information module can directly output a fixed adjustment level to the circuit to be adjusted within the chip, achieving persistent adjustment state. Simultaneously, the latch unlocking module returns to the locked state and no longer responds to externally input unlocking codes and adjustment codes, preventing subsequent misoperations from arbitrarily altering the adjustment state. In addition, the initialization module, data input module, address scanning module, and other functional modules enter a low-power sleep mode after adjustment, reducing the overall static and dynamic power consumption of the chip integrating this fuse adjustment system.

[0075] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A fuse trimming system, characterized by, include: The data input module receives clock and data signals, generates column selection address signals and row data through shift registers, and transmits the clock and data signals to the latch unlock module and the fuse information column address module. The latch unlock module, connected to the data input module, latches the data signal according to the clock signal and generates an enable signal when the latched data matches a preset unlock code. The fuse information column address module, connected to both the data input module and the latch unlock module, releases the locked state of the fuse information column address according to the enable signal, latches the column selection address signal, and, during the fuse pre-adjustment phase, adjusts the latched column selection address signal. The clock signal is decoded, and a decoded signal is output. The address scanning module is used to generate the row address signal and column address signal of the fuse during the fuse adjustment stage according to the clock signal. The fuse unit module is connected to the address scanning module and is used to program the target fuse unit according to the row address signal and column address signal output by the address scanning module and the delayed power-on reset signal, and output fuse status information at the same time. The fuse information module is connected to the data input module, the fuse information column address module and the fuse unit module respectively, and is used to read the fuse status information output by the fuse unit module according to the decoded signal, the row data and the delayed power-on reset signal, and latch the fuse status information.

2. The fuse trimming system of claim 1, wherein The data input module includes a shift register, which includes a first to an eighth D flip-flop. The data input terminal of the first D flip-flop is used to receive the data signal. The inverted output terminal of the previous stage D flip-flop is connected to the data input terminal of the next stage D flip-flop through an inverter. The inverted output terminals of all the D flip-flops are connected to the fuse information module. The output terminals of the first to second D flip-flops are connected to the fuse information column address module.

3. The fuse trimming system of claim 1, wherein The latch unlocking module includes: a ninth to a sixteenth D flip-flop, the data input terminal of the ninth D flip-flop being used to receive the data signal, and the output terminal of the preceding D flip-flop being connected to the data input terminal of the following D flip-flop; a sixth logic gate, used to perform an AND logic operation on the inverted signals of the output terminals of the thirteenth to sixteenth D flip-flops, outputting a fifth intermediate signal; a seventh logic gate, used to perform an AND logic operation on the output terminals of the ninth to twelfth D flip-flops, outputting a sixth intermediate signal; an eighth logic gate, used to perform an AND logic operation on the fifth intermediate signal and the sixth intermediate signal, outputting a seventh intermediate signal; and a seventeenth D flip-flop, the data input terminal of which is connected to the seventh intermediate signal, and the output terminal of which serves as the output terminal of the latch unlocking module, used to generate an enable signal.

4. The fuse trimming system according to claim 1, characterized in that, The fuse information column address module includes: a latch unit for latching the first column selection address signal and the second column selection address signal output by the data input module; and a decoder unit for decoding the column selection address signal latched by the latch unit under the action of the enable signal output by the latch unlock module.

5. The fuse trimming system according to claim 4, characterized in that, The latch unit includes: an eighteenth D flip-flop, the data input of which is connected to the inverted signal of an eighth intermediate signal, and the output of which is used to output the eighth intermediate signal; a nineteenth D flip-flop, the data input of which is connected to a third signal, and the output of which is used to output a ninth intermediate signal, wherein the third signal is the XOR signal of the eighth and ninth intermediate signals; a twentieth D flip-flop, the data input of which is connected to a fourth signal, and the output of which is used to output a tenth intermediate signal, wherein the fourth signal is the signal obtained by performing an AND operation on the eighth and ninth intermediate signals and then an XOR operation on the tenth intermediate signal; a ninth logic gate, used to perform an AND operation on the eighth, ninth, and tenth intermediate signals to output an eleventh intermediate signal; and a tenth logic gate, used to perform a NAND operation on the eleventh intermediate signal and the enable signal. The algorithm performs a logical operation, outputting the twelfth intermediate signal; the twenty-first D flip-flop, with its data input connected to the fifth signal, its output used to generate the first latch signal, and its inverted output used to generate the second latch signal, wherein the fifth signal is the inverted signal of the data signal and the NOR signal of the eleventh intermediate signal; the twenty-second D flip-flop, with its data input connected to the sixth signal, its output used to generate the third latch signal, and its inverted output used to generate the fourth latch signal, wherein the sixth signal is the inverted signal of the first column selection address signal and the NOR signal of the eleventh intermediate signal; the twenty-third D flip-flop, with its data input connected to the seventh signal, its output used to generate the fifth latch signal, and its inverted output used to generate the sixth latch signal, wherein the seventh signal is the inverted signal of the second column selection address signal and the NOR signal of the eleventh intermediate signal.

6. The fuse trimming system of claim 5, wherein, The decoder unit includes: an eleventh logic gate, used to perform a NAND logic operation on the second latch signal, the fourth latch signal, and the fifth latch signal, and output a thirteenth intermediate signal; a twelfth logic gate, used to perform a NAND logic operation on the first latch signal, the third latch signal, and the sixth latch signal, and output a fourteenth intermediate signal; a thirteenth logic gate, used to perform a NAND logic operation on the second latch signal, the third latch signal, and the sixth latch signal, and output a fifteenth intermediate signal; a fourteenth logic gate, used to perform a NOR logic operation on the second latch signal, the third latch signal, and the fifth latch signal, and output a sixteenth intermediate signal; a fifteenth logic gate, used to perform a NOR logic operation on the first latch signal, the third latch signal, and the fifth latch signal, and output a seventeenth intermediate signal; and a sixteenth logic gate, used to perform an enable signal... The system performs a NOR operation on the inverted signal of the enable signal and the thirteenth intermediate signal to output a first decoded signal and its inverted signal; the seventeenth logic gate performs a NOR operation on the inverted signal of the enable signal and the fourteenth intermediate signal to output a second decoded signal and its inverted signal; the eighteenth logic gate performs a NOR operation on the inverted signal of the enable signal and the fifteenth intermediate signal to output a third decoded signal and its inverted signal; the nineteenth logic gate performs a NOR operation on the inverted signal of the enable signal and the sixteenth intermediate signal to output a fourth decoded signal and its inverted signal; and the twentieth logic gate performs a NOR operation on the inverted signal of the enable signal and the delayed signal of the seventeenth intermediate signal to output a fifth decoded signal and its inverted signal.

7. The fuse trimming system of claim 1, wherein The address scanning module includes: a first logic unit and a second logic unit, each including: a twenty-first logic gate, used to perform an OR logic operation on the first row address signal and the second row address signal, outputting an eighteenth intermediate signal; a twenty-second logic gate, used to perform an OR logic operation on the third row address signal, the fourth row address signal, and the fifth row address signal, outputting a nineteenth intermediate signal; a twenty-third logic gate, used to perform an OR logic operation on the sixth row address signal, the seventh row address signal, and the eighth row address signal, outputting a twentieth intermediate signal; and a twenty-fourth logic gate, used to perform a NOR logic operation on the eighteenth, nineteenth, and twentieth intermediate signals, outputting a twenty-first intermediate signal; and a first shift register unit, including twenty-fourth to thirty-first D flip-flops, the data input terminal of the twenty-fourth D flip-flop being connected to the twenty-first intermediate signal output by the first logic unit. The intermediate signal is connected to the data input of the next stage D flip-flop. The clock inputs of the 24th to 31st D flip-flops are all connected to the clock signal. The outputs of the 24th to 31st D flip-flops sequentially output the address signals for the first to eighth rows. The second shift register unit includes the 32nd to 39th D flip-flops. The data input of the 32nd D flip-flop is connected to the 21st intermediate signal output by the second logic unit. The output of the previous stage D flip-flop is connected to the data input of the next stage D flip-flop. The clock inputs of the 32nd to 39th D flip-flops are all connected to the first row address signal. The output of the 32nd D flip-flop is used to output the first column address signal. The output of the 33rd D flip-flop is used to output the second column address signal. The outputs of the 34th to 39th D flip-flops sequentially output the address signals for the third to eighth rows.

8. The fuse trimming system of claim 1, wherein The fuse unit module includes: a delay unit, used to delay the power-on reset signal, output a first power-on delayed reset signal and a second power-on delayed reset signal, and output a third power-on delayed reset signal to the fuse information module; and a fuse unit, connected to the delay unit and the address scanning module, used to output fuse status information based on the row address signal and column address signal output by the address scanning module, the first power-on delayed reset signal and the second power-on delayed reset signal, and the output signal of the fuse information module.

9. The fuse trimming system according to claim 8, characterized in that, The fuse unit comprises multiple units, each of which includes: a 25th logic gate, used to perform an AND logic operation on the row address signal, column address signal, and output signal of the fuse information module to output a first control signal; a first on / off switch, which can controllably connect the fuse to be repaired to a first node under the action of the first power-on delay reset signal, and the first node outputs the fuse status information via inversion; a second on / off switch, which can controllably connect the first node to a ground terminal under the action of the second power-on delay reset signal; and a third on / off switch, which can controllably connect the fuse to be repaired to the ground terminal under the action of the first control signal.

10. The fuse trimming system of claim 8, wherein, The fuse information module is composed of multiple fuse information units arranged in an array. The array of fuse information units corresponds one-to-one with the array address of the fuse units. Each fuse information unit includes: a 26th logic gate, used to perform an OR logic operation on the inverted signal of the fuse status information and the third power-on delay reset signal, outputting a 22nd intermediate signal; a 27th logic gate, used to perform an OR logic operation on the 8th signal and the decoded signal output by the fuse information column address module, outputting a 23rd intermediate signal; a 28th logic gate, used to perform an OR logic operation on the row data output by the data input module and the inverted signal of the decoded signal, outputting a 24th intermediate signal; and a 29th logic gate, used to perform an OR logic operation on the 23rd intermediate signal and the 24th intermediate signal. The system performs a NAND logic operation on the intermediate signal and the twenty-fourth intermediate signal to output the twenty-fifth intermediate signal; the thirtieth logic gate performs an OR logic operation on the fuse status information and the third power-on delay reset signal to output the twenty-sixth intermediate signal; the thirty-first logic gate performs an AND logic operation on the twenty-sixth intermediate signal and the power-on reset signal to output the twenty-seventh intermediate signal; the fortieth D flip-flop has its data input terminal connected to the twenty-fifth intermediate signal, its asynchronous set terminal connected to the twenty-second intermediate signal, and its asynchronous reset terminal connected to the twenty-seventh intermediate signal. The output terminal of the fortieth D flip-flop is used to output the output signal of the fuse information module, and its inverted output terminal is used to output the eighth signal.

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