An advanced process chip failure hot spot positioning method and system

Abstract

The application discloses a kind of advanced process chip failure hotspot positioning method and system, belong to semiconductor advanced technology process detection and failure analysis technical field.The method includes: to be measured chip is prepared and establishes chip back coordinate system by back observation;According to preset excitation sequence, at least two groups of different conditions are applied Current excitation, back light emission image is synchronously collected;Multiple images are executed registration and joint denoising, and candidate hotspot set is extracted;Based on the dynamic light response characteristics and spatial distribution characteristics of candidate hotspot under different current excitation conditions, dynamic defect probability index is calculated to determine hotspot priority;According to the highest priority candidate hotspot, output failure analysis coordinate information.The application is through multi-excitation linkage and multidimensional probability index evaluation, and is combined with solid-state immersion lens technology, substantially filters out thermal effect false hotspot, reduces candidate hotspot number by more than 75%, positioning error is reduced to 2.1 μm or less, and verification closed loop period is shortened by 59.3%, applicable to advanced logic, memory and advanced packaging and other scenes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor advanced process inspection and failure analysis technology, and in particular to an advanced process chip failure hotspot location method and system based on the linkage of back-side light emission and current excitation. Background Technology

[0002] As semiconductor manufacturing processes continue to evolve towards 7nm, 5nm, and 3nm nodes, the number of metal interconnect layers within chips is constantly increasing. Device structures are transitioning from planar MOSFETs to FinFETs and Gate-All-Around FETs (GAA-FETs), and the stacked layers of 3D NAND flash memory have exceeded 200. Simultaneously, the widespread application of advanced packaging technologies such as Through-Silicon Vias (TSVs), Fan-Out Wafer-Level Packaging (FOWLP), and Hybrid Bonding has further improved the three-dimensional integration of chips. These technological advancements mean that failure analysis targets are often located deep within metal layers, interface layers, or high aspect ratio structures, making traditional methods of failure localization from the front of the chip ineffective in reaching the target area.

[0003] Backside photon emission microscopy (PSM) technology utilizes the transparency of silicon in the near-infrared band to observe the weak photon emission generated during device operation from the back of the chip due to mechanisms such as electron-hole recombination and hot carrier effects. It has become an important method for locating failures in advanced process chips. However, existing backside photon emission analysis schemes still have the following shortcomings in engineering practice: First, existing solutions typically perform only one optical emission observation under a single current condition, lacking the ability to acquire data under multiple excitation conditions. Since different types of failure defects (such as gate oxide breakdown, metal interconnect electromigration, via voids, etc.) have different response characteristics to current excitation, optical emission images obtained under a single excitation condition often cannot effectively distinguish between real failure hotspots and background noise or spurious signals, resulting in an excessive number of candidate hotspots that need to be verified one by one, leading to low analysis efficiency.

[0004] Second, existing solutions lack a systematic mechanism for denoising and prioritizing hotspot maps. False hotspot signals generated by factors such as detector dark current, environmental thermal radiation, and pixel defects are mixed with real failed hotspots, requiring analysts to rely on experience for manual judgment, which is not only inefficient but also has a high error rate.

[0005] Third, in the workflow transition from light emission positioning to subsequent analysis (such as focused ion beam cutting and nanoprobe electrical measurements), existing solutions often lack a unified coordinate reference and result inheritance mechanism. Inconsistent coordinate systems between different analytical devices lead to the accumulation of positioning errors, often requiring repeated unpacking and imaging, resulting in sample damage and prolonged analysis cycles. Summary of the Invention

[0006] The purpose of this invention is to provide an advanced process chip failure hotspot location method and system based on the linkage of back-side light emission and current excitation, so as to solve the problems of lack of excitation condition linkage, large number of candidate hotspots and high misjudgment rate, and difficulty in inheriting the location coordinates in subsequent analysis processes in the prior art.

[0007] To achieve the above objectives, the present invention provides a method for locating failure hotspots in advanced process chips, comprising the following steps: S1, prepare for back-side observation of the chip under test, and establish a chip back-side coordinate system based on the physical characteristics of the chip under test; S2, apply at least two sets of current excitations under different conditions to the chip under test according to a preset excitation sequence, and simultaneously acquire the corresponding back light emission image under each set of current excitation conditions; S3, register and jointly denoise the multiple frames of back light emission images acquired under each group of current excitation conditions, and extract a set of candidate hotspots whose luminescence features meet a preset threshold. S4. Based on the dynamic luminescence response characteristics and spatial distribution characteristics of the candidate hotspots under different current excitation conditions, calculate and determine the priority ranking of each candidate hotspot. S5. Based on the priority sorting, output the failure analysis coordinate information of at least one high-priority candidate hot spot.

[0008] Furthermore, the preset excitation sequence includes at least two constant current excitations, pulse excitations, or a combination of constant current and pulse excitations with different amplitudes; The constant current excitation current amplitude ranges from 5mA to 40mA; the pulse width of the pulse excitation ranges from 50ns to 2μs.

[0009] Furthermore, the joint denoising process described in step S3 includes: Dark field background radiation subtraction is performed on each frame of back-side light emission image to eliminate dark current noise and environmental thermal radiation interference; Perform outlier removal based on spatially connected components to remove single-pixel spurious signals; Alignment superposition average enhancement is performed on no less than 5 frames of images under the same set of current excitation conditions to improve the signal-to-noise ratio of weak luminous hot spots, wherein the exposure integration time of a single frame image is 20ms to 200ms.

[0010] Furthermore, the dynamic light emission response characteristics described in step S4 include: Hotspot intensity: Characterizes the average light emission intensity of candidate hotspots under various excitation conditions; Normalized excitation response slope: Characterizes the gradient of the light emission intensity of the candidate hotspot as a function of the applied current excitation, and is mapped to a preset numerical range after feature scaling. The spatial distribution characteristics include: Positional stability: characterizes the degree of dispersion of the centroid coordinates of the same candidate hotspot across multiple frames of images; Spatial convergence: characterizes the convergence trend of the luminescent region area of ​​candidate hotspots shrinking as the excitation current increases; Layout relevance: Characterizes the spatial correspondence between candidate hotspot locations and key structures in the chip layout.

[0011] Furthermore, the priority ranking in step S4 is based on a dynamic defect probability index. The calculation formula for the dynamic defect probability index is as follows:

[0012] in: A comprehensive priority score is given to the candidate hotspots; The average signal-to-noise ratio of the candidate hotspot across multiple frames after joint denoising processing; The slope of the normalized excitation response is defined, with a value range of [0, 1]. The spatial variance of the centroid coordinates of the same candidate hotspot across multiple frames of images characterizes its positional stability. The equivalent pixel area of ​​the candidate hotspot luminescent region; This is the map relevance coefficient, with a value range of [0, 1]. All are preset normalized weight coefficients, and satisfy the following conditions: .

[0013] Furthermore, the failure analysis coordinate information mentioned in step S5 includes: The absolute coordinates of the hotspot center and the range of the hotspot boundary, based on the aforementioned back coordinate system.

[0014] Furthermore, before outputting the failure analysis coordinate information, the method further includes: Extract chip layout markers or package structure markers, and use the markers to calibrate the back coordinate system. The calibration includes at least one of translation compensation, rotation compensation, and scaling compensation.

[0015] This invention also provides an advanced process chip failure hotspot location system, comprising: The excitation control module is used to apply at least two sets of current excitations with different conditions to the chip under test according to a preset excitation sequence. The back light emission acquisition module is connected to the excitation control module via a synchronous trigger bus. When it receives the excitation synchronization signal, it performs time-synchronous acquisition of the back light emission image of the chip under test. An image processing module is communicatively coupled to the back-side light emission acquisition module to receive multi-frame image data streams. The image processing module is configured to perform inter-frame registration and joint denoising processing on the image data streams and output a set of candidate hotspots containing feature coordinates downstream. The hotspot sorting module takes the candidate hotspot set and the current state data from the excitation control module as input, and calls an external layout database. It is configured to execute the calculation formula of the dynamic defect probability index as described in claim 5, thereby generating a priority sorting sequence for each candidate hotspot. The coordinate output module, logically connected to the hotspot sorting module, is used to receive the highest priority candidate hotspot information and, in conjunction with a preset coordinate reference, convert it into failure analysis coordinate information adapted to subsequent analysis equipment, thereby forming a closed-loop data link of "excitation-acquisition-evaluation-mapping" in the entire positioning system.

[0016] Furthermore, the back-side light emission acquisition module includes a near-infrared detector and a solid-state immersion lens coupled to the front end of the detector's optical path, and the response band of the near-infrared detector covers 900nm to 1700nm. The excitation control module is configured to output at least one of a constant current mode and a pulse mode, wherein the output range of the constant current mode is 5mA to 40mA, and the pulse width of the pulse mode is adjustable from 50ns to 2μs.

[0017] Furthermore, the coordinate output module is configured to output the failure analysis coordinate information in a target coordinate format suitable for focused ion beam equipment, nanoprobe equipment, or scanning electron microscope, and simultaneously output absolute coordinates, relative coordinates, and conversion parameters adapted to subsequent equipment.

[0018] Compared with the prior art, the present invention has the following beneficial effects: (1) Reduce candidate hotspots and reduce damage risk: By using multi-excitation linkage and multi-frame joint denoising, false hotspot signals are effectively filtered out, reducing the number of candidate hotspots that need physical verification and reducing the risk of damage to the sample by subsequent destructive verification. (2) Improve positioning accuracy and optimize equipment guidance: By introducing a multi-dimensional priority index model to sort candidate hotspots, the positioning error is reduced, and reliable coordinate guidance is provided for the accurate connection of equipment such as FIB or nanoprobes. (3) Reduce transfer error and shorten the analysis cycle: By constructing a unified coordinate benchmark and outputting coordinate transformation parameters adapted to the equipment, the coordinate compatibility between platforms is improved, secondary positioning error is reduced, and the closed-loop cycle of failure analysis is shortened. (4) Strong scenario versatility and wide adaptability: The system architecture and linkage method do not need to change the underlying hardware, and can adapt to the positioning of deep buried defects in various complex structures such as advanced logic chips, three-dimensional high-density memory and advanced packaging components. Attached Figure Description

[0019] Figure 1 A schematic diagram of the system architecture and module connection of an advanced process chip failure hotspot location system based on back-side light emission and current excitation provided in an embodiment of the present invention; Figure 2 A flowchart of the back-side light emission hotspot localization method provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a hotspot map and map mapping scenario provided in an embodiment of the present invention; Figure 4 A schematic diagram of the key parameter window provided in the embodiments of the present invention; Figure 5 The verification effect comparison chart provided for the embodiments of the present invention; Figure 6 These are schematic diagrams illustrating different implementation methods provided in this invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0021] like Figure 1As shown, the system provided in this embodiment of the invention includes at least the following five functional modules: an excitation control module 101, a back-side light emission acquisition module 102, an image processing module 103, a hotspot ranking module 104, and a coordinate output module 105. The excitation control module 101 and the back-side light emission acquisition module 102 are connected via a synchronous trigger bus to ensure strict timing synchronization between current excitation and light emission acquisition. The image processing module 103 is communicatively coupled to the acquisition module 102 to receive multi-frame image data streams and perform noise reduction processing. The hotspot ranking module 104 receives a set of candidate hotspots and current state data from the excitation control module, and calls an external layout database to perform priority calculations. The coordinate output module 105 converts the ranking results into a coordinate format suitable for subsequent analysis equipment. These modules form a closed-loop data link of "excitation-acquisition-evaluation-mapping" around a unified coordinate reference.

[0022] like Figure 2 As shown, the main technical process of this invention includes the following steps: Step S101: Backside observation preparation and coordinate system establishment. A backside thinning process is performed on the chip under test. Specifically, firstly, most of the silicon substrate material is removed by mechanical polishing, and then fine thinning is performed by chemical mechanical polishing (CMP) to control the remaining silicon thickness within the range of 10μm to 100μm. The thinned silicon substrate has sufficient transmittance in the near-infrared band (approximately 900nm to 1700nm), allowing photon signals generated during the operation of internal devices to pass through the backside and be collected by the detector. After thinning is completed, a backside observation coordinate system is established with reference to the alignment marks on the chip package or the feature structures in the layout. This coordinate system will serve as the unified spatial reference for all subsequent analysis operations.

[0023] Step S102: Current Excitation Application and Backside Light Emission Image Acquisition. According to a preset excitation sequence, at least two different sets of current excitation conditions are applied to the chip under test via the excitation control module. The excitation mode can be constant current mode, pulse mode, or a combination of both. In constant current mode, the current amplitude can be set within the range of 5mA to 40mA, preferably within the range of 18mA to 28mA; in pulse mode, the pulse width can be adjusted within the range of 50ns to 2μs, preferably within the range of 200ns to 800ns. Using a shorter pulse width helps reduce the thermal diffusion effect of the sample and reduces the diffusion of pseudo-hot spots caused by thermal effects. Simultaneously with the application of each set of excitation conditions, the backside light emission acquisition module acquires the corresponding images.

[0024] Specifically, for advanced processes such as 5nm / 3nm, to overcome the spot dispersion problem caused by the near-infrared optical diffraction limit, the acquisition module preferably couples a solid-state immersion lens (SIL) at the front end of the detector (such as an InGaAs infrared detector). SIL technology significantly improves the system's numerical aperture (NA), effectively enhancing spatial resolution and ensuring accurate acquisition of the emitting area and location of extremely small defects. The single-frame exposure integration time can be set within the range of 20ms to 200ms, preferably 60ms to 120ms. At least 5 frames are acquired under each set of conditions.

[0025] Step S103: Image registration and denoising. Multiple frames of images are registered and enhanced with denoising. First, inter-frame registration is performed to correct spatial offsets caused by minute sample displacements or temperature changes. Then, the following steps are executed sequentially: (1) Background radiation subtraction: Under no-excitation conditions, dark background images are acquired and subtracted pixel by pixel to eliminate interference from dark current and environmental thermal radiation; (2) Abnormal isolated point removal: Based on spatial connected component analysis, single-pixel pseudo-signals generated by detector defects or cosmic rays are removed; (3) Multi-frame superposition enhancement: Multiple frames of images are aligned, superimposed, and averaged to improve the signal-to-noise ratio of weakly luminous hotspots. After the above processing, luminous regions with a signal-to-noise ratio (SNR) higher than a preset threshold are extracted to form a candidate hotspot set.

[0026] Step S104: Hotspot Priority Calculation. This step overcomes the shortcomings of existing technologies that rely on subjective judgment based on human experience, and creatively proposes a calculation model based on multi-dimensional feature fusion called the "Dynamic Defect Probability Index". The hotspot ranking module extracts the features of candidate hotspots under different stimulus conditions and substitutes them into the following formula to calculate their comprehensive priority score. :

[0027] In this physical and mathematical model: (1) Signal-to-noise ratio contribution ( ): The signal-to-noise ratio is the average across multiple frames. Since extremely bright hotspots do not necessarily indicate actual physical defects (they could be strong light emitted by normally powered-on external circuitry), a natural logarithm function is introduced. Nonlinear compression ensures that weak signals can be effectively evaluated, while suppressing the absolute dominance of extremely strong light spots on the total score.

[0028] (2) Stimulus response characteristic items ( ): Real leakage or breakdown defects are typically very sensitive to changes in current excitation. The system first calculates the absolute response slope. To eliminate mathematical and logical errors caused by differences in the dimensions of different devices, this invention maps the absolute slope to the [0, 1] interval through feature scaling (Min-Max Normalization) to obtain the normalized response slope. The larger this value, the higher the probability that it is a true failure point.

[0029] (3) Spatial convergence constraint terms ( This item is the core constraint factor for the spatial dimension. The variance of the centroid position of the same candidate hotspot across multiple frames of images characterizes its positional stability. The luminescent area is represented by [value]. In real deep-buried layers, luminescent points generated by defects are often extremely stable in location and their areas tend to converge. This is achieved through an exponential decay function. When the position experiences thermal drift, the score for this item will drop sharply to 0; if the position is highly stable, this item will receive a weight compensation close to full marks.

[0030] (4) Map relevance item ( The correlation coefficient is obtained by mapping the coordinates of candidate hotspots to the layout database. If the center of the hotspot happens to fall on a known critical structure that is prone to failure (such as the edge of a transistor gate or the junction of a TSV), a high correlation coefficient is assigned to it to leverage the verification role of expert experience and knowledge.

[0031] All are preset normalized weight coefficients, and their sum is 1. According to The priority sequence is obtained by sorting the values ​​in descending order.

[0032] Step S105: Failure Analysis Coordinate Output. Select one or more candidate hotspots with the highest priority and output the corresponding failure analysis coordinate information. The coordinate information includes the absolute coordinates of the hotspot center and the hotspot boundary range based on the back coordinate system. Coordinate transformation parameters (translation compensation, rotation compensation angle, and scaling factor) that match subsequent FIB, nanoprobe, or SEM equipment can also be output to achieve precise blind-switching guidance between equipment.

[0033] like Figure 3 As shown, during the hotspot map and layout mapping process, the hotspot map obtained from the back-side light emission acquisition window 203 is superimposed and aligned with the chip layout data. Near-infrared photons are transmitted through the thinned silicon substrate on the back-side observation surface 201, and the current excitation interface 202 is the application point for the excitation signal. In the figure, H1 is marked as a high-priority candidate hotspot, and H2 and H3 are lower-priority candidate hotspots. The layout reference point 204 is used for coordinate system alignment and calibration.

[0034] Example 1: Two-stage constant current excitation positioning of a standard back-side thinned sample

[0035] This embodiment focuses on an advanced logic chip manufactured using a 7nm FinFET process. During functional testing, this chip exhibited abnormal current leakage in a specific functional module, raising suspicion of gate oxide breakdown defects. Step one involves back-side thinning of the chip under test. Mechanical polishing was used to reduce the silicon substrate thickness from approximately 775μm to approximately 80μm, followed by chemical mechanical polishing to further reduce it to approximately 50μm. The surface roughness (Ra) after thinning was controlled to within 2nm. A back-side observation coordinate system was established using the metal pad alignment marks at the chip corners as a reference. Step two involves applying a two-stage constant current excitation sequence. The first stage excitation current I1 was set to 20mA for 5 seconds, under which 8 frames were acquired, with a single frame exposure integration time of 80ms. The second stage excitation current I2 was set to 28mA for 5 seconds, also with 8 frames acquired. The acquisition equipment used an InGaAs detector paired with a SIL solid-state immersion lens, with a response band of 950nm to 1650nm. Step 3: Perform registration and denoising on 16 frames of images. Acquire dark background images and subtract noise pixel-by-pixel; perform cross-correlation inter-frame registration with an accuracy better than 0.5 pixels; perform connected component area filtering to remove isolated bright spots; finally, average the results. Three candidate hotspots (H1, H2, H3) are extracted. Step 4: The system calculates the dynamic defect probability index using the formula. Hotspot H1 has the highest intensity, and more importantly, its response slope from I1 to I2 is extremely high. Normalization... It is close to 0.95. Simultaneously, its multi-frame centroid standard deviation is extremely low (0.3μm), its spatial convergence score is extremely high, and the hotspot center highly matches the overlapping region of the gate oxide layer in the layout. Ultimately, H1 obtained... The highest priority is given to this step. Step five outputs the hotspot center coordinates of H1 (X=1523.6μm, Y=892.4μm) and the conversion parameters for the adapted FIB device. Subsequent FIB cutting successfully revealed the gate oxide layer breakdown defect at position H1, verifying the accuracy of the positioning result. In this embodiment, the positioning error was only 1.8μm, and the closed-loop verification period was 1.9 hours.

[0036] Example 2: Pulse excitation and multi-frame superposition denoising localization of abnormal samples with many false hotspots

[0037] This embodiment focuses on a 128-layer 3D NAND flash memory chip, which exhibited durability degradation in specific memory blocks during reliability testing. Due to the dense metal layers and high aspect ratio in the structure, spurious hot spots were significantly increased. Step 1: The chip under test was thinned to approximately 30 μm using chemical mechanical polishing. The chip edge scribe line was used as a reference when establishing the back-side observation coordinate system. Step 2: A pulse excitation mode was adopted. The first group: amplitude 15 mA, pulse width 500 ns, repetition frequency 1 kHz, acquiring 15 valid images. The second group: amplitude 25 mA, pulse width 500 ns, acquiring 15 images. Pulse excitation significantly reduced the average thermal load of the sample, suppressing the generation of thermally-induced spurious hot spots. Step 3: Enhanced denoising processing was performed. A "multi-round superposition consistency screening" strategy was adopted, dividing each group of 15 images into 3 groups and superimposing them separately, retaining only the areas where all images appeared. The original 18 suspected bright spots were compressed into 4 candidate hot spots. Step 4: After… The dynamic defect probability algorithm calculates that although H1's signal-to-noise ratio is not the highest in the entire field, its stable position and high response pulse slope give it the highest priority. Step five involves outputting H1's coordinate information and adapting it to a nanoprobe device for electrical verification. The leakage path between the word line and bit line is finally confirmed. The positioning error is 2.4 μm, and the verification closed-loop period is 2.5 hours.

[0038] Example 3: Coordinate correction and multi-device adaptation positioning for samples with different metal layer depths

[0039] This embodiment focuses on an advanced processor chip using a 2.5D package, with the suspected failure location at the interface region between the redistribution layer (RDL) and through-silicon via (TSV). Step 1: A window was created in the target area on the back of the package substrate, and laser-assisted etching combined with CMP was used to thin the silicon substrate to 40μm. A coordinate system was established using dual references: a layout reference point and package boundary markers. Step 2: A combination of constant current and pulse excitation (I=22mA; pulse 30mA / 300ns; I=35mA) was used, acquiring 10 frames of images for each. Step 3: Inter-frame registration was performed, and an affine transformation model was introduced to compensate for image distortion caused by package warping. After denoising, two candidate hotspots were identified. Step 4: H1 was assigned the highest priority using a formula, and the layout relevance parameter indicated that it was located in the transition region between the TSV and RDL. Step 5: Three-dimensional coordinates (X, Y, Z) were output, with the Z-axis coordinate representing the estimated depth location. Subsequent FIB layer-by-layer cutting successfully revealed a void defect at the bottom of the TSV at location H1. The positioning error was 2.8 μm, and the verification cycle was 3.1 hours.

[0040] Comparative Example: Using the same sample from Example 1 as the object, a conventional single-shot light emission observation scheme was employed (single constant current 20mA, single-frame image, without system denoising and intelligent sorting). The results showed as many as 12 candidate hotspots, requiring blind FIB verification one by one, with the true location only found at the 5th position. The positioning error was approximately 9.2μm, and the verification closed-loop cycle was as long as 5.8 hours. The data comparison fully demonstrates the significant superiority of the multi-excitation linkage and algorithm scheduling of this invention.

[0041] like Figure 4 As shown, the preferred window for key parameters of this invention is: constant current 18mA to 28mA; pulse width 200ns to 800ns; exposure integral 60ms to 120ms; SNR threshold ≥ 4.5. The system achieves optimal positioning accuracy when the preferred window is met. Figure 6 As shown, the core technical concept is equivalently extended according to the analysis objective: Example 1 is applicable to standard logic chips; Example 2 is applicable to deeply buried memory; Example 3 is applicable to multi-layer structure packaged chips.

[0042] It should be understood that the above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for locating failure hotspots in advanced process chips, characterized in that: Includes the following steps: S1, prepare for back-side observation of the chip under test, and establish a chip back-side coordinate system based on the physical characteristics of the chip under test; S2, apply at least two sets of current excitations under different conditions to the chip under test according to a preset excitation sequence, and simultaneously acquire the corresponding back light emission image under each set of current excitation conditions; S3, register and jointly denoise the multiple frames of back light emission images acquired under each group of current excitation conditions, and extract a set of candidate hotspots whose luminescence features meet a preset threshold. S4. Based on the dynamic luminescence response characteristics and spatial distribution characteristics of the candidate hotspots under different current excitation conditions, calculate and determine the priority ranking of each candidate hotspot. S5. Based on the priority sorting, output the failure analysis coordinate information of at least one high-priority candidate hot spot.

2. The method according to claim 1, characterized in that: The preset excitation sequence includes at least two constant current excitations, pulse excitations, or a combination of constant current and pulse excitations with different amplitudes. The constant current excitation current amplitude ranges from 5mA to 40mA; the pulse width of the pulse excitation ranges from 50ns to 2μs.

3. The method according to claim 1, characterized in that: The joint denoising process described in step S3 includes: Dark field background radiation subtraction is performed on each frame of back-side light emission image to eliminate dark current noise and environmental thermal radiation interference; Perform outlier removal based on spatially connected components to remove single-pixel spurious signals; Alignment superposition average enhancement is performed on no less than 5 frames of images under the same set of current excitation conditions to improve the signal-to-noise ratio of weak luminous hot spots, wherein the exposure integration time of a single frame image is 20ms to 200ms.

4. The method according to claim 1, characterized in that: The dynamic light emission response characteristics mentioned in step S4 include: Hotspot intensity: Characterizes the average light emission intensity of candidate hotspots under various excitation conditions; Normalized excitation response slope: Characterizes the gradient of the light emission intensity of the candidate hotspot as a function of the applied current excitation, and is mapped to a preset numerical range after feature scaling. The spatial distribution characteristics include: Positional stability: characterizes the degree of dispersion of the centroid coordinates of the same candidate hotspot across multiple frames of images; Spatial convergence: characterizes the convergence trend of the luminescent region area of ​​candidate hotspots shrinking as the excitation current increases; Layout relevance: Characterizes the spatial correspondence between candidate hotspot locations and key structures in the chip layout.

5. The method according to claim 4, characterized in that: The priority ranking in step S4 is based on the dynamic defect probability index. The calculation formula for the dynamic defect probability index is as follows: in: A comprehensive priority score is given to the candidate hotspots; The average signal-to-noise ratio of the candidate hotspot across multiple frames after joint denoising processing; The slope of the normalized excitation response is defined, with a value range of [0, 1]. The spatial variance of the centroid coordinates of the same candidate hotspot across multiple frames of images characterizes its positional stability. The equivalent pixel area of ​​the candidate hotspot luminescent region; This is the map relevance coefficient, with a value range of [0, 1]. All are preset normalized weight coefficients, and satisfy the following conditions: .

6. The method according to claim 1, characterized in that: The failure analysis coordinate information mentioned in step S5 includes: The absolute coordinates of the hotspot center and the range of the hotspot boundary, based on the aforementioned back coordinate system.

7. The method according to claim 6, characterized in that: Before outputting the failure analysis coordinate information, the method further includes: Extract chip layout markers or package structure markers, and use the markers to calibrate the back coordinate system. The calibration includes at least one of translation compensation, rotation compensation, and scaling compensation.

8. A failure hotspot location system for advanced process chips, characterized in that: include: The excitation control module is used to apply at least two sets of current excitations with different conditions to the chip under test according to a preset excitation sequence. The back light emission acquisition module is connected to the excitation control module via a synchronous trigger bus. When it receives the excitation synchronization signal, it performs time-synchronous acquisition of the back light emission image of the chip under test. An image processing module is communicatively coupled to the back-side light emission acquisition module to receive multi-frame image data streams. The image processing module is configured to perform inter-frame registration and joint denoising processing on the image data streams and output a set of candidate hotspots containing feature coordinates downstream. The hotspot sorting module takes the candidate hotspot set and the current state data from the excitation control module as input, and calls an external layout database. It is configured to execute the calculation formula of the dynamic defect probability index as described in claim 5, thereby generating a priority sorting sequence for each candidate hotspot. The coordinate output module, logically connected to the hotspot sorting module, is used to receive the highest priority candidate hotspot information and, in conjunction with a preset coordinate reference, convert it into failure analysis coordinate information adapted to subsequent analysis equipment, thereby forming a closed-loop data link of "excitation-acquisition-evaluation-mapping" in the entire positioning system.

9. The system according to claim 8, characterized in that: The back-side light emission acquisition module includes a near-infrared detector and a solid-state immersion lens coupled to the front end of the detector's optical path. The response band of the near-infrared detector covers 900nm to 1700nm. The excitation control module is configured to output at least one of a constant current mode and a pulse mode, wherein the output range of the constant current mode is 5mA to 40mA, and the pulse width of the pulse mode is adjustable from 50ns to 2μs.

10. The system according to claim 8, characterized in that: The coordinate output module is configured to output the failure analysis coordinate information in a target coordinate format suitable for focused ion beam equipment, nanoprobe equipment, or scanning electron microscope, and simultaneously output absolute coordinates, relative coordinates, and conversion parameters adapted to subsequent equipment.

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