A driving isolated power supply common mode interference suppression circuit
Patent Information
- Application Number
- CN202610842269.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-11
- Publication Date
- 2026-08-18
AI Technical Summary
[0004]本发明提供了一种驱动隔离电源共模干扰抑制电路，用于解决现有的驱动隔离电源共模干扰防护方法难以消除传导电磁干扰对驱动隔离电源采样和控制信号的影响，导致驱动隔离电源的传导电磁干扰免疫能力较低的技术问题
本发明提供的驱动隔离电源共模干扰抑制电路，低侧驱动板卡的一端与下管的栅极连接，闭环控制电路的输入端与低压控制板卡的低侧栅极控制信号端口或高侧栅极控制信号端口连接，低侧驱动板卡的另一端和低压控制板卡的低侧栅极控制信号端口，高侧驱动板卡的一侧与上管的栅极连接，高侧驱动板卡的另一端与低压控制板卡的高侧栅极控制信号端口连接，上管的漏极与下管的源极连接，通过将上管或下管的栅极控制信号接入驱动隔离电源，根据上管或下管的栅极控制信号生成驱动隔离电源的采样时钟，实现功率器件开关与驱动隔离电源工作的同步，通过合理设置栅极控制信号与电源采样时钟的相位差，可以使采样时刻避开电磁干扰电压的跳变时刻，避免噪声电压对采样信号的影响，从而保证驱动隔离电源输出电压的稳定性，解决了现有的驱动隔离电源共模干扰防护方法难以消除传导电磁干扰对驱动隔离电源采样和控制信号的影响，导致驱动隔离电源的传导电磁干扰免疫能力较低的技术问题。
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Figure CN122600699A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of isolated power supply technology, and in particular to a common-mode interference suppression circuit for driving isolated power supplies. Background Technology
[0002] Power semiconductor devices are core components for achieving efficient power conversion and are evolving towards higher voltage, higher current, and faster switching speeds. However, the high-speed switching of power devices generates changing voltages and currents, producing strong high-frequency electromagnetic interference (EMI) to surrounding equipment. Gate driver boards, acting as a bridge connecting the control loop and power circuits, are tightly connected to power devices to ensure reliable switching and are thus subject to strong EMI. Taking a typical half-bridge structure as an example, the switching action of the power device causes a change in the midpoint potential of the bridge arm, leading to a potential shift in the reference ground of the secondary circuit of the high-side driver board. This, in turn, generates common-mode current through the parasitic capacitance of the isolation units (signal isolators and drive isolation power supplies) in the driver circuit. Since the parasitic capacitance of the drive isolation power supply is much larger than that of the signal isolator, it becomes the main channel for EMI transmission. When EMI passes through the drive isolation power supply, it couples into the control loop inside the drive isolation power supply through its sampling feedback circuit, interfering with the drive signals of the switching transistors and causing abnormal output voltage. This will lead to problems such as increased switching losses and stress in power devices, overvoltage breakdown of the gate oxide layer, malfunction or failure of the drive circuit, and undervoltage lockout of the drive chip, seriously threatening the safety of power devices and power electronic converters.
[0003] Existing methods for protecting drive-isolated power supplies from common-mode interference mainly include installing common-mode EMI filters and reducing the parasitic capacitance of the isolation transformer in the drive-isolated power supply. However, common-mode EMI filters are typically large in size and weight, limiting the improvement of the power density of the drive-isolated power supply. Reducing the parasitic capacitance of the isolation transformer requires increasing the size of the isolation transformer in the drive-isolated power supply or using more advanced and complex processes, leading to problems such as reduced power supply efficiency, increased control complexity, and increased cost. Furthermore, methods such as using common-mode filters or reducing the parasitic capacitance of the isolation transformer in the drive-isolated power supply do not change the transmission impedance of common-mode interference through the sampling and control loop in the drive-isolated power supply or cut off the transmission path, thus failing to solve the problem of output voltage fluctuations and instability caused by common-mode interference through the sampling and control loop in the drive-isolated power supply. Therefore, how to eliminate the influence of conducted electromagnetic interference on the sampling and control signals of the drive-isolated power supply and improve the conducted electromagnetic interference immunity of the drive-isolated power supply is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0004] This invention provides a common-mode interference suppression circuit for driving isolated power supplies, which solves the technical problem that existing common-mode interference protection methods for driving isolated power supplies are unable to eliminate the influence of conducted electromagnetic interference on the sampling and control signals of the driving isolated power supply, resulting in low immunity to conducted electromagnetic interference of the driving isolated power supply.
[0005] In view of this, the present invention provides a common-mode interference suppression circuit for driving isolated power supplies, including a low-voltage control board, a low-side drive board, a high-side drive board, an upper transistor, and a lower transistor; The low-voltage control board is connected to both the low-side drive board and the high-side drive board. The high-side driver board includes a signal isolator, an amplifier unit, a power conversion unit, and a closed-loop control circuit. One end of the low-side drive board is connected to the gate of the lower transistor. The input of the closed-loop control circuit is connected to the low-side gate control signal port or the high-side gate control signal port of the low-voltage control board. The other end of the low-side drive board is connected to the low-side gate control signal port of the low-voltage control board. One side of the high-side drive board is connected to the gate of the upper transistor. The other end of the high-side drive board is connected to the high-side gate control signal port of the low-voltage control board. The drain of the upper transistor is connected to the source of the lower transistor. One end of the signal isolator is connected to the high-side gate control signal port of the low-voltage control board, and the other end of the signal isolator is connected to the input terminal of the amplifier unit. The output terminal of the amplifier unit is connected to the gate of the upper transistor, and the midpoint of the bridge arm of the upper and lower transistors is grounded with the amplifier unit. The power conversion unit is used to amplify and rectify the modulated signal output from the closed-loop control circuit before outputting it. The closed-loop control circuit is used to generate a sampling clock signal based on the low-side gate control signal or the high-side gate control signal, sample the output signal of the power conversion unit based on the sampling clock signal and perform pulse modulation to generate a modulation signal for controlling the power conversion unit.
[0006] Optionally, the closed-loop control circuit includes an optocoupler feedback unit, a sample-and-hold unit, an error amplifier, and a PWM modulator; The input terminal of the optocoupler feedback unit is connected to the output terminal of the power conversion unit, the output terminal of the optocoupler feedback unit is connected to the input terminal of the sample-and-hold unit, the output terminal of the sample-and-hold unit is connected to the input terminal of the error amplifier, and the output terminal of the error amplifier is connected to the input terminal of the PWM modulator.
[0007] Optionally, the power conversion unit includes an RCD clamping unit, a flyback transformer, a switching transistor, and an output rectifier and filter unit; The input terminal of the RCD clamping unit is connected to the DC input power supply. The output terminal of the RCD clamping unit is connected to the primary side of the flyback transformer. The primary side of the flyback transformer is connected to the source of the switching transistor. The secondary side of the flyback transformer is connected to the input terminal of the output rectifier and filter unit. The gate of the switching transistor is connected to the closed-loop control circuit. The drain of the switching transistor is grounded.
[0008] Optionally, the sample-and-hold unit includes a synchronous clock control circuit and a sample-and-hold circuit; The synchronous clock control circuit is connected to the sample-and-hold circuit. The analog signal input terminal of the sample-and-hold circuit is connected to the output terminal of the optocoupler feedback unit. The logic control signal input terminal of the sample-and-hold circuit is connected to the output terminal of the synchronous clock control circuit. The input terminal of the synchronous clock control circuit is connected to the low-side gate control signal port of the low-voltage control board.
[0009] Optionally, the synchronous clock control circuit includes a DC voltage source, a timer, a Schmitt buffer, a first Schmitt inverter, a second Schmitt inverter, a first diode, a second diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; One end of the first capacitor is connected to the low-side gate control signal port of the low-voltage control board. The other end of the first capacitor is connected to one end of the first resistor, the cathode of the first diode, and the input of the first Schmitt inverter. The other end of the first resistor and the anode of the first diode share a common ground. The output of the first Schmitt inverter is connected to the trigger pin of the timer. One end of the second resistor is connected to the DC voltage source and the reset pin of the timer. The other end of the second resistor is connected to the discharge pin and the threshold pin of the timer, and one end of the second capacitor. The other end of the second capacitor is grounded. The input of the second Schmitt inverter is connected to the output pin of the timer. The output of the second Schmitt inverter is connected to one end of the third capacitor. The other end of the third capacitor is connected to the input of the Schmitt buffer, one end of the third resistor, and the cathode of the second diode. The other end of the third resistor and the anode of the second diode share a common ground. The output of the Schmitt buffer is connected to the logic control signal input of the sample-and-hold circuit. One end of the fourth capacitor is connected to the control voltage pin of the timer. The other end of the fourth capacitor shares a common ground with the ground pin of the timer.
[0010] Optionally, the timer is an NE555 timer.
[0011] Optionally, the low-level duration of the output voltage of the first Schmitt inverter is:
[0012] in, The duration of the low-level output voltage of the first Schmitt inverter. This is the resistance value of the first resistor. This is the capacitance value of the first capacitor. The low-side gate control signal port outputs a high level. This is the negative threshold voltage of the first Schmitt inverter.
[0013] Optionally, the capacitance of the fourth capacitor is 0.01uF.
[0014] Optionally, the pulse width of the output signal of the Schmitt trigger buffer is:
[0015] in, The pulse width of the output signal of the Schmitt buffer. This is the resistance value of the third resistor. This is the capacitance value of the third capacitor. The low-side gate control signal port outputs a high level. This is the negative threshold voltage of the first Schmitt inverter.
[0016] Optionally, the pulse width of the signal output by the timer's output pin is:
[0017] in, The pulse width of the signal output from the timer's output pin. This is the resistance value of the second resistor. This is the capacitance value of the second capacitor.
[0018] As can be seen from the above technical solutions, the common-mode interference suppression circuit for the drive isolation power supply provided by the present invention has the following advantages: The common-mode interference suppression circuit for the drive isolation power supply provided by this invention has one end of the low-side drive board connected to the gate of the lower transistor, and the input terminal of the closed-loop control circuit connected to the low-side gate control signal port or the high-side gate control signal port of the low-voltage control board. The other end of the low-side drive board is connected to the low-side gate control signal port of the low-voltage control board. One side of the high-side drive board is connected to the gate of the upper transistor, and the other end of the high-side drive board is connected to the high-side gate control signal port of the low-voltage control board. The drain of the upper transistor is connected to the source of the lower transistor. By connecting the gate control signal of the upper or lower transistor to the drive isolation power supply, according to the above... The gate control signal of the lower transistor or the upper transistor generates the sampling clock for driving the isolated power supply, realizing the synchronization of the power device switching and the operation of the driving isolated power supply. By reasonably setting the phase difference between the gate control signal and the power supply sampling clock, the sampling time can avoid the transition time of electromagnetic interference voltage, avoid the influence of noise voltage on the sampling signal, and thus ensure the stability of the output voltage of the driving isolated power supply. This solves the technical problem that existing common-mode interference protection methods for driving isolated power supplies are difficult to eliminate the influence of conducted electromagnetic interference on the sampling and control signals of the driving isolated power supply, resulting in low conducted electromagnetic interference immunity of the driving isolated power supply. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a typical half-bridge circuit drive structure diagram; Figure 2 A typical structural diagram for driving an isolated power supply; Figure 3 Waveform diagram of nodes subjected to electromagnetic interference in the sampling control loop of the driving isolated power supply; Figure 4 This is a schematic diagram of the common-mode interference suppression circuit for the drive isolation power supply provided in an embodiment of the present invention; Figure 5 This is a waveform diagram of the drive isolation power supply node of the common-mode interference suppression circuit provided in the embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of the drive isolation power supply provided in an embodiment of the present invention; Figure 7 This is a circuit diagram of the sample-and-hold unit provided in an embodiment of the present invention; Figure 8 This is a node waveform diagram of the synchronous clock control circuit provided in an embodiment of the present invention. Detailed Implementation
[0021] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0022] For easier understanding, please refer to Figure 4 The present invention provides an embodiment of a common-mode interference suppression circuit for driving isolated power supplies, including a low-voltage control board, a low-side drive board, a high-side drive board, an upper transistor, and a lower transistor; The low-voltage control board is connected to both the low-side drive board and the high-side drive board. The high-side driver board includes a signal isolator, an amplifier unit, a power conversion unit, and a closed-loop control circuit. One end of the low-side drive board is connected to the gate of the lower transistor. The input of the closed-loop control circuit is connected to the low-side gate control signal port or the high-side gate control signal port of the low-voltage control board. The other end of the low-side drive board is connected to the low-side gate control signal port of the low-voltage control board. One side of the high-side drive board is connected to the gate of the upper transistor. The other end of the high-side drive board is connected to the high-side gate control signal port of the low-voltage control board. The drain of the upper transistor is connected to the source of the lower transistor. One end of the signal isolator is connected to the high-side gate control signal port of the low-voltage control board, and the other end of the signal isolator is connected to the input terminal of the amplifier unit. The output terminal of the amplifier unit is connected to the gate of the upper transistor, and the midpoint of the bridge arm of the upper and lower transistors is grounded with the amplifier unit. The power conversion unit is used to amplify and rectify the modulated signal output from the closed-loop control circuit before outputting it. The closed-loop control circuit is used to generate a sampling clock signal based on the low-side gate control signal or the high-side gate control signal, sample the output signal of the power conversion unit based on the sampling clock signal and perform pulse modulation to generate a modulation signal for controlling the power conversion unit.
[0023] It should be noted that a typical half-bridge circuit drive structure is as follows: Figure 1 As shown, it includes a low-voltage control board, a high-side drive board, a low-side drive board, and an upper tube. (Power devices) and lower transistor (Power devices), the high-side driver board includes a driver isolation power supply, a signal isolator, and an amplification unit buffer. When the half-bridge circuit driver structure is working normally, the upper transistor... and lower pipe Alternating conduction causes the voltage at the midpoint SW of the bridge arm to be... bus voltage Rapid transition between ground and earth. A typical structure for driving an isolated power supply is as follows: Figure 2 As shown, the node waveform of the drive isolation power supply sampling control loop subjected to electromagnetic interference is as follows: Figure 3 As shown. Midpoint voltage of bridge arm. Transient (dv / dt) voltages can apply repetitive electromagnetic interference voltages to the sampling feedback unit driving the isolated power supply. This, in turn, generates common-mode current through the isolation capacitor. The current flows to the input port of the sampling controller. At each sampling moment, the common-mode current... Inflow holding capacitor At the sampling voltage Noise voltage generated on Sampling voltage affected by noise The error signal is obtained after passing through the error amplifier. This alters the modulation timing of the triangular carrier signal and the error signal, thereby affecting the PWM signal of the switching transistor in the next cycle. The pulse width, after being amplified by the power conversion unit, causes abnormal fluctuations in the output voltage of the drive isolation power supply. To eliminate the influence of conducted electromagnetic interference on the output voltage of the drive isolation power supply, this invention provides a common-mode interference suppression circuit for the drive isolation power supply, such as... Figure 4 As shown in the figure, the waveform of the drive isolation power supply node of the circuit shown is as follows. Figure 5 As shown. For a half-bridge structure, in order to eliminate the electromagnetic interference of the bridge arm midpoint voltage transient on the drive isolation power supply, the input terminal of the closed-loop control circuit is connected to the low-side gate control signal port or the high-side gate control signal port of the low-voltage control board, thereby controlling the power device being driven (i.e., the upper transistor). Or lower pipe The gate control signal of the power conversion unit is connected to the sampling feedback unit of the driving isolated power supply, i.e., the closed-loop control circuit. The power conversion unit of the driving isolated power supply amplifies and rectifies the modulation signal output by the closed-loop control circuit before outputting it. The closed-loop control circuit generates a sampling clock signal based on the low-side gate control signal or the high-side gate control signal, samples the output signal of the power conversion unit according to the sampling clock signal to obtain a sampling signal, and performs error amplification on the sampling signal before pulse modulation to generate a modulation signal used to control the power conversion unit.
[0024] In one embodiment, such as Figure 6 As shown, the power conversion unit includes an RCD clamping unit, a flyback transformer, a switching transistor, and an output rectifier and filter unit. The input terminal of the RCD clamping unit is connected to the DC input power supply. The output of the RCD clamping unit is connected to the primary side of the flyback transformer, which in turn is connected to the source of the switching transistor. The secondary side of the flyback transformer is connected to the input of the output rectifier and filter unit. The gate of the switching transistor is connected to the closed-loop control circuit, and its drain is grounded. The principle is the same as that of a flyback converter. The closed-loop control circuit includes an optocoupler feedback unit, a sample-and-hold unit, an error amplifier, and a PWM modulator. The input of the optocoupler feedback unit is connected to the output of the power conversion unit. The output of the optocoupler feedback unit is connected to the input of the sample-and-hold unit. The output of the sample-and-hold unit is connected to the input of the error amplifier, and the output of the error amplifier is connected to the input of the PWM modulator. The output voltage of the output rectifier and filter unit... The output of the optocoupler feedback unit is fed back to the primary side. The input terminal of the sample-and-hold unit is connected, and the sampled signal is obtained after passing through the sampling unit. Sampling signal The error signal is obtained after passing through the error amplifier. Error signal The PWM signal is obtained after passing through the PWM modulator to control the switching of the switching transistor. The sample-and-hold unit includes a synchronous clock control circuit and a sample-and-hold circuit. The synchronous clock control circuit is connected to the sample-and-hold circuit. The analog signal input of the sample-and-hold circuit is connected to the output of the optocoupler feedback unit. The logic control signal input of the sample-and-hold circuit is connected to the output of the synchronous clock control circuit. The input of the synchronous clock control circuit is connected to the low-side gate control signal port of the low-voltage control board. The input of the synchronous clock control circuit is connected to the low-side power device (lower MOSFET) of the half-bridge structure. The gate control signal PWML or the high-side power device (upper transistor) of the half-bridge structure. The gate control signal PWMH of the half-bridge structure is connected to the input terminal of the synchronous clock control circuit in this invention. Taking the gate control signal PWML as an example, the output of the synchronous clock control circuit is connected to the logic control signal input SEL of the sample-and-hold circuit. The analog signal input S of the sample-and-hold circuit is connected to the output of the optocoupler feedback unit, and the output D of the sample-and-hold circuit is connected to the input of the error amplifier.
[0025] like Figure 7 As shown, the synchronous clock control circuit provided in this invention includes a DC voltage source. NE555 timer, Schmitt buffer ST, first Schmitt inverter ST.inv1, second Schmitt inverter ST.inv2, first diode Second diode First resistor Second resistor Third resistor Fourth resistor First capacitor Second capacitor Third capacitor and the fourth capacitor First capacitor One end is connected to the low-side gate control signal port PWML of the low-voltage control board, and the first capacitor The other end is connected to the first resistor. One end, the first diode The cathode is connected to the input terminal of the first Schmitt inverter ST.inv1, and the first resistor is connected to the input terminal of the first Schmitt inverter ST.inv1. The other end and the first diode The anodes are grounded, the output of the first Schmitt inverter ST.inv1 is connected to the TRIG trigger pin of the timer NE555, and the second resistor... One end is connected to a DC voltage source The second resistor is connected to the RESET pin of the NE555 timer. The other end is connected to the discharge pin DISGH of the timer NE555, the threshold pin THRS, and the second capacitor, respectively. One end is connected to the second capacitor. The other end is grounded. The input of the second Schmitt inverter ST.inv2 is connected to the output pin of the timer NE555. The output of the second Schmitt inverter ST.inv2 is connected to the third capacitor. One end is connected to the third capacitor. The other end is connected to the input terminal of the Schmitt buffer ST and the third resistor, respectively. One end and the second diode Cathode connection, third resistor The other end is connected to the second diode. The anodes of the circuit are grounded, and the output of the Schmitt trigger buffer ST is connected to the logic control signal input SEL of the sample-and-hold circuit. Let the output voltage of the Schmitt trigger buffer ST be... Fourth capacitor One end is connected to the control voltage pin VCONT of the NE555 timer, and the fourth capacitor The other end is grounded with the GND pin of the NE555 timer.
[0026] The node waveforms of the synchronous clock control circuit are as follows: Figure 8 As shown, during normal operation, the low-side power device (i.e., the lower transistor) The gate control signal PWML is high. A pulse signal with a low level of 0. First resistor. First capacitor and the first diode This forms an RC differentiating circuit, whose function is to convert the input gate control signal PWML into a transient spike signal, highlighting the edge changes of the input signal. When the gate control signal PWML is high, the first resistor... Voltage at both ends for:
[0027] When the gate control signal PWML is low, the first resistor Voltage at both ends for:
[0028] in, The first diode The forward voltage drop. When the first resistor Voltage at both ends Reduced to the negative threshold of the first Schmitt inverter ST.inv1 At that time, the output voltage of the first Schmitt inverter ST.inv1 The voltage transitions from low to high, and remains high until the next rising edge of the gate control signal PWML. The output voltage of the first Schmitt inverter ST.inv1... low level duration for:
[0029] Timer and second resistor Second capacitor DC voltage source and the fourth capacitor This forms a monostable multivibrator. When the timer's trigger pin TRIG receives a low-level pulse ( When ), the output pin OUT generates a high level of fixed width. Pulse width By the second resistor Second capacitor Size determines:
[0030] Fourth capacitor The value is 0.01uF, used to bypass high-frequency noise and ensure the stability of the threshold voltage of the internal comparator of the NE555 timer. The output voltage of the NE555 timer. After being inverted by the second Schmitt inverter ST.inv2, the current passes through the third resistor. Third capacitor Second diode The constructed RC differentiating circuit produces an edge-synchronized transient spike signal, which is then subjected to hysteresis comparison via a Schmitt trigger buffer ST to generate an edge-synchronized sampling pulse signal. Sampling pulse signal pulse width for:
[0031] After processing by the synchronous clock control circuit, it can be applied to the low-side power device (i.e., the lower transistor). After the rising edge of the gate control signal PWML, the delay time is... The generated pulse width is Sampling pulse signal This achieves synchronization between the gate control signal of the power device and the sampling clock of the drive isolation power supply. Among other things, If satisfied ,in, It is the sum of the propagation delay of the drive circuit and the turn-off delay of the power device. This refers to the time from when the voltage of the electromagnetic interference source begins to rise until the electromagnetic noise disappears. Let V be the time it takes for the voltage of the electromagnetic interference source to drop until the electromagnetic noise disappears. Then, let V be the electromagnetic interference noise voltage. This prevents the sampling control loop of the drive isolation power supply from entering, thus ensuring the stability of the drive isolation power supply's output voltage. The function of the synchronous clock control circuit is to delay the signal after the rising or falling edge of the power device's gate control signal. Generate sampling pulse Subsequently, sampling pulses Input sample-and-hold circuit for output voltage Perform sampling.
[0032] The common-mode interference suppression circuit for the drive isolation power supply provided by this invention has one end of the low-side drive board connected to the gate of the lower transistor, and the input terminal of the closed-loop control circuit connected to either the low-side gate control signal port or the high-side gate control signal port of the low-voltage control board. The other end of the low-side drive board is connected to the low-side gate control signal port of the low-voltage control board. One side of the high-side drive board is connected to the gate of the upper transistor, and the other end of the high-side drive board is connected to the high-side gate control signal port of the low-voltage control board. The drain of the upper transistor is connected to the source of the lower transistor. By connecting the gate control signal of the upper or lower transistor to the drive isolation power supply, the sampling signal of the drive isolation power supply is generated based on the gate control signal of the upper or lower transistor. The sampling clock synchronizes the switching of power devices with the operation of the drive isolation power supply. By reasonably setting the phase difference between the gate control signal and the power supply sampling clock, the sampling time can avoid the transition time of electromagnetic interference voltage, thus avoiding the influence of noise voltage on the sampling signal. It can effectively prevent the propagation of electromagnetic interference noise caused by the voltage transition at the midpoint of the bridge arm in the sampling control loop of the drive isolation power supply, thereby ensuring the stability of the output voltage of the drive isolation power supply. This solves the technical problem that existing common-mode interference protection methods for drive isolation power supplies are difficult to eliminate the influence of conducted electromagnetic interference on the sampling and control signals of the drive isolation power supply, resulting in low conducted electromagnetic interference immunity of the drive isolation power supply.
[0033] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0034] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A drive isolated power supply common mode interference rejection circuit, characterized by, This includes low-voltage control boards, low-side drive boards, high-side drive boards, upper tubes, and lower tubes; The low-voltage control board is connected to both the low-side drive board and the high-side drive board. The high-side driver board includes a signal isolator, an amplifier unit, a power conversion unit, and a closed-loop control circuit. One end of the low-side drive board is connected to the gate of the lower transistor. The input of the closed-loop control circuit is connected to the low-side gate control signal port or the high-side gate control signal port of the low-voltage control board. The other end of the low-side drive board is connected to the low-side gate control signal port of the low-voltage control board. One side of the high-side drive board is connected to the gate of the upper transistor. The other end of the high-side drive board is connected to the high-side gate control signal port of the low-voltage control board. The drain of the upper transistor is connected to the source of the lower transistor. One end of the signal isolator is connected to the high-side gate control signal port of the low-voltage control board, and the other end of the signal isolator is connected to the input terminal of the amplifier unit. The output terminal of the amplifier unit is connected to the gate of the upper transistor, and the midpoint of the bridge arm of the upper and lower transistors is grounded with the amplifier unit. The power conversion unit is used to amplify and rectify the modulated signal output from the closed-loop control circuit before outputting it. The closed-loop control circuit is used to generate a sampling clock signal based on the low-side gate control signal or the high-side gate control signal, sample the output signal of the power conversion unit based on the sampling clock signal and perform pulse modulation to generate a modulation signal for controlling the power conversion unit.
2. The drive-isolation power supply common-mode disturbance rejection circuit of claim 1, wherein, The closed-loop control circuit includes an optocoupler feedback unit, a sample-and-hold unit, an error amplifier, and a PWM modulator; The input terminal of the optocoupler feedback unit is connected to the output terminal of the power conversion unit, the output terminal of the optocoupler feedback unit is connected to the input terminal of the sample-and-hold unit, the output terminal of the sample-and-hold unit is connected to the input terminal of the error amplifier, and the output terminal of the error amplifier is connected to the input terminal of the PWM modulator.
3. The drive-isolation power supply common-mode disturbance rejection circuit of claim 1 or 2, wherein, The power conversion unit includes an RCD clamping unit, a flyback transformer, a switching transistor, and an output rectifier and filter unit; The input terminal of the RCD clamping unit is connected to the DC input power supply. The output terminal of the RCD clamping unit is connected to the primary side of the flyback transformer. The primary side of the flyback transformer is connected to the source of the switching transistor. The secondary side of the flyback transformer is connected to the input terminal of the output rectifier and filter unit. The gate of the switching transistor is connected to the closed-loop control circuit. The drain of the switching transistor is grounded.
4. The drive-isolation power supply common-mode disturbance rejection circuit of claim 2, wherein, The sample-and-hold unit includes a synchronous clock control circuit and a sample-and-hold circuit; The synchronous clock control circuit is connected to the sample-and-hold circuit. The analog signal input terminal of the sample-and-hold circuit is connected to the output terminal of the optocoupler feedback unit. The logic control signal input terminal of the sample-and-hold circuit is connected to the output terminal of the synchronous clock control circuit. The input terminal of the synchronous clock control circuit is connected to the low-side gate control signal port of the low-voltage control board.
5. The common-mode interference suppression circuit for drive isolation power supply according to claim 4, characterized in that, The synchronous clock control circuit includes a DC voltage source, a timer, a Schmitt buffer, a first Schmitt inverter, a second Schmitt inverter, a first diode, a second diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; One end of the first capacitor is connected to the low-side gate control signal port of the low-voltage control board. The other end of the first capacitor is connected to one end of the first resistor, the cathode of the first diode, and the input of the first Schmitt inverter. The other end of the first resistor and the anode of the first diode share a common ground. The output of the first Schmitt inverter is connected to the trigger pin of the timer. One end of the second resistor is connected to the DC voltage source and the reset pin of the timer. The other end of the second resistor is connected to the discharge pin and the threshold pin of the timer, and one end of the second capacitor. The other end of the second capacitor is grounded. The input of the second Schmitt inverter is connected to the output pin of the timer. The output of the second Schmitt inverter is connected to one end of the third capacitor. The other end of the third capacitor is connected to the input of the Schmitt buffer, one end of the third resistor, and the cathode of the second diode. The other end of the third resistor and the anode of the second diode share a common ground. The output of the Schmitt buffer is connected to the logic control signal input of the sample-and-hold circuit. One end of the fourth capacitor is connected to the control voltage pin of the timer. The other end of the fourth capacitor shares a common ground with the ground pin of the timer.
6. The common-mode interference suppression circuit for drive isolation power supply according to claim 5, characterized in that, The timer is an NE555 timer.
7. The common-mode interference suppression circuit for drive isolation power supply according to claim 5, characterized in that, The duration of the low-level output voltage of the first Schmitt inverter is: in, The duration of the low-level output voltage of the first Schmitt inverter. This is the resistance value of the first resistor. This is the capacitance value of the first capacitor. The low-side gate control signal port outputs a high level. This is the negative threshold voltage of the first Schmitt inverter.
8. The common-mode interference suppression circuit for drive isolation power supply according to claim 5, characterized in that, The capacitance of the fourth capacitor is 0.01uF.
9. The common-mode interference suppression circuit for drive isolation power supply according to claim 5, characterized in that, The pulse width of the output signal of the Schmitt trigger buffer is: in, The pulse width of the output signal of the Schmitt buffer. This is the resistance value of the third resistor. This is the capacitance value of the third capacitor. The low-side gate control signal port outputs a high level. This is the negative threshold voltage of the first Schmitt inverter.
10. The common-mode interference suppression circuit for the drive isolation power supply according to claim 5, characterized in that, The pulse width of the signal output from the timer's output pin is: in, The pulse width of the signal output from the timer's output pin. This is the resistance value of the second resistor. This is the capacitance value of the second capacitor.