Method for improving thickness uniformity of a lamination impedance layer and power board

Abstract

The present application relates to a kind of methods for improving the uniformity of pressing impedance layer medium thickness, comprising the following steps: S1, provide a multilayer board pressing structure, the multilayer board pressing structure at least includes first conductive layer, second conductive layer and third conductive layer, the thickness of the second conductive layer is greater than the thickness of the first conductive layer, the second conductive layer includes impedance control area and pure flow area;S2, in the pure flow area of the second conductive layer, copper is dug, and the residual copper rate of the pure flow area is reduced to match the residual copper rate of the impedance control area;S3, between the first conductive layer and the second conductive layer, and / or between the first conductive layer and the third conductive layer, blind hole is opened and filled with conductive paste.The present application makes the copper thickness of L2 layer in pure flow area and impedance control area consistent, solves the problem of medium thickness uneven caused by copper thickness difference after pressing, so that impedance control precision can meet the requirement of ±5%.

Description

Technical Field

[0001] This invention relates to the field of circuit boards, and more particularly to a method for improving the uniformity of dielectric thickness of a laminated impedance layer and a computing power supply board. Background Technology

[0002] Traditional computing power supply boards typically employ a dual-module design: one module is the pure current-carrying area (large copper surface), and the other module is used for impedance control circuitry. Impedance control is primarily distributed in the outer layer (L1) and the next outermost layer (L2), with a control specification of ±10%. With the rapid iteration of AI computing power, the requirements for current-carrying capacity of computing power supply boards have significantly increased, while impedance control accuracy also needs to be improved to ±5%. In this context, both L1 and L2 layers must meet stringent impedance control requirements. However, the L2 layer, as a hybrid layer, contains both a large copper surface area (pure current-carrying) and a fine-grained circuitry area (impedance control). If a thicker copper layer is used to improve current-carrying capacity, the difference in residual copper ratio between the large copper surface area and the circuitry area during lamination will be too large, resulting in severe unevenness in the dielectric layer thickness, thus making it impossible to meet the ±5% accuracy requirement for impedance control. Summary of the Invention

[0003] In view of this, the present invention provides a method for improving the uniformity of the dielectric thickness of the press-fit impedance layer and a computing power board.

[0004] The objective of this invention is achieved through the following technical solution: A method for improving the uniformity of dielectric thickness in a press-fit impedance layer includes the following steps: S1. A multilayer board lamination structure is provided, the multilayer board lamination structure includes at least a first conductive layer, a second conductive layer and a third conductive layer, the thickness of the second conductive layer is greater than the thickness of the first conductive layer, and the second conductive layer includes an impedance control region and a pure current-carrying region; S2. Perform copper removal in the pure current-passing region of the second conductive layer to reduce the residual copper rate of the pure current-passing region to match the residual copper rate of the impedance control region, with the difference not exceeding ±10 percentage points. S3. A blind hole is formed between the first conductive layer and the second conductive layer, and / or between the first conductive layer and the third conductive layer, and filled with conductive paste.

[0005] In the above technical solution, copper removal is performed in the pure current-carrying region of the second conductive layer (L2 layer) to reduce the residual copper ratio in the pure current-carrying region to match the residual copper ratio in the impedance control region. This makes the copper thickness of the L2 layer in the pure current-carrying region and the impedance control region more consistent. As a result, during the lamination process, the PP compression amount in the two regions is basically the same, and the dielectric layer thickness remains highly uniform throughout the entire board. This solves the problem of dielectric thickness non-uniformity caused by copper thickness differences, enabling the impedance control accuracy to meet the stringent requirement of ±5%.

[0006] Furthermore, by creating blind vias and filling them with conductive paste between the first and second conductive layers, and / or between the first and third conductive layers, the reliability of the interlayer electrical connection can be enhanced, the via resistance can be reduced, and the high current carrying capacity can be improved. This allows the L2 layer to still use a relatively thick original copper foil to meet the current carrying requirements. At the same time, by matching the residual copper ratio to eliminate the non-uniformity of the lamination, a balance between high current carrying capacity and high-precision impedance control can be achieved.

[0007] Optionally, in one possible implementation, the copper removal method in step S2 is as follows: copper removal is performed using a combination of grid copper and array windowing, with a grid line width of 4-12 mil and a grid spacing of 20-60 mil.

[0008] In the above technical solution, by adjusting the grid line width and spacing, the residual copper ratio in the pure current-carrying region can be flexibly controlled within the range of 20% to 40%, facilitating matching with the residual copper ratio in the impedance control region within ±10 percentage points, thereby ensuring the uniformity of the dielectric thickness after lamination. Furthermore, the grid copper structure avoids completely hollowing out the copper layer, ensuring that the current can still flow continuously along the grid lines; the array windowing further optimizes the current distribution. Compared to a uniform grid, the composite form can provide lower DC resistance at the same residual copper ratio, meeting the high current-carrying requirements while also considering impedance control.

[0009] Optionally, in one possible implementation, a transition band is provided between the pure current-carrying region and the impedance control region, and the transition band is greater than or equal to 1.0 mm.

[0010] In the above technical solution, the transition zone serves as a smooth transition area between the pure current-carrying region and the impedance control region for the residual copper ratio, avoiding abrupt changes in copper area at the direct interface of the two different pattern structures. A width of ≥1.0mm ensures a gradual transition in resin flow and fiberglass cloth deformation during lamination, thereby eliminating steep local changes in dielectric thickness and further improving the uniformity of the overall dielectric layer thickness.

[0011] Alternatively, in one possible implementation, the window density within the transition zone varies linearly or stepwise.

[0012] In the above technical solution, the gradual opening density provides a "gradual" flow channel for the resin during the pressing process. The resin can flow evenly from the high opening area to the low opening area, avoiding local high-speed scouring or retention of resin due to sudden density changes, and effectively reducing defects such as voids in the board, insufficient resin or twisted fiberglass cloth.

[0013] Alternatively, in one possible implementation, the grid shape of the copper grid is any one of a square, a rhombus, or a hexagon.

[0014] In the above technical solutions, different shapes of meshes have different guiding effects on resin flow during the pressing process. Hexagonal meshes, due to their 120° included angle, have the least resin flow resistance and the most uniform distribution, which can further reduce the internal stress of pressing. The acute angle area of ​​the rhomboid mesh can guide the resin to flow in a specific direction, which helps to control the directional uniformity of the medium thickness. Square meshes provide a balanced flow channel. Designers can select the optimal shape according to the laminate structure and pressing process, thereby reducing the risk of board warping and delamination.

[0015] Optionally, in one possible implementation, the blind vias in step S3 include a plurality of first blind vias connecting the first conductive layer and the second conductive layer and / or a plurality of second blind vias connecting the first conductive layer and the third conductive layer, wherein the first blind vias and the second blind vias are plugged with resin after being filled with conductive paste.

[0016] In the above technical solutions, after the conductive paste is filled, there may be micro-depressions or protrusions at the blind via opening. Direct lamination or fabrication of the outer layer circuitry will result in uneven surfaces, affecting the uniformity of dielectric layer thickness and impedance control. Adding additional resin plugs can make the via opening flush with the copper surface, achieving excellent surface flatness and thus eliminating local dielectric thickness deviations caused by the via opening morphology.

[0017] Optionally, in one possible implementation, the multilayer board lamination structure is provided with vias, the diameter of which is determined according to the electroplating aspect ratio capability, satisfying: the via diameter ≥ interlayer thickness / electroplating aspect ratio capability value, and copper is extracted in the second conductive layer according to the via diameter.

[0018] In the above technical solution, the via diameter is determined according to a formula, ensuring that the electroplating solution can fully fill the via wall under a given interlayer thickness, resulting in a uniform copper layer thickness without voids, rat tails, or other defects. This enables the via to have sufficient effective conductive cross-sectional area and low resistance under high current flow scenarios. In conjunction with copper removal and blind via filling solutions, it comprehensively guarantees high current flow capability from three dimensions: via wall conductivity, interlayer conductivity, and planar conductivity.

[0019] Optionally, in one possible implementation, the thickness of the first conductive layer is less than or equal to 2 oz, and the thickness of the second conductive layer is 3 oz to 6 oz.

[0020] In the above technical solution, the first conductive layer uses thin copper of ≤2OZ, which facilitates obtaining accurate line width and spacing through fine etching. At the same time, thin copper is not sensitive to changes in the thickness of the underlying dielectric layer, which is conducive to achieving stable high-precision impedance control of ±5%. The second conductive layer uses thick copper of 3OZ-6OZ, providing low DC resistance and a large current-carrying cross-section to meet the requirements of AI computing power boards for hundreds of amperes of current carrying capacity.

[0021] Optionally, in one possible implementation, the conductive paste is copper paste or silver paste, and the conductive paste forms a conductive interconnect structure after curing.

[0022] In the above technical solution, both copper paste and silver paste have excellent conductivity. After curing, they form a dense metal filler, ensuring a stable and low-ohm electrical connection between the first conductive layer and the second / third conductive layer, thus meeting the requirements of high current flow and low-loss signal transmission.

[0023] A computing power supply board is prepared by the above-mentioned method for improving the uniformity of the dielectric thickness of the press-fit impedance layer.

[0024] In the above technical solution, the computing power board achieves high-precision impedance control of ±5% in both L1 and L2 layers through multi-dimensional collaborative optimization, such as copper removal matching residual copper rate, blind via filling conductive paste, transition zone gradient design, grid copper selection, and thick and thin copper layer matching. At the same time, the pure current-carrying region of the L2 layer still has a large current-carrying capacity of 3OZ-6OZ thick copper. It perfectly solves the core contradiction of dielectric thickness unevenness and impedance runaway caused by thick copper in traditional solutions. It is the optimal solution for current AI computing power boards under the dual constraints of high power density and high signal integrity. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of a multilayer board pressing structure according to an embodiment of the present invention.

[0027] Reference numerals in the attached figures: 1-First conductive layer; 2-Second conductive layer; 3-Third conductive layer; 4-First blind via; 5-Second blind via. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0029] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0030] Please refer to Figure 1 This embodiment provides a method for improving the uniformity of the dielectric thickness of the press-fit impedance layer, comprising the following steps: S1. A multilayer board lamination structure is provided, the multilayer board lamination structure includes at least a first conductive layer 1, a second conductive layer 2 and a third conductive layer 3, the thickness of the second conductive layer 2 is greater than the thickness of the first conductive layer 1, and the second conductive layer 2 includes an impedance control region and a pure current-carrying region; wherein, one or more sheets of PP are laminated between two adjacent conductive layers. S2. Perform copper removal in the pure current-passing region of the second conductive layer 2 to reduce the residual copper rate in the pure current-passing region to match the residual copper rate in the impedance control region, with the difference not exceeding ±10 percentage points. S3. A blind hole is opened between the first conductive layer 1 and the second conductive layer 2, and / or between the first conductive layer 1 and the third conductive layer 3, and filled with conductive paste to restore the current carrying capacity lost due to copper removal.

[0031] By performing copper stripping in the pure current-carrying region of the second conductive layer 2 (L2 layer), the residual copper ratio in the pure current-carrying region is reduced to match the residual copper ratio in the impedance control region. This makes the copper thickness of the L2 layer in the pure current-carrying region and the impedance control region more consistent. As a result, during the lamination process, the PP compression amount in the two regions is basically the same, and the dielectric layer thickness remains highly uniform throughout the entire board. This solves the problem of dielectric thickness non-uniformity caused by copper thickness differences, enabling the impedance control accuracy to meet the stringent requirement of ±5%.

[0032] Furthermore, by creating blind vias and filling them with conductive paste between the first conductive layer 1 and the second conductive layer 2, and / or between the first conductive layer 1 and the third conductive layer 3, the reliability of the interlayer electrical connection can be enhanced, the via resistance can be reduced, and the high current carrying capacity can be improved. This allows the L2 layer as a whole to still use a relatively thick original copper foil to meet the current carrying requirements. At the same time, by matching the residual copper ratio to eliminate the non-uniformity of the lamination, a balance between high current carrying capacity and high-precision impedance control can be achieved.

[0033] In this embodiment, the copper removal method in step S2 is as follows: copper removal is performed using a combination of grid copper and array windowing. The grid line width is 4-12 mil, and the grid spacing is 20-60 mil. The grid copper is mesh-like, similar to a sieve, with square, hexagonal, or rhomboid mesh openings. The copper lines are relatively thin, and the copper within the mesh openings is etched away. The array windowing further removes larger square or circular copper areas on top of the grid copper, forming a composite structure of "large windows + fine grid". The combination of the two methods can precisely control the residual copper rate (e.g., reducing it from 95% to 30%-40% of the solid copper) and avoid stress concentration or current path breakage caused by large-area continuous copper removal.

[0034] By adjusting the grid line width and spacing, the residual copper ratio in the pure current-carrying region can be flexibly controlled within the range of 20% to 40%, facilitating matching with the residual copper ratio in the impedance control region within ±10 percentage points, thereby ensuring the uniformity of the dielectric thickness after lamination. Furthermore, the grid copper structure avoids completely hollowing out the copper layer, ensuring that current can still flow continuously along the grid lines; the array windowing further optimizes the current distribution. Compared to a uniform grid, the composite form can provide lower DC resistance at the same residual copper ratio, meeting the high current-carrying requirements while also considering impedance control.

[0035] Understandably, if a large-area, fully open-window copper extraction method is used in the pure current-passing region, the large copper surface area will lose the structural support of the copper foil, making it highly susceptible to reliability issues such as warping and delamination during high-temperature, high-pressure lamination and subsequent thermal cycling. In this embodiment, a grid linewidth of 4-12 mil forms a continuous copper skeleton network within the pure current-passing region. This effectively reduces the residual copper ratio to match the impedance control area while maintaining sufficient copper foil continuity, significantly enhancing the mechanical rigidity and anti-warping capability of the large copper surface area, ensuring the structural reliability of the multilayer board during high-temperature lamination and actual use.

[0036] Different mesh shapes have different guiding effects on resin flow during the lamination process. Hexagonal meshes, due to their 120° included angle, have the least resistance to resin flow and the most uniform distribution, which can further reduce the internal stress of lamination. The acute angle area of ​​the rhomboid mesh can guide the resin to flow in a specific direction, which helps to control the directional uniformity of the medium thickness. Square meshes provide a balanced flow channel. Designers can choose the optimal shape according to the laminate structure and lamination process, thereby reducing the risk of board warping and delamination.

[0037] In this embodiment, a transition band is provided between the pure current-carrying region and the impedance control region, and the transition band is greater than or equal to 1.0 mm.

[0038] The transition zone, serving as a smooth transition area between the pure current-carrying region and the impedance control region, avoids abrupt changes in copper area at the direct interface of two different pattern structures. A width of ≥1.0 mm ensures a gradual transition in resin flow and fiberglass cloth deformation during lamination, thereby eliminating steep local changes in dielectric thickness and further improving the uniformity of the overall dielectric layer thickness.

[0039] It should be noted that the window density within the transition zone varies linearly or stepwise. For example, the window density increases or decreases from the pure current-carrying region to the impedance-controlled region.

[0040] Gradual window density provides a "progressive" flow channel for the resin during the pressing process. The resin can flow evenly from the high window area to the low window area, avoiding local high-speed scouring or stagnation of resin caused by sudden density changes, and effectively reducing defects such as voids in the board, insufficient resin or twisted fiberglass cloth.

[0041] Understandably, linearly gradient copper content varies uniformly and continuously within the transition band, resulting in the smoothest dielectric thickness transition. This is suitable for scenarios with extremely high impedance continuity requirements and ample transition band width (≥1.0mm), achieving optimal impedance gradient consistency. Stepped gradient divides the transition band into several sub-segments, with a constant window density within each segment and step-like transitions between segments. This is suitable for scenarios with limited transition band width or where multiple different copper content target values ​​need to be considered. While ensuring dielectric thickness uniformity, it simplifies design and manufacturing complexity and reduces process implementation difficulty.

[0042] In this embodiment, the blind holes in step S3 include a plurality of first blind holes 4 connecting the first conductive layer 1 and the second conductive layer 2 and / or a plurality of second blind holes 5 connecting the first conductive layer 1 and the third conductive layer 3. The first blind holes 4 and the second blind holes 5 are plugged with resin after being filled with conductive paste.

[0043] After the conductive paste is filled, there may be micro-depressions or protrusions at the opening of the blind via. Direct lamination or fabrication of the outer layer circuitry can lead to surface unevenness, affecting the uniformity of dielectric layer thickness and impedance control. Adding additional resin plugs can make the via opening flush with the copper surface, achieving excellent surface flatness and thus eliminating local dielectric thickness deviations caused by the via shape.

[0044] In this embodiment, the multilayer board lamination structure includes vias. The via diameter is determined based on the electroplating aspect ratio capability, satisfying the condition: via diameter ≥ interlayer thickness / electroplating aspect ratio capability. Copper is then extracted in the second conductive layer 2 according to the via diameter. For example, if the thickness of L1-L3 is 25mil and the electroplating aspect ratio capability is 2, the laser via diameter needs to be designed to be 13.78mil. Copper extraction is then performed in layer L2 according to the laser via diameter, such as increasing it by 8mil on one side, resulting in a pad diameter of 29.78mil.

[0045] The via diameter is determined by a formula to ensure that, given the interlayer thickness, the electroplating solution can fully fill the via wall, resulting in a uniform copper layer thickness free of voids, rat tails, and other defects. This gives the via sufficient effective conductive cross-sectional area and low resistance under high current flow scenarios. In conjunction with copper removal and blind via filling solutions, it comprehensively guarantees high current flow capability from three dimensions: via wall conductivity, interlayer conductivity, and planar conductivity.

[0046] In this embodiment, the thickness of the first conductive layer 1 is less than or equal to 2 oz, and the thickness of the second conductive layer 2 is 3 oz to 6 oz. The first conductive layer 1 uses thin copper of ≤2 oz, which facilitates obtaining accurate line width and spacing through fine etching. At the same time, thin copper is not sensitive to changes in the thickness of the underlying dielectric layer, which is beneficial for achieving stable high-precision impedance control of ±5%. The second conductive layer 2 uses thick copper of 3 oz to 6 oz, providing low DC resistance and a large current-carrying cross-section to meet the requirements of AI computing power boards for hundreds of amperes of current carrying capacity.

[0047] It should be noted that the conductive paste is either copper or silver paste, which forms a conductive interconnect structure after curing. Both copper and silver pastes have excellent conductivity and form a dense metallic filler after curing, ensuring a stable and low-ohmic electrical connection between the first conductive layer 1 and the second / third conductive layer 3, meeting the requirements for high current carrying capacity and low-loss signal transmission.

[0048] This embodiment also provides a computing power board, which is prepared by the above-described method for improving the uniformity of the dielectric thickness of the press-fit impedance layer.

[0049] The computing power board achieves high-precision impedance control of ±5% in both L1 and L2 layers through multi-dimensional collaborative optimization, including copper removal to match residual copper rate, blind via filling with conductive paste, gradient transition zone design, grid copper selection, and combination of thick and thin copper layers. At the same time, the pure current-carrying region of the L2 layer still has a large current-carrying capacity at the level of 3OZ-6OZ thick copper. It perfectly solves the core contradiction of dielectric thickness unevenness and impedance runaway caused by thick copper in traditional solutions. It is the optimal solution for current AI computing power boards under the dual constraints of high power density and high signal integrity.

[0050] In the description of this invention, it should be understood that terms such as "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0052] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for improving the uniformity of dielectric thickness in a press-fit impedance layer, characterized in that, Includes the following steps: S1. A multilayer board lamination structure is provided, the multilayer board lamination structure includes at least a first conductive layer, a second conductive layer and a third conductive layer, the thickness of the second conductive layer is greater than the thickness of the first conductive layer, and the second conductive layer includes an impedance control region and a pure current-carrying region; S2. Perform copper removal in the pure current-passing region of the second conductive layer to reduce the residual copper rate of the pure current-passing region to match the residual copper rate of the impedance control region, with the difference not exceeding ±10 percentage points. S3. A blind hole is formed between the first conductive layer and the second conductive layer, and / or between the first conductive layer and the third conductive layer, and filled with conductive paste.

2. The method for improving the uniformity of the dielectric thickness of the press-fit impedance layer according to claim 1, characterized in that, The copper removal method in step S2 is as follows: copper removal is performed using a combination of grid copper and array windowing, with a grid line width of 4-12 mil and a grid spacing of 20-60 mil.

3. The method for improving the uniformity of the dielectric thickness of the press-fit impedance layer according to claim 2, characterized in that, A transition band is provided between the pure current-carrying region and the impedance control region, and the transition band is greater than or equal to 1.0 mm.

4. The method for improving the uniformity of the dielectric thickness of the press-fit impedance layer according to claim 3, characterized in that, The window density within the transition zone exhibits a linear or stepwise gradient.

5. The method for improving the uniformity of the dielectric thickness of the press-fit impedance layer according to claim 2, characterized in that, The grid shape of the copper grid can be any one of a square, rhombus, or hexagon.

6. The method for improving the uniformity of the dielectric thickness of the press-fit impedance layer according to claim 1, characterized in that, The blind holes in step S3 include a plurality of first blind holes connecting the first conductive layer and the second conductive layer and / or a plurality of second blind holes connecting the first conductive layer and the third conductive layer. The first blind holes and the second blind holes are plugged with resin after being filled with conductive paste.

7. The method for improving the uniformity of the dielectric thickness of the press-fit impedance layer according to claim 1, characterized in that, The multilayer board lamination structure is provided with vias. The diameter of the vias is determined according to the electroplating aspect ratio capability, satisfying: the via diameter ≥ interlayer thickness / electroplating aspect ratio capability value, and copper is extracted in the second conductive layer according to the via diameter.

8. The method for improving the uniformity of the dielectric thickness of the press-fit impedance layer according to claim 1, characterized in that, The thickness of the first conductive layer is less than or equal to 2 oz, and the thickness of the second conductive layer is 3 oz to 6 oz.

9. The method for improving the uniformity of the dielectric thickness of the press-fit impedance layer according to claim 1, characterized in that, The conductive paste is copper paste or silver paste, and after curing, it forms a conductive interconnect structure.

10. A computing power supply board, characterized in that, It is prepared by the method described in any one of claims 1-9.

Images