Enhanced gallium nitride power device and method of making same

Abstract

The application provides an enhanced gallium nitride power device, which comprises, from bottom to top, a substrate, a buffer layer, a channel layer, a barrier layer and a gate, wherein the gate comprises a P-type semiconductor layer and a gate metal, and further comprises a first passivation layer and a second passivation layer; the first passivation layer covers the top and sidewall of the gate metal and the upper surface of the P-type semiconductor layer which is not covered by the gate metal; the second passivation layer covers the top and sidewall of the first passivation layer, the sidewall of the P-type semiconductor layer and the upper surface of the barrier layer which is not covered by the source, the drain and the gate, and the hydrogen atom content of the first passivation layer is lower than that of the second passivation layer. By arranging the first passivation layer with a lower hydrogen atom content between the gate metal and the surface of the P-type semiconductor layer, the second passivation layer with a higher hydrogen content does not directly contact the top of the P-type semiconductor layer and the gate metal / pGaN interface, so that the threshold voltage of the device remains stable under high-temperature processing and working conditions.

Description

Technical Field

[0001] This application relates to the field of semiconductor power device technology, specifically to an enhanced gallium nitride power device and its fabrication method. Background Technology

[0002] The description in this section provides only background information relevant to the disclosure of this application and does not constitute prior art.

[0003] Figure 1 This illustrates a typical enhancement-mode HEMT device in the prior art, whose gate comprises a gate metal / P-type semiconductor (pGaN) structure. The width of the gate metal is smaller than the width of the P-type semiconductor, thus the upper surface of the P-type semiconductor is in direct contact with the first passivation layer.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] Reference Figure 2 As shown, through the applicant's inventive discovery, the epitaxial passivation layer is usually made of materials such as silicon nitride, which contains a large number of hydrogen atoms. Under high temperature, hydrogen atoms diffuse from silicon nitride into the interior of the P-type semiconductor layer and the interface between the gate metal and the P-type semiconductor layer, thereby affecting the threshold voltage and gate reliability of the device.

[0006] This application aims to solve the technical problem in existing enhanced gallium nitride power devices where hydrogen atoms in the epitaxial passivation layer (silicon nitride) diffuse to the P-type semiconductor layer and the gate metal / P-type semiconductor layer interface under high temperature conditions, resulting in device threshold voltage drift and reduced gate reliability.

[0007] To achieve the above objectives, this application provides the following technical solution: An enhanced gallium nitride power device includes, from bottom to top, a substrate, a buffer layer, a channel layer, a barrier layer, a source, a drain, and a gate formed on the barrier layer, wherein the source and the drain are located on opposite sides of the gate, and the gate includes a P-type semiconductor layer and a gate metal formed on the P-type semiconductor layer, and further includes a first passivation layer and a second passivation layer. The first passivation layer covers the top and sidewalls of the gate metal and the upper surface of the P-type semiconductor layer that is not covered by the gate metal; The second passivation layer covers the top and sidewalls of the first passivation layer, the sidewalls of the P-type semiconductor layer, and the upper surface of the barrier layer that is not covered by the source, drain, and gate. The hydrogen atom content of the first passivation layer is lower than that of the second passivation layer.

[0008] Preferably, the material of the first passivation layer is selected from any one or more combinations of SiN, SiO2, SiON, AlN, Al2O3, AlON, and HfO2.

[0009] Preferably, the thickness of the first passivation layer ranges from 0.1 nm to 1 μm.

[0010] Preferably, the first passivation layer and the second passivation layer use the same dielectric material, and the difference in hydrogen atom content is achieved through different deposition processes.

[0011] Preferably, the first passivation layer is LPCVD SiN, and the second passivation layer is PE-SiN.

[0012] Preferably, the P-type semiconductor layer is at least one of P-type doped GaN, P-type doped AlGaN, P-type doped InGaN, and P-type doped GaN / InGaN superlattice structure.

[0013] Preferably, the second passivation layer is any one or more combinations of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxide (Al2O3), aluminum oxynitride (AlON), and hafnium oxide (HfO2).

[0014] Preferably, it further includes a third passivation layer, which covers the second passivation layer and the source and drain.

[0015] Preferably, the third passivation layer is any one or a combination of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), polyimide (PI), and benzocyclobutene (BCB).

[0016] This application also discloses a method for fabricating an enhanced gallium nitride power device as described above, characterized by comprising the following steps: S1. A buffer layer, a channel layer, a barrier layer, and a P-type semiconductor layer are epitaxially grown sequentially on the substrate. S2. Deposit gate metal on the P-type semiconductor layer and form patterned gate metal by etching; S3. Deposit the first passivation layer over the entire area, so that the first passivation layer completely covers the upper surface of the gate metal and the P-type semiconductor material; S4. Etch the regions on both sides of the P-type semiconductor material from the first passivation material to form the gate and the first passivation layer; S5. Deposit a second passivation material to form the second passivation layer, so that the second passivation layer covers the sidewall of the P-type semiconductor layer, the barrier layer and the outer side of the first passivation layer; S6. Etch ohmic contact openings on the second passivation material to prepare source metal and drain metal; S7, Deposit the third passivation layer.

[0017] The beneficial effects of this application, based on the above technical solutions, are as follows: (1) Significantly improved threshold voltage stability: This application provides a first passivation layer with a low hydrogen atom content on the surface of the gate metal and the P-type semiconductor layer, so that the second passivation layer with a high hydrogen content does not directly contact the top of the P-type semiconductor layer and the gate metal / P-type semiconductor interface. Under high temperature conditions, hydrogen atoms in the second passivation layer need to pass through the first passivation layer before reaching the P-type semiconductor layer and the gate interface. Since the hydrogen atom content of the first passivation layer is low and it acts as a dense diffusion barrier layer, it effectively blocks the inward diffusion of hydrogen atoms in the second passivation layer, thereby significantly reducing the influence of hydrogen atoms on the P-type semiconductor layer and the gate interface, and keeping the threshold voltage of the device stable under high temperature process and operating conditions.

[0018] (2) Improved gate reliability: Due to the reduction of hydrogen atom aggregation at the gate metal / pGaN interface, the degree of change in interface state density and interface dipole is reduced, the long-term stability and durability of the gate structure are improved, and the device performs better in high-temperature operating life test.

[0019] (3) Flexible structural design and strong process compatibility: The first passivation layer and the second passivation layer can use the same dielectric material (such as SiN) and achieve hydrogen content differences through different deposition processes (such as LPCVD and PECVD). It is highly compatible with the existing GaN power device manufacturing process, without the need to introduce complex new equipment and additional photolithography steps, which facilitates industrialization.

[0020] Specific embodiments of this application are disclosed in detail with reference to the following description and accompanying drawings, illustrating how the principles of this application can be employed. It should be understood that the embodiments of this application are not limited in scope. Within the spirit and scope of the appended claims, the embodiments of this application include many changes, modifications, and equivalents.

[0021] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0022] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components. Attached Figure Description

[0023] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of this application in any way. Furthermore, the shapes and scales of the components in the drawings are merely illustrative to aid in understanding this application and do not specifically limit the shapes and scales of the components. Those skilled in the art, guided by the teachings of this application, can select various possible shapes and scales to implement this application according to specific circumstances. In the drawings: Figure 1 This is a schematic diagram of the structure of an enhanced gallium nitride power device in the prior art.

[0024] Figure 2 This is a schematic diagram illustrating the diffusion of hydrogen atoms from the epitaxial passivation layer to the P-type semiconductor layer and the gate metal / pGaN interface in the prior art.

[0025] Figure 3 This is a schematic diagram of an embodiment of the enhanced gallium nitride power device of this application.

[0026] Figures 4A-4H for Figure 3 Process flow diagram of medium-enhanced gallium nitride power device fabrication method.

[0027] The meanings of the markings in the attached figures are as follows: 1. Substrate; 2. Buffer layer; 3. Channel layer; 4. Barrier layer; 5. P-type semiconductor layer; 6. Gate metal; 7. First passivation layer; 71. First plate portion; 72. Sidewall portion; 73. Second plate portion; 8. Second passivation layer; 81. Third plate portion; 82. First side portion; 83. Fourth plate portion; 84. Second side portion; 85. Fifth plate portion; 9. Source; 10. Drain; 11. Third passivation layer. Detailed Implementation

[0028] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0029] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only embodiments.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0031] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0032] It should be noted that in the description of this application, the terms "first," "second," etc., are used only for descriptive purposes and to distinguish similar objects; there is no order between them, nor should they be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more.

[0033] Reference Figure 3 As shown, this application provides an enhancement-mode gallium nitride power device, which is generally a pGaN gate enhancement-mode high electron mobility transistor (HEMT). The device includes a substrate 1, a buffer layer 2, a channel layer 3, and a barrier layer 4 stacked sequentially from bottom to top.

[0034] Specifically, the substrate 1 serves as the underlying support structure of the device. The substrate 1 can be made of conventional substrate materials, such as silicon substrate 1, sapphire substrate 1, or silicon carbide substrate 1, or it can be a composite of several materials, such as silicon on insulator (SOI). The thickness of the substrate 1 is generally in the range of 300µm-3000µm. In this embodiment, a silicon substrate 1 is preferably used to reduce manufacturing costs and facilitate compatibility with existing semiconductor processes. When using a Si substrate 1, its resistivity ranges from 0.001 to 5000 Ω·cm.

[0035] The buffer layer 2 is located on the substrate 1. The function of the buffer layer 2 is to alleviate lattice and thermal mismatch between the substrate 1 and the upper epitaxial layer, reduce the extension of defects and dislocations into the epitaxial layer, and provide a transition layer for subsequent high-quality epitaxial growth. The buffer layer 2 can be composed of different materials depending on the substrate 1 and specific requirements. For example, when using a silicon substrate 1, it can be composed of an AlN nucleation layer, one or more AlGaN transition layers, a superlattice buffer layer 2 formed by alternating periods of AlN and AlGaN, and a high-carbon layer (carbon concentration greater than 10%). 18 cm -3 It can be composed of GaN layers, or sequentially of AlN nucleation layers, one or more AlGaN layers, and high carbon (carbon concentration greater than 10). 18 cm -3 It consists of GaN layers.

[0036] The channel layer 3 is located above the buffer layer 2. Channel layer 3 is the main region containing the two-dimensional electron gas (2DEG) conductive channel in this device. Channel layer 3 can be formed of a semiconductor material, for example, a low-carbon material (carbon concentration less than 10⁻⁶). 18 cm -3 GaN is a high-carrier-mobility and good-thermal-stability material, making it suitable as a channel layer for power devices.

[0037] The barrier layer 4 is located above the channel layer 3. The barrier layer 4 can be formed of a semiconductor material, such as a ternary or quaternary alloy compound based on gallium nitride, such as Al. x Ga 1x N, AlInGaN, In x Ga 1x N, Al x In 1x Al, AlScN. In this embodiment, the barrier layer 4 is an AlGaN barrier layer 4. An AlGaN / GaN heterojunction is formed between the AlGaN barrier layer 4 and the underlying GaN channel layer 3. Due to the spontaneous polarization and piezoelectric polarization effects between the AlGaN and GaN materials, a high-concentration, high-mobility two-dimensional electron gas is formed at the heterojunction interface near the GaN channel layer 3. This two-dimensional electron gas serves as the conductive channel when the device is turned on. The barrier layer 4 provides polarization to form the two-dimensional electron gas and withstands reverse bias in the off state.

[0038] The source 9, gate, and drain 10 are all disposed above the barrier layer 4. Specifically, the source 9 and drain 10 are electrically connected to the barrier layer 4 and the two-dimensional electron gas below it through ohmic contacts, serving as the current input and output terminals of the device, respectively. The gate is disposed between the source 9 and drain 10. By applying a bias voltage to the gate, the concentration of the two-dimensional electron gas in the channel below the gate can be adjusted, thereby controlling the on and off states of the device.

[0039] The gate comprises a P-type semiconductor layer 5 and a gate metal 6 formed on the P-type semiconductor layer 5. The P-type semiconductor layer 5 is at least one of P-type doped GaN, P-type doped AlGaN, P-type doped InGaN, or a P-type doped GaN / InGaN superlattice structure. The gate metal 6 is typically made of any one or more combinations of nickel (Ni), gold (Au), tungsten (W), platinum (Pt), and molybdenum (Mo), and may also be a Ni / Au stacked structure, or a TiN / Ti / Al stacked structure, etc.

[0040] Similar to existing technologies, the lateral width of the gate metal 6 is smaller than the lateral width of the P-type semiconductor layer 5, meaning that on both sides of the gate metal 6, the upper surface portion of the P-type semiconductor layer 5 is exposed outside the gate metal 6. This structural feature allows the subsequent first passivation layer 7 to cover the area on the upper surface of the P-type semiconductor layer 5 that is not covered by the gate metal 6, which is crucial for the hydrogen diffusion blocking effect of this application (the specific function will be explained in detail below in conjunction with the function of the first passivation layer 7).

[0041] Reference Figure 4E As shown, a first passivation layer 7 is disposed in the gate region. The first passivation layer 7 includes a first plate portion 71, two sidewall portions 72 formed on both sides of the first plate portion 71, and two second plate portions 73. The first plate portion 71 of the first passivation layer 7 covers the top surface of the gate metal 6. The sidewall portions 72 of the first passivation layer 7 cover the outer sidewall surfaces of the gate metal 6. The two second plate portions 73 of the first passivation layer 7 cover the upper surface of the P-type semiconductor layer 5 that is not covered by the gate metal 6. As mentioned above, since the width of the gate metal 6 is smaller than the width of the P-type semiconductor layer 5, there are exposed areas (i.e., edge upper surface areas of the P-type semiconductor layer 5) on both sides of the gate metal 6 on the upper surface of the P-type semiconductor layer 5 that are not covered by the gate metal 6. The two second plate portions 73 of the first passivation layer 7 cover these exposed areas, so that the upper surface of the P-type semiconductor layer 5 is protected by a low-hydrogen passivation layer. Preferably, the second plate portions 73 of the first passivation layer 7 are flush with the sidewalls of their corresponding P-type semiconductor layers 5.

[0042] In summary, the first passivation layer 7 forms a complete "coverage" of the gate metal 6. In a cross-sectional view, the outline of the first passivation layer 7 presents a structure resembling a "hat" or an "inverted concave shape".

[0043] The choice of material for the first passivation layer 7 is crucial to achieving the technical effects of this application. Since the first passivation layer 7 needs to have a low hydrogen atom content, its material should be an insulating dielectric material with low hydrogen atom doping under conventional deposition process conditions. In this embodiment, the material of the first passivation layer 7 is selected from any one or more combinations of SiN, SiO2, SiON, AlN, Al2O3, AlON, and HfO2. Silicon nitride (SiN) prepared using low-pressure chemical vapor deposition (LPCVD) is one of the preferred options because the hydrogen content of LPCVD SiN films is typically much lower than that of PECVD SiN films. Other materials such as SiO2 and Al2O3 can also achieve low hydrogen content through atomic layer deposition (ALD) or reactive sputtering processes, and possess good insulation and density. All of the above materials have good insulation properties and thermal stability, and can be effectively used as hydrogen diffusion barrier layers.

[0044] The thickness of the first passivation layer 7 is also a crucial factor affecting its hydrogen diffusion barrier effect. If the first passivation layer 7 is too thin, it may not provide sufficient physical barrier thickness, and hydrogen atoms may still tunnel through the first passivation layer 7 at high temperatures to reach the P-type semiconductor layer 5 and the gate interface. If the first passivation layer 7 is too thick, it may increase device manufacturing time and cost, and may introduce stress problems. In this application, the thickness of the first passivation layer 7 ranges from 0.1 nm to 1 μm. In a more preferred embodiment, the thickness of the first passivation layer 7 ranges from 0.5 nm to 200 nm. Within this preferred range, the first passivation layer 7 can provide an effective hydrogen diffusion barrier thickness while maintaining good process compatibility and stress matching.

[0045] Reference Figure 4G As shown, the second passivation layer 8 includes a third plate portion 81 covering the first plate portion 71 above the first passivation layer 7, a first side portion 82 covering the outside of the sidewall portion 72 of the first passivation layer 7, a fourth plate portion 83 covering the second plate portion 73, a second side portion 84 covering the outside of the sidewall formed by the P-type semiconductor layer 5 and the second plate portion 73 of the first passivation layer 7, and a fifth plate portion 85 covering the upper surface of the barrier layer 4 that is not covered by the source 9, drain 10 and gate.

[0046] In this application, the material of the second passivation layer 8 can be any one or more combinations of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxide (Al2O3), aluminum oxynitride (AlON), and hafnium oxide (HfO2). It should be noted that the material of the second passivation layer 8 can be the same as that of the first passivation layer 7 (both being SiN, etc.) or different from that of the first passivation layer 7. However, regardless of the material, the hydrogen atom content of the second passivation layer 8 is higher than that of the first passivation layer 7. In a preferred embodiment, the first passivation layer 7 and the second passivation layer 8 use the same dielectric material (e.g., both being silicon nitride), but the difference in hydrogen atom content is achieved through different deposition processes. Specifically, the first passivation layer 7 is silicon nitride (LPCVD SiN) prepared using a low-pressure chemical vapor deposition (LPCVD) process, while the second passivation layer 8 is silicon nitride (PE-SiN) prepared using a plasma-enhanced chemical vapor deposition (PECVD) process. LPCVD SiN deposition typically occurs at high temperatures (approximately 700℃–800℃), using dichlorosilane (SiH₂Cl₂) and ammonia (NH₃) as reactant gases. Deposition occurs under low-pressure conditions, resulting in SiN films with high density and low hydrogen content. PECVD SiN deposition occurs at lower temperatures (approximately 250℃–350℃), using silane (SiH₄) and ammonia (NH₃) or nitrogen (N₂) as reactant gases. Deposition occurs under radio frequency plasma assistance, resulting in SiN films with a higher concentration of hydrogen atoms (incorporated from H atoms in the reactant gases). Therefore, even if the first passivation layer 7 and the second passivation layer 8 are both SiN materials, their hydrogen content can be differentiated by selecting the deposition process.

[0047] In this application, the hydrogen atom content of the first passivation layer 7 is lower than that of the second passivation layer 8. The first passivation layer 7 itself is a low-hydrogen-content insulating dielectric film, while the second passivation layer 8 is a high-hydrogen-content insulating dielectric film. For example, the first passivation layer is SiN grown by LPCVD, wherein the H content is between 2% and 8%, and the second passivation layer is SiN grown by PECVD, wherein the H content is between 20% and 30%.

[0048] This application also includes a third passivation layer 11, which covers the second passivation layer 8 and the source 9 and drain 10.

[0049] The third passivation layer 11 provides passivation protection for the entire device. The third passivation layer 11 covers the upper surface of the second passivation layer 8, and also covers the upper surfaces of the source electrode 9 and the drain electrode 10. The presence of the third passivation layer 11 ensures that the entire upper surface of the device is protected. In actual device fabrication, since the source electrode 9 and drain electrode 10 need to be connected to external electrodes, the third passivation layer 11 typically has contact hole openings at the source electrode 9 and drain electrode 10 locations. These openings are used for subsequent metal interconnection and pad fabrication.

[0050] The third passivation layer 11 is any one or a combination of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), polyimide (PI), and benzocyclobutene (BCB).

[0051] The third passivation layer 11 can be a single-layer structure or a multi-layer stacked structure. In one embodiment, the third passivation layer 11 adopts a SiO2 / SiN bilayer structure, wherein SiO2 serves as a stress buffer layer 2 in contact with the second passivation layer 8, and SiN serves as the top moisture-proof layer. In another embodiment, the third passivation layer 11 adopts a polyimide single-layer structure with a thickness of 5μm to 20μm, providing good stress relief and mechanical protection.

[0052] It should be noted that the third passivation layer 11 is located above the second passivation layer 8 and the source / drain electrode 9, and does not affect the hydrogen content relationship and spatial coverage relationship between the first passivation layer 7 and the second passivation layer 8. The presence of the third passivation layer 11 further enhances the overall environmental tolerance of the device.

[0053] This application also provides a method for fabricating an enhanced gallium nitride power device, comprising the following steps: Reference Figure 4A As shown, S1, a buffer layer 2, a channel layer 3, a barrier layer 4, and a P-type semiconductor layer 5 are epitaxially grown sequentially on substrate 1.

[0054] Crystal growth of each layer can be performed on substrate 1 using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) techniques.

[0055] Specifically, the substrate 1 is first placed in the MOCVD reaction chamber, and the buffer layer 2, the channel layer 3, the barrier layer 4, and the P-type semiconductor layer 5 are grown sequentially.

[0056] Reference Figure 4B and 4C As shown, in step S2, gate metal 6 material is deposited on the P-type semiconductor layer 5, and patterned gate metal 6 is formed by etching.

[0057] A gate metal 6 material is deposited over the entire surface of the upper surface of the P-type semiconductor layer 5 to form the gate metal 6. After deposition, the gate metal 6 material is etched by photolithography to form the gate metal 6.

[0058] Reference Figure 4D As shown, in step S3, a first passivation layer 7 is deposited over the entire domain, so that the first passivation layer 7 completely covers the upper surface and sidewalls of the gate metal 6, as well as the upper surface of the P-type semiconductor layer 5 that is not covered by the gate metal 6.

[0059] Reference Figure 4E As shown, S4 etches the regions on both sides of the P-type semiconductor layer 5 to expose the mesa of the barrier layer 4.

[0060] Photoresist is coated onto the surface of the structure formed in S3, and the areas to be etched (i.e., the areas on both sides of the P-type semiconductor layer 5 that do not need to be retained) are defined by photolithography. Then, the first passivation layer 7 and the P-type semiconductor layer 5 are etched sequentially until the upper surface of the barrier layer 4 is exposed. After etching, the photoresist is removed, forming the mesa structure of the P-type semiconductor layer 5 and the first passivation layer 7. At this point, the P-type semiconductor layer 5 is only retained below and near the gate metal 6 (the width of the P-type semiconductor layer 5 is greater than that of the gate metal 6), while the active region surface of the barrier layer 4 is exposed. At this point, the first passivation layer 7 covers the top and sidewalls of the gate metal 6 and the upper surface of the P-type semiconductor layer 5 that is not covered by the gate metal 6.

[0061] Reference Figure 4F As shown, in step S5, a second passivation layer 8 is deposited, so that the second passivation layer 8 covers the outer side of the first passivation layer 7 and the barrier layer 4 not covered by the first passivation layer 7.

[0062] Reference Figure 4G and 4H As shown, in step S6, ohmic contact openings are etched on the second passivation layer 8 to prepare the source electrode 9 and the drain electrode 10.

[0063] Reference Figure 3 As shown, in step S7, a third passivation layer 11 is deposited on the second passivation layer 8, the source electrode 9, and the drain electrode 10.

[0064] It should be understood that the above description is for illustrative purposes and not for limitation. Many embodiments and applications beyond the provided examples will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this teaching should not be determined by reference to the above description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed application subject matter.

Claims

1. An enhancement-mode gallium nitride power device, comprising, from bottom to top, a substrate, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode, and a gate electrode formed on the barrier layer, wherein the source electrode and the drain electrode are located on opposite sides of the gate electrode, and the gate electrode comprises a p-type semiconductor layer and a gate metal formed on the p-type semiconductor layer, characterized in that, It also includes a first passivation layer and a second passivation layer; The first passivation layer covers the top and sidewalls of the gate metal and the upper surface of the P-type semiconductor layer that is not covered by the gate metal; The second passivation layer covers the top and sidewalls of the first passivation layer, the sidewalls of the P-type semiconductor layer, and the upper surface of the barrier layer that is not covered by the source, drain, and gate. The hydrogen atom content of the first passivation layer is lower than that of the second passivation layer.

2. The enhanced gallium nitride power device according to claim 1, characterized in that, The material of the first passivation layer is selected from any one or more combinations of SiN, SiO2, SiON, AlN, Al2O3, AlON, and HfO2.

3. The enhanced gallium nitride power device according to claim 1, characterized in that, The thickness of the first passivation layer ranges from 0.1 nm to 1 μm.

4. The enhanced gallium nitride power device according to claim 1, characterized in that, The first passivation layer and the second passivation layer use the same dielectric material, but achieve the difference in hydrogen atom content through different deposition processes.

5. The enhanced gallium nitride power device according to claim 4, characterized in that, The first passivation layer is LPCVD SiN, and the second passivation layer is PE-SiN.

6. The enhanced gallium nitride power device according to claim 1, characterized in that, The P-type semiconductor layer is at least one of P-type doped GaN, P-type doped AlGaN, P-type doped InGaN, and P-type doped GaN / InGaN superlattice structure.

7. The enhanced gallium nitride power device according to claim 1, characterized in that, The second passivation layer is any one or a combination of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxide (Al2O3), aluminum oxynitride (AlON), and hafnium oxide (HfO2).

8. The enhanced gallium nitride power device according to claim 1, characterized in that, It also includes a third passivation layer, which covers the second passivation layer and the source and drain.

9. The enhanced gallium nitride power device according to claim 8, characterized in that, The third passivation layer is any one or a combination of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), polyimide (PI), and benzocyclobutene (BCB).

10. A method for fabricating an enhanced gallium nitride power device, characterized in that, Includes the following steps: S1. A buffer layer, a channel layer, a barrier layer, and a P-type semiconductor layer are epitaxially grown sequentially on the substrate. S2. Deposit gate metal on the P-type semiconductor layer and form patterned gate metal by etching; S3. Deposit the first passivation layer over the entire area, so that the first passivation layer completely covers the upper surface of the gate metal and the P-type semiconductor material; S4. Etch the regions on both sides of the P-type semiconductor material from the first passivation material to form the gate and the first passivation layer; S5. Deposit a second passivation material to form the second passivation layer, so that the second passivation layer covers the sidewall of the P-type semiconductor layer, the barrier layer and the outer side of the first passivation layer; S6. Etch ohmic contact openings on the second passivation material to prepare source metal and drain metal; S7, Deposit the third passivation layer.

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