Silicon-based germanium epitaxial structure and manufacturing method

Abstract

The application provides a silicon-based germanium epitaxial structure and a manufacturing method. After a silicon groove is formed by etching, a germanium sacrificial layer is formed on the surface of the silicon groove to absorb oxygen plasma residual defects on the surface of the silicon groove, and then the germanium sacrificial layer is removed to remove the oxygen plasma residual defects. After the oxygen plasma residual defects are removed, a base silicon layer is formed on the surface of the silicon groove by a deposition process, so that the high-quality base silicon layer serves as a base for forming a germanium epitaxial layer. That is, the germanium sacrificial layer is used to remove the oxygen plasma residual defects on the surface of the silicon groove, and the deposition process is used to form a high-quality base silicon layer on the surface of the silicon groove, and then the germanium epitaxial layer is formed. After the germanium epitaxial layer is formed, the interface between silicon and germanium is flat, and the crystal quality and uniformity of germanium are high.

Description

Technical Field

[0001] This invention belongs to the field of silicon-based germanium photodetector technology, and relates to a silicon-based germanium epitaxial structure and its fabrication method. Background Technology

[0002] With the advent of the artificial intelligence era, big data processing has become a key link in information and communication technology. Silicon photonics chips, with their efficient data processing capabilities, are gradually becoming the core direction of current and future development. Against this backdrop, the large-scale mass production of 12-inch large-size wafers has become a hot research topic and a mainstream trend for major chip manufacturers. As the core device of silicon photonics chips, the performance of silicon-based germanium photodetectors largely depends on the crystal quality of the germanium epitaxial layer.

[0003] In silicon photonics chip manufacturing, silicon-based germanium photodetectors typically require precise alignment and efficient coupling with silicon waveguide structures. To achieve this, silicon grooves of specific shapes are often pre-etched into the silicon substrate, and then germanium is epitaxially grown within these structures. While performing germanium epitaxy after forming silicon grooves facilitates heterogeneous integration of the photodetector and the waveguide, the complex three-dimensional structure significantly increases the difficulty of the germanium epitaxial process, mainly in the following aspects:

[0004] 1. The silicon grooves formed by etching usually have a high aspect ratio structure (such as deep trenches or stepped morphology), resulting in irregular surface geometry. The complex surface morphology brings challenges to epitaxial uniformity.

[0005] 2. The exacerbation of lattice mismatch and defect proliferation: After etching to form silicon trenches, the crystal orientations of the trench walls and bottom may be different (such as simultaneously exposing the (100) and (111) crystal planes), resulting in inconsistent growth rates and defect behaviors of germanium epitaxial layers in different regions. Local stress concentration is more severe, which can easily induce crystal defects such as dislocations and stacking faults, which extend upward along the epitaxial layer, significantly reducing the crystal quality of the germanium epitaxial layer and affecting the dark current and response speed of the detector.

[0006] Achieving high crystal quality, high uniformity, and low defect density germanium film growth on non-planar structures is one of the key bottlenecks in the current development of silicon photonics chips towards larger size, higher performance, and higher integration.

[0007] Currently, methods for forming silicon-based germanium epitaxial structures include:

[0008] (a) such as Figure 1 As shown, the dielectric layer 2 and the silicon substrate 1 are etched using an etching process to form a dielectric layer trench 3 and a silicon trench 4. The surface of the silicon trench 4 has residual oxygen plasma defects introduced by the etching process.

[0009] (ii) such as Figure 2As shown, a germanium epitaxial layer 7 is formed in the silicon trench 4, and the germanium epitaxial layer 7 extends into the dielectric layer trench 3.

[0010] like Figure 3 As shown, this is an electron microscope image of the interface region between silicon and germanium at the bottom of the silicon trench after the formation of the germanium epitaxial layer in the prior art. Due to the presence of residual oxygen plasma defects on the surface of the silicon trench, the formation of the germanium epitaxial layer results in an uneven interface between silicon and germanium, which reduces the crystal quality and uniformity of germanium and adversely affects the performance of the photodetector.

[0011] Therefore, how to provide a silicon-based germanium epitaxial structure and its fabrication method to improve the crystal quality and uniformity of the germanium epitaxial layer has become a technical problem that urgently needs to be solved by those skilled in the art.

[0012] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0013] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a silicon-based germanium epitaxial structure and its fabrication method, which solves the problem that the low crystal quality and uniformity of germanium in the prior art have an adverse effect on the performance of photodetectors.

[0014] To achieve the above and other related objectives, the present invention provides a method for fabricating a silicon-based germanium epitaxial structure, comprising the following steps:

[0015] A silicon substrate is provided, a dielectric layer is formed on the silicon substrate, and the dielectric layer and the silicon substrate are etched to form a dielectric layer trench in the dielectric layer and a silicon trench is formed in the silicon substrate below the dielectric layer trench. The surface of the silicon trench has residual oxygen plasma defects introduced by the etching process.

[0016] A germanium sacrificial layer is formed on the surface of the silicon trench, wherein the oxygen plasma residual defects on the surface of the silicon trench are enriched in the germanium sacrificial layer and / or the interface region between the germanium sacrificial layer and the silicon trench;

[0017] HCl gas is introduced into the process chamber to remove the germanium sacrificial layer. During the removal of the germanium sacrificial layer, the oxygen plasma residual defects enriched in the germanium sacrificial layer and / or in the interface region between the germanium sacrificial layer and the silicon trench are also removed.

[0018] A substrate silicon layer is formed on the surface of the silicon groove using a deposition method;

[0019] A germanium epitaxial layer is formed in the silicon trench after the formation of the substrate silicon layer using a selective epitaxial growth method, and the germanium epitaxial layer extends into the dielectric layer trench.

[0020] Optionally, when forming the germanium sacrificial layer, the deposition temperature range is 300~350℃ and the deposition pressure range is 50~100 Torr.

[0021] Optionally, when removing the germanium sacrificial layer, the flow rate of the HCl gas is in the range of 100~200 sccm, the chamber temperature is in the range of 700~750℃, and the chamber pressure is in the range of 100~150 Torr.

[0022] Optionally, when forming the substrate silicon layer, the deposition gas includes SiH4, wherein the flow rate of SiH4 is in the range of 200~300 sccm and the deposition temperature is in the range of 700~750℃.

[0023] Optionally, when forming the substrate silicon layer, the deposition gas includes SiH2Cl2, wherein the flow rate of SiH2Cl2 is in the range of 200~300 sccm and the deposition temperature is in the range of 700~750℃.

[0024] Optionally, the germanium epitaxial layer includes a first germanium epitaxial layer and a second germanium epitaxial layer disposed from bottom to top, and the step of forming the germanium epitaxial layer includes:

[0025] The first germanium epitaxial layer is formed in a temperature range of 300~350℃;

[0026] The structure after the formation of the first germanium epitaxial layer is annealed at a temperature of 350~650℃, wherein the annealing temperature is increased at a preset heating rate during the annealing process.

[0027] The second germanium epitaxial layer is formed in a temperature range of 600~650℃.

[0028] Optionally, the annealing step includes:

[0029] The first stage of annealing is carried out by heating at a rate of 0.5℃ / s during the temperature process of 350~500℃.

[0030] The second stage of annealing is carried out by heating at a rate of 0.3℃ / s during the temperature process of 500~650℃.

[0031] Optionally, before forming the germanium sacrificial layer in the silicon trench, the method further includes a baking step of the structure after forming the silicon trench, wherein the baking temperature ranges from 850 to 950°C and the chamber pressure ranges from 10 to 100 Torr.

[0032] Optionally, after removing the germanium sacrificial layer and before forming the substrate silicon layer, the method further includes a baking step on the structure after removing the germanium sacrificial layer, wherein the baking temperature range is 850~950℃ and the chamber pressure range is 10~100 Torr.

[0033] The present invention also provides a silicon-based germanium epitaxial structure, wherein the silicon-based germanium epitaxial structure is fabricated by the method for fabricating a silicon-based germanium epitaxial structure as described in any one of the preceding claims, comprising:

[0034] A silicon substrate, wherein a dielectric layer is disposed on the silicon substrate;

[0035] A dielectric layer groove is located within the dielectric layer;

[0036] A silicon trench, located in the silicon substrate below the dielectric layer trench;

[0037] A substrate silicon layer is located on the surface of the silicon trench;

[0038] A germanium epitaxial layer is located in the silicon trench and extends into the dielectric layer trench.

[0039] As described above, in the silicon-based germanium epitaxial structure and fabrication method of the present invention, after forming a silicon trench using an etching process, a germanium sacrificial layer is formed on the surface of the silicon trench to absorb residual oxygen plasma defects on the surface of the silicon trench. Then, the germanium sacrificial layer is removed to remove residual oxygen plasma defects. After removing residual oxygen plasma defects, a substrate silicon layer is formed on the surface of the silicon trench using a deposition process. A high-quality substrate silicon layer is used as the substrate for forming the germanium epitaxial layer. That is, this application uses a germanium sacrificial layer to assist in removing residual oxygen plasma defects on the surface of the silicon trench, and uses a deposition process to form a high-quality substrate silicon layer on the surface of the silicon trench, and then forms the germanium epitaxial layer. After forming the germanium epitaxial layer, the interface between silicon and germanium is flat, and the crystal quality and uniformity of germanium are high. Attached Figure Description

[0040] Figure 1 This is a schematic diagram showing the etching of the dielectric layer and silicon substrate in the prior art to form dielectric layer trenches and silicon trenches.

[0041] Figure 2 The diagram shown is a schematic of the formation of a germanium epitaxial layer in the prior art.

[0042] Figure 3 The image shown is an electron microscope image of silicon and germanium at the interface region at the bottom of the silicon trench after the formation of a germanium epitaxial layer in the prior art.

[0043] Figure 4 The diagram shown is a flowchart of the method for fabricating a silicon-based germanium epitaxial structure in an embodiment of the present invention.

[0044] Figure 5The diagram shown is a schematic diagram of the dielectric layer and silicon substrate after etching to form dielectric layer trenches and silicon trenches in an embodiment of the present invention.

[0045] Figure 6 The diagram shown is a schematic diagram of the germanium sacrificial layer after its formation in an embodiment of the present invention.

[0046] Figure 7 The diagram shown is a schematic diagram after the germanium sacrificial layer has been removed in an embodiment of the present invention.

[0047] Figure 8 The diagram shown is a schematic diagram of the silicon substrate layer after it has been formed in an embodiment of the present invention.

[0048] Figure 9 The diagram shown is a schematic diagram of the germanium epitaxial layer formed in an embodiment of the present invention.

[0049] Figure 10 The image shown is an electron microscope image of the germanium epitaxial layer formed in an embodiment of the present invention.

[0050] Figure 11 The image shown is an electron microscope image of silicon and germanium at the interface region at the bottom of the silicon trench after the formation of the germanium epitaxial layer in an embodiment of the present invention.

[0051] Component labeling explanation: 1-Silicon substrate; 2-Dielectric layer; 200-Temperatured silicon oxide layer; 201-Deposited silicon oxide layer; 3-Dielectric layer trench; 4-Silicon trench; 5-Germanium sacrificial layer; 6-Base silicon layer; 7-Germanium epitaxial layer; S1~S5-Steps. Detailed Implementation

[0052] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0054] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0055] In the context of this application, the structure described above the first feature may include embodiments in which the first feature and the second feature are in direct contact, or embodiments in which an additional feature is disposed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact.

[0056] Please see Figures 4 to 11 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0057] This embodiment provides a method for fabricating a silicon-based germanium epitaxial structure. Please refer to [link to relevant documentation]. Figure 4 The flowchart shown is a method for fabricating a silicon-based germanium epitaxial structure according to an embodiment of the present invention, including the following steps:

[0058] S1: A silicon substrate is provided, a dielectric layer is formed on the silicon substrate, and the dielectric layer and the silicon substrate are etched, a dielectric layer trench is formed in the dielectric layer, and a silicon trench is formed in the silicon substrate below the dielectric layer trench, wherein the surface of the silicon trench has oxygen plasma residual defects introduced by the etching process;

[0059] S2: A germanium sacrificial layer is formed on the surface of the silicon trench, wherein the oxygen plasma residual defects on the surface of the silicon trench are enriched in the germanium sacrificial layer and / or the interface region between the germanium sacrificial layer and the silicon trench;

[0060] S3: HCl gas is introduced into the process chamber to remove the germanium sacrificial layer. During the removal of the germanium sacrificial layer, the oxygen plasma residual defects enriched in the germanium sacrificial layer and / or in the interface region between the germanium sacrificial layer and the silicon trench are also removed.

[0061] S4: A substrate silicon layer is formed on the surface of the silicon trench using a deposition method;

[0062] S5: Using selective epitaxial growth, a germanium epitaxial layer is formed in the silicon trench after the formation of the substrate silicon layer, and the germanium epitaxial layer extends into the dielectric layer trench.

[0063] The fabrication method of the silicon-based germanium epitaxial structure in this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0064] First, please refer to Figure 5Step S1: Provide a silicon substrate 1, form a dielectric layer 2 on the silicon substrate 1, and etch the dielectric layer 2 and the silicon substrate 1, form a dielectric layer groove 3 in the dielectric layer 2, and form a silicon groove 4 in the silicon substrate 1 below the dielectric layer groove 3. The surface of the silicon groove 4 has residual oxygen plasma defects introduced by the etching process.

[0065] As an example, in this embodiment, the silicon substrate 1 is the top silicon layer of an SOI (silicon-on-insulator) wafer. The SOI wafer includes a bottom silicon layer, an intermediate buried oxide layer, and a top silicon layer arranged from bottom to top. Using the SOI wafer as the support substrate for the detector, the intermediate buried oxide layer provides good electrical isolation, effectively reducing parasitic capacitance and leakage current between the device and the bottom silicon layer, and improving the response speed and sensitivity of the detector. Furthermore, the SOI wafer supports the integration of various passive devices (such as waveguides, gratings, and couplers) and active devices (such as modulators and detectors) on the same substrate, which is beneficial for realizing complex photonic integrated circuits. In another example, the silicon substrate 1 can also be a silicon wafer, and is not limited to this embodiment.

[0066] As an example, the dielectric layer 2 includes a thermally oxidized silicon oxide layer 200 and a deposited silicon oxide layer 201 disposed from bottom to top. First, a thermal oxidation process is used to oxidize the upper surface of the silicon substrate 1 to form the thermally oxidized silicon oxide layer 200. Then, a high-density plasma chemical vapor deposition process is used to form the deposited silicon oxide layer 201 on the thermally oxidized silicon oxide layer 200. Through thermal oxidation of the upper surface of the silicon substrate 1, the interface state density between the thermally oxidized silicon oxide layer 200 and the silicon substrate 1 is extremely low, significantly reducing dark current (especially edge leakage current) from the interface between the silicon substrate 1 and the thermally oxidized silicon oxide layer 200. Furthermore, the thermally oxidized silicon oxide layer 200 has excellent density, uniformity, and stability, providing a flat and clean platform for the deposited silicon oxide layer 201, thus improving the quality of the deposited silicon oxide layer 201.

[0067] As an example, after forming the deposited silicon oxide layer 201, the dielectric layer trench 3 and the silicon trench 4 are formed using processes such as photolithography and etching. The steps for forming the dielectric layer trench 3 and the silicon trench 4 include:

[0068] (i) A photoresist layer is formed and patterned on the structure after the formation of the deposited silicon oxide layer 201, and the patterned photoresist layer defines the positions of the dielectric layer groove 3 and the silicon groove 4;

[0069] (ii) Using the patterned photoresist layer as a mask, the dielectric layer 2 is etched using a dry etching process to form the dielectric layer groove 3, which penetrates the dielectric layer 2;

[0070] (iii) The silicon substrate 1 is etched using a dry etching process to form the silicon groove 4.

[0071] As an example, oxygen is introduced during the formation of the dielectric layer groove 3 and the silicon groove 4; otherwise, the roughness of the groove sidewalls would be unfavorable. Due to the introduction of oxygen during the etching process, oxygen plasma residue defects will exist on the surface of the silicon groove 4.

[0072] Next, please refer to Figure 6 Step S2: A germanium sacrificial layer 5 is formed on the surface of the silicon groove 4, wherein the oxygen plasma residual defects on the surface of the silicon groove 4 are enriched in the germanium sacrificial layer 5 and / or the interface region between the germanium sacrificial layer 5 and the silicon groove 4.

[0073] As an example, before forming the germanium sacrificial layer 5, a baking step is included on the structure after forming the silicon trench 4 to clean and stabilize the interface and improve the quality of the subsequently formed germanium sacrificial layer 5. During baking, the baking temperature range is 850~950℃ (degrees Celsius), for example, 850℃, 880℃, 900℃, 920℃, 950℃, etc.; the chamber pressure range is 10~100 Torr, for example, 10 Torr, 30 Torr, 50 Torr, 80 Torr, 100 Torr, etc.

[0074] As an example, during the high-temperature baking stage, the residual oxygen plasma defects on the surface of the silicon groove 4 are difficult to remove.

[0075] As an example, in this embodiment, the germanium sacrificial layer 5 is formed using a low-temperature process. If the germanium sacrificial layer 5 is formed using a high-temperature process, the surface migration ability of germanium atoms is stronger in the high-temperature process, and they can easily form three-dimensional islands through long-distance diffusion, resulting in incomplete local coverage.

[0076] As an example, in this embodiment, when forming the germanium sacrificial layer 5, the deposition temperature range is 300~350℃, for example, it can be 300℃, 310℃, 320℃, 330℃, 340℃, 350℃, etc.; the deposition pressure range is 50~100 Torr, for example, it can be 50 Torr, 60 Torr, 70 Torr, 80 Torr, 90 Torr, 100 Torr, etc.

[0077] As an example, in this embodiment, when forming the germanium sacrificial layer 5, the gas used is a germane mixed with hydrogen gas with a mass fraction of 10%. By diluting the germane with hydrogen, the partial pressure of the germane and the surface germanium supply rate are reduced, and parasitic nucleation and gas-phase side reactions on the surface of the medium are suppressed, so that the germanium sacrificial layer 5 is formed only on the surface of the silicon groove 4. The gas flow rate range is 40~120 sccm (standard cubic centimeters per minute), for example, it can be 40 sccm, 60 sccm, 80 sccm, 100 sccm, 120 sccm, etc.

[0078] As an example, the germanium sacrificial layer 5 serves as a sacrificial layer, covering the surface of the silicon trench 4 during the growth process and absorbing the residual oxygen plasma defects on the surface of the silicon trench 4.

[0079] Next, please refer to Figure 7 Step S3: HCl gas is introduced into the process chamber to remove the germanium sacrificial layer 5. During the removal of the germanium sacrificial layer 5, the oxygen plasma residual defects enriched in the germanium sacrificial layer 5 and / or in the interface region between the germanium sacrificial layer 5 and the silicon trench 4 are also removed.

[0080] As an example, after the germanium sacrificial layer 5 is formed, HCl gas is introduced into the process chamber to remove the germanium sacrificial layer 5. When removing the germanium sacrificial layer 5, the flow rate of the HCl gas is in the range of 100~200 sccm, for example, it can be 100 sccm, 120 sccm, 140 sccm, 160 sccm, 180 sccm, 200 sccm, etc.; the chamber temperature is in the range of 700~750℃, for example, it can be 700℃, 710℃, 720℃, 730℃, 740℃, 750℃, etc.; the chamber pressure is in the range of 100~150 Torr, for example, it can be 100 Torr, 110 Torr, 120 Torr, 130 Torr, 140 Torr, 150 Torr, etc.

[0081] As an example, during the removal of the germanium sacrificial layer 5, the oxygen plasma residual defects absorbed and enriched in the germanium sacrificial layer 5 and / or in the interface region between the germanium sacrificial layer 5 and the silicon trench 4 are removed simultaneously.

[0082] As an example, as required, over-etching is performed during the removal of the germanium sacrificial layer 5 to etch the damaged layer on the surface of the silicon trench 4, thereby achieving atomic-level planarization.

[0083] Next, please refer to Figure 8 Step S4: A substrate silicon layer 6 is formed on the surface of the silicon groove 4 using a deposition method.

[0084] As an example, before forming the substrate silicon layer 6, a baking step is included for the structure after removing the germanium sacrificial layer 5 to clean and stabilize the interface, thereby improving the quality of the subsequently formed substrate silicon layer 6. During baking, the baking temperature range is 850~950℃, for example, 850℃, 880℃, 900℃, 920℃, 950℃, etc.; the chamber pressure range is 10~100 Torr, for example, 10 Torr, 30 Torr, 50 Torr, 80 Torr, 100 Torr, etc.

[0085] As an example, in one instance, when forming the substrate silicon layer 6, the deposition gas includes SiH2Cl2, wherein the flow rate of the SiH2Cl2 is in the range of 200~300 sccm, for example, it can be 200 sccm, 220 sccm, 240 sccm, 260 sccm, 280 sccm, 300 sccm, etc.; and the deposition temperature is in the range of 700~750℃, for example, it can be 700℃, 710℃, 720℃, 730℃, 740℃, 750℃, etc. In another example, when forming the substrate silicon layer 6, the deposition gas includes SiH4, wherein the flow rate of the SiH4 is in the range of 200~300 sccm, for example, it can be 200 sccm, 220 sccm, 240 sccm, 260 sccm, 280 sccm, 300 sccm, etc.; the deposition temperature is in the range of 700~750℃, for example, it can be 700℃, 710℃, 720℃, 730℃, 740℃, 750℃, etc.

[0086] As an example, the substrate silicon layer 6 is formed by a deposition process, and the substrate silicon layer 6 does not undergo an etching process, that is, the substrate silicon layer 6 has good quality. Using the high-quality substrate silicon layer 6 as the substrate for the subsequent formation of the germanium epitaxial layer 7 can improve the quality of the germanium epitaxial layer 7.

[0087] As an example, when forming the substrate silicon layer 6, a high flow rate of silicon source gas is used to induce local silicon deposition or redistribution, which can repair the tip edge of the silicon groove 4 to smooth the groove corner.

[0088] Next, please refer to Figure 9 Step S5: Using selective epitaxial growth, a germanium epitaxial layer 7 is formed in the silicon trench 4 after the formation of the substrate silicon layer 6, and the germanium epitaxial layer 7 extends into the dielectric layer trench 3.

[0089] As an example, the germanium epitaxial layer 7 includes a first germanium epitaxial layer and a second germanium epitaxial layer disposed from bottom to top, and the steps for forming the germanium epitaxial layer 7 include:

[0090] (i) The first germanium epitaxial layer is formed in a temperature range of 300~350℃, that is, the first germanium epitaxial layer is a germanium epitaxial layer formed by a low temperature process; when forming the first germanium epitaxial layer, the deposition temperature can be 300℃, 310℃, 320℃, 330℃, 340℃, 350℃, etc.; the chamber pressure range is 40~60 Torr, for example, it can be 40 Torr, 50 Torr, 60 Torr, etc.; the first germanium epitaxial layer serves as a low temperature nucleation layer, by reducing the reaction temperature, an ultrathin germanium layer is deposited on the substrate silicon layer 6, the surface diffusion is suppressed at low temperature, a high density of nucleation points is formed, the growth of three-dimensional islands is reduced, and the lattice stress is partially released through dislocation slip.

[0091] (ii) The structure after the formation of the first germanium epitaxial layer is annealed at a temperature of 350~650℃. During the annealing process, the annealing temperature is increased at a preset heating rate. In this embodiment, the annealing of the structure after the formation of the first germanium epitaxial layer includes a first-stage annealing and a second-stage annealing. During the first-stage annealing, the temperature is increased from 350℃ to 500℃ at a heating rate of 0.5℃ / s. During the second-stage annealing, the temperature is increased from 500℃ to 650℃ at a heating rate of 0.3℃ / s. The two-stage annealing is carried out by first using a high heating rate and then using a low heating rate. On the one hand, the capacity of the machine itself is limited to prevent temperature overshoot during the heating process of 500~650℃. On the other hand, the temperature of the high-temperature range of 500~650℃ is relatively high and needs to be more gradual than the heating process of the low-temperature range of 350~500℃ to prevent defects in the process from quickly penetrating to the top layer, thereby ensuring the crystal quality.

[0092] (iii) The second germanium epitaxial layer is formed in the temperature range of 600~650℃, that is, the second germanium epitaxial layer is a germanium epitaxial layer formed by high temperature process; when forming the second germanium epitaxial layer, the deposition temperature can be 600℃, 610℃, 620℃, 630℃, 640℃, 650℃, etc.; the chamber pressure range is 40~60 Torr, for example, it can be 40 Torr, 50 Torr, 60 Torr, etc.; the second germanium epitaxial layer is a high temperature epitaxial layer, which enhances atomic mobility and promotes lattice order arrangement through high temperature growth, achieves strain relaxation through dislocation interaction, and reduces defect density.

[0093] As an example, during the formation of the germanium epitaxial layer 7, as the thickness of the germanium epitaxial layer 7 increases, the germanium epitaxial layer 7 extends into the dielectric layer groove 3.

[0094] As an example, after forming the second germanium epitaxial layer, a high-temperature annealing step is also included; the annealing temperature range is 750~850℃, for example, it can be 750℃, 780℃, 800℃, 820℃, 850℃, etc.; the chamber pressure range is 40~60 Torr, for example, it can be 40 Torr, 50 Torr, 60 Torr, etc.; through high-temperature annealing, the density of penetrating dislocations in the germanium epitaxial layer 7 is reduced and residual stress is further released.

[0095] For example, please refer to Figure 10 The image shown is an electron microscope image of the germanium epitaxial layer formed in an embodiment of the present invention; please refer to [link / reference]. Figure 11 The image shown is an electron microscope (EM) image of the interface region between silicon and germanium at the bottom of the silicon trench after the formation of the germanium epitaxial layer in this embodiment of the invention. In this embodiment, after the formation of the germanium epitaxial layer 7, the interface between silicon and germanium is smooth, indicating high crystal quality and uniformity of germanium.

[0096] Thus, a silicon-based germanium epitaxial structure is obtained, comprising a silicon substrate 1, a dielectric layer groove 3, a silicon groove 4, a base silicon layer 6, and a germanium epitaxial layer 7; the silicon substrate 1 is provided with a dielectric layer 2; the dielectric layer groove 3 is located in the dielectric layer 2; the silicon groove 4 is located in the silicon substrate 1 below the dielectric layer groove 3; the base silicon layer 6 is located on the surface of the silicon groove 4; and the germanium epitaxial layer 7 is located in the silicon groove 4 and extends into the dielectric layer groove 3.

[0097] As an example, in this embodiment, the silicon substrate 1 is the top silicon layer of an SOI (silicon-on-insulator) wafer. The SOI wafer includes a bottom silicon layer, an intermediate buried oxide layer, and a top silicon layer arranged from bottom to top. Using the SOI wafer as the support substrate for the detector, the intermediate buried oxide layer provides good electrical isolation, effectively reducing parasitic capacitance and leakage current between the device and the bottom silicon layer, and improving the response speed and sensitivity of the detector. Furthermore, the SOI wafer supports the integration of various passive devices (such as waveguides, gratings, and couplers) and active devices (such as modulators and detectors) on the same substrate, which is beneficial for realizing complex photonic integrated circuits. In another example, the silicon substrate 1 can also be a silicon wafer, and is not limited to this embodiment.

[0098] As an example, the dielectric layer 2 includes a thermally oxidized silicon oxide layer 200 and a deposited silicon oxide layer 201 disposed from bottom to top. The thermally oxidized silicon oxide layer 200 is formed by thermal oxidation of the upper surface of the silicon substrate 1, and the deposited silicon oxide layer 201 is formed using a high-density plasma chemical vapor deposition process. Through thermal oxidation of the upper surface of the silicon substrate 1, the interface state density between the thermally oxidized silicon oxide layer 200 and the silicon substrate 1 is extremely low, significantly reducing dark current (especially edge leakage current) from the interface between the silicon substrate 1 and the thermally oxidized silicon oxide layer 200. Furthermore, the thermally oxidized silicon oxide layer 200 exhibits excellent density, uniformity, and stability, providing a flat and clean platform for the deposited silicon oxide layer 201, thereby improving the quality of the deposited silicon oxide layer 201.

[0099] As an example, the dielectric layer groove 3 and the silicon groove 4 are formed using processes such as photolithography and etching.

[0100] As an example, the substrate silicon layer 6 is formed by a deposition process and does not undergo an etching process, that is, the substrate silicon layer 6 has good quality. Using the high-quality substrate silicon layer 6 as the substrate for forming the germanium epitaxial layer 7 can improve the quality of the germanium epitaxial layer 7.

[0101] As an example, the silicon source for forming the substrate silicon layer 6 is SiH2Cl2 or SiH4.

[0102] In summary, in the silicon-based germanium epitaxial structure and fabrication method of the present invention, after forming a silicon trench using an etching process, a germanium sacrificial layer is formed on the surface of the silicon trench to absorb residual oxygen plasma defects on the surface of the silicon trench. Then, the germanium sacrificial layer is removed to remove the residual oxygen plasma defects. After removing the residual oxygen plasma defects, a substrate silicon layer is formed on the surface of the silicon trench using a deposition process. This high-quality substrate silicon layer serves as the substrate for forming the germanium epitaxial layer. That is, this application uses a germanium sacrificial layer to assist in removing residual oxygen plasma defects on the surface of the silicon trench, and uses a deposition process to form a high-quality substrate silicon layer on the surface of the silicon trench before forming the germanium epitaxial layer. After forming the germanium epitaxial layer, the interface between silicon and germanium is smooth, and the crystal quality and uniformity of germanium are high. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0103] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a silicon-based germanium epitaxial structure, characterized in that, Includes the following steps: A silicon substrate is provided, a dielectric layer is formed on the silicon substrate, and the dielectric layer and the silicon substrate are etched to form a dielectric layer trench in the dielectric layer and a silicon trench is formed in the silicon substrate below the dielectric layer trench. The surface of the silicon trench has residual oxygen plasma defects introduced by the etching process. A germanium sacrificial layer is formed on the surface of the silicon trench, wherein the oxygen plasma residual defects on the surface of the silicon trench are enriched in the germanium sacrificial layer and / or the interface region between the germanium sacrificial layer and the silicon trench; HCl gas is introduced into the process chamber to remove the germanium sacrificial layer. During the removal of the germanium sacrificial layer, the oxygen plasma residual defects enriched in the germanium sacrificial layer and / or in the interface region between the germanium sacrificial layer and the silicon trench are also removed. A substrate silicon layer is formed on the surface of the silicon groove using a deposition method; A germanium epitaxial layer is formed in the silicon trench after the formation of the substrate silicon layer using a selective epitaxial growth method, and the germanium epitaxial layer extends into the dielectric layer trench.

2. The method for fabricating a silicon-based germanium epitaxial structure according to claim 1, characterized in that: When forming the germanium sacrificial layer, the deposition temperature range is 300~350℃ and the deposition pressure range is 50~100 Torr.

3. The method for fabricating a silicon-based germanium epitaxial structure according to claim 1, characterized in that: When removing the germanium sacrificial layer, the flow rate of the HCl gas is in the range of 100~200 sccm, the chamber temperature is in the range of 700~750℃, and the chamber pressure is in the range of 100~150 Torr.

4. The method for fabricating a silicon-based germanium epitaxial structure according to claim 1, characterized in that: When forming the substrate silicon layer, the deposition gas includes SiH4, wherein the flow rate of SiH4 is in the range of 200~300 sccm and the deposition temperature is in the range of 700~750℃.

5. The method for fabricating a silicon-based germanium epitaxial structure according to claim 1, characterized in that: When forming the substrate silicon layer, the deposition gas includes SiH2Cl2, wherein the flow rate of SiH2Cl2 is in the range of 200~300 sccm and the deposition temperature is in the range of 700~750℃.

6. The method for fabricating a silicon-based germanium epitaxial structure according to claim 1, characterized in that, The germanium epitaxial layer includes a first germanium epitaxial layer and a second germanium epitaxial layer disposed from bottom to top, and the steps for forming the germanium epitaxial layer include: The first germanium epitaxial layer is formed in a temperature range of 300~350℃; The structure after the formation of the first germanium epitaxial layer is annealed at a temperature of 350~650℃, wherein the annealing temperature is increased at a preset heating rate during the annealing process. The second germanium epitaxial layer is formed in a temperature range of 600~650℃.

7. The method for fabricating a silicon-based germanium epitaxial structure according to claim 6, characterized in that, The annealing step includes: The first stage of annealing is carried out by heating at a rate of 0.5℃ / s during the temperature process of 350~500℃. The second stage of annealing is carried out by heating at a rate of 0.3℃ / s during the temperature process of 500~650℃.

8. The method for fabricating a silicon-based germanium epitaxial structure according to claim 1, characterized in that: Before forming the germanium sacrificial layer in the silicon trench, the method further includes a baking step of the structure after forming the silicon trench, wherein the baking temperature range is 850~950℃ and the chamber pressure range is 10~100 Torr.

9. The method for fabricating a silicon-based germanium epitaxial structure according to claim 1, characterized in that: After removing the germanium sacrificial layer and before forming the substrate silicon layer, the process further includes a baking step on the structure after removing the germanium sacrificial layer, wherein the baking temperature range is 850~950℃ and the chamber pressure range is 10~100 Torr.

10. A silicon-based germanium epitaxial structure, characterized in that, The silicon-based germanium epitaxial structure is fabricated by the method for fabricating a silicon-based germanium epitaxial structure according to any one of claims 1 to 9, comprising: A silicon substrate, wherein a dielectric layer is disposed on the silicon substrate; A dielectric layer groove is located within the dielectric layer; A silicon trench, located in the silicon substrate below the dielectric layer trench; A substrate silicon layer is located on the surface of the silicon trench; A germanium epitaxial layer is located in the silicon trench and extends into the dielectric layer trench.

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