Chip packaging structure and preparation method of chip packaging structure
By using an alternating stacking structure of glass core layers and interconnect sublayers, high interconnect density chip packaging is achieved, solving the problems of signal integrity and space utilization, reducing signal loss and latency, and simplifying the manufacturing process.
Patent Information
- Application Number
- CN202611269568.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-20
- Publication Date
- 2026-11-03
AI Technical Summary
Existing co-packaging optical technologies struggle to achieve high interconnect density chip packaging while ensuring signal integrity. Silicon-based materials suffer from signal loss and process complexity issues, while organic materials face challenges related to thermal mismatch and limited interconnect density.
The alternating stacking structure of glass core layer and connector sublayer is adopted, and vertical interconnection is achieved by using glass substrate and conductive pillars. Combined with the design of wiring layer and chip layer, a vertical interconnection channel is formed, which shortens the signal transmission path and improves space utilization.
It achieves high interconnect density chip packaging, reduces signal loss and latency, improves space utilization and packaging structure reliability, and simplifies manufacturing processes.
Smart Images
Figure CN123035974A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor packaging technology, and more specifically, to a chip packaging structure and a method for preparing the chip packaging structure. Background Technology
[0002] With the increasing demands for bandwidth and computing power from artificial intelligence, high-performance computing, and data centers, the requirements for the speed and density of electrical signal transmission between chip packaging structures and between chips and external systems are becoming increasingly stringent. Co-Packaged Optics (CPO) technology packages optical engines (including photonic integrated circuits (PICs) and electronic integrated circuits (EICs)) and the main control chip (ASIC) onto the same substrate to reduce signal attenuation, transmission latency, and power consumption. However, current co-packaged optics packaging methods have structural limitations, making it difficult to achieve high interconnect density requirements while ensuring signal integrity. Summary of the Invention
[0003] To overcome the technical problems mentioned in the background, this application provides a chip packaging structure, which includes: A glass core layer includes multiple glass core sub-layers and multiple connecting sub-layers stacked sequentially. At least some of the connecting sub-layers are located between adjacent glass core sub-layers. Each glass core sub-layer includes a glass substrate, a first conductive via penetrating the glass substrate, and a first conductive post filling the first conductive via. Each connecting sub-layer includes a first connecting sub-layer body, a second conductive via penetrating the first connecting sub-layer body, and a second conductive post filling the second conductive via. The first conductive posts of adjacent glass core sub-layers are electrically connected through the second conductive posts of the connecting sub-layers. Any layer of the glass substrate includes at least one substrate opening penetrating the glass substrate. At least one first chip of different types is disposed in the substrate opening. The first chip is electrically connected to the first conductive post of the glass core sub-layer adjacent to the first chip through the second conductive post. Alternatively, multiple adjacent layers of glass substrates each include a substrate opening penetrating the glass substrate, and the substrate openings of adjacent layers of glass substrates overlap. At least one first chip of different types is disposed in the substrate opening, and the first chips are electrically connected to each other through the second conductive post. The wiring layer includes a first wiring layer and a second wiring layer, the first wiring layer and the second wiring layer are located on opposite sides of the glass core layer, and the wiring of the first wiring layer and the wiring of the second wiring layer are electrically connected to the first conductive post of the glass core layer. A chip layer is located on the side of the first wiring layer away from the glass core layer. The chip layer includes at least one second chip and a packaging layer surrounding the second chip. The second chip is electrically connected to the wiring of the first wiring layer.
[0004] In one possible implementation, the first conductive post of the glass core sublayer is correspondingly provided, and the second conductive post connecting the sublayer is also correspondingly provided with the first conductive post of the glass core sublayer. The first chip includes chip pins arranged at intervals, and the chip pins are also correspondingly arranged with the second conductive post.
[0005] In one possible implementation, the connection sublayer further includes a second connection sublayer body disposed around the first chip.
[0006] The materials of the first connecting sublayer body and the second connecting sublayer body include thermally conductive materials.
[0007] In one possible implementation, the glass core sublayer includes a first glass core sublayer, a second glass core sublayer, and a third glass core sublayer stacked sequentially, and the connecting sublayer includes a first connecting sublayer, a second connecting sublayer, and a third connecting sublayer. The first connecting sublayer body of the first connecting sublayer is located between the first glass core sublayer and the second glass core sublayer, the first connecting sublayer body of the second connecting sublayer is located between the second glass core sublayer and the third glass core sublayer, and the first connecting sublayer body of the third connecting sublayer is located between the third glass core sublayer and the first wiring layer. The glass substrate of the second glass core layer includes a first substrate opening and a second substrate opening, and the glass substrate of the third glass core layer includes a third substrate opening, wherein the second substrate opening and the third substrate opening are overlapped. The first chip includes a first sub-chip, a second sub-chip, and a third sub-chip of different types. The first sub-chip is disposed in the opening of the first substrate. The chip pins of the first sub-chip are electrically connected to the first conductive post of the first glass core layer and the first conductive post of the third glass core layer through the second conductive post of the first connecting sub-layer and the second conductive post of the second connecting sub-layer, respectively. The second sub-chip is disposed in the opening of the second substrate, and the third sub-chip is disposed in the opening of the third substrate. The chip pins on one side of the second sub-chip are electrically connected to the first conductive post of the first glass core layer through the second conductive post of the first connecting sub-layer, and the chip pins on the other side of the second sub-chip are electrically connected to the chip pins of the third sub-chip through the second conductive post of the second connecting sub-layer.
[0008] In one possible implementation, the first sub-chip includes a bridging chip, the second sub-chip includes an electrical chip, and the third sub-chip includes a fiber array chip. The second chip includes a switching chip or a memory chip.
[0009] In one possible implementation, the coefficients of thermal expansion of the glass substrates of at least some of the glass core sublayers are different.
[0010] In one possible implementation, the glass core layer further includes at least one dielectric sublayer located between adjacent glass core layers; The dielectric sublayer includes a dielectric sublayer body and a third conductive post penetrating the dielectric sublayer body. The third conductive post of the dielectric sublayer is electrically connected to the first conductive post of the glass core sublayer through the second conductive post of the connecting sublayer. The material of the dielectric sublayer body includes semiconductor materials or organic materials, and the semiconductor material includes silicon.
[0011] This application also provides a method for fabricating a chip packaging structure, the method comprising: A glass core layer is fabricated, wherein the glass core layer comprises a plurality of glass core sub-layers and a plurality of connecting sub-layers stacked sequentially, at least some of the connecting sub-layers being located between adjacent glass core sub-layers. Each glass core sub-layer includes a glass substrate, a first conductive via penetrating the glass substrate, and a first conductive post filling the first conductive via. Each connecting sub-layer includes a first connecting sub-layer body, a second conductive via penetrating the first connecting sub-layer body, and a second conductive post filling the second conductive via. The first conductive posts of adjacent glass core sub-layers are electrically connected through the second conductive posts of the connecting sub-layers. Any layer of the glass substrate includes at least one substrate opening penetrating the glass substrate, and at least one first chip of different types is disposed within the substrate opening. The first chip is electrically connected to the first conductive post of the adjacent glass core sub-layer through the second conductive post. Alternatively, adjacent layers of glass substrates each include substrate openings penetrating the glass substrate, and the substrate openings of adjacent layers of glass substrates overlap. At least one first chip of different types is disposed within the substrate opening, and the first chips are electrically connected to each other through the second conductive post. A first wiring layer and a second wiring layer are respectively fabricated on opposite sides of the glass core layer, wherein the wiring of the first wiring layer and the wiring of the second wiring layer are electrically connected to the first conductive post of the glass core layer. A chip layer is fabricated on the side of the first wiring layer away from the glass core layer, wherein the chip layer includes at least one second chip and an encapsulation layer surrounding the second chip, and the second chip is electrically connected to the wiring of the first wiring layer.
[0012] In one possible implementation, the step of fabricating the glass core layer includes: Provide a first glass core layer; A first connecting sublayer is formed on one side of the first glass core sublayer, wherein the first conductive post of the first glass core sublayer is correspondingly and electrically connected to the second conductive post of the first connecting sublayer. A second glass core layer is formed on the side of the first connecting sublayer away from the first glass core layer, wherein the first conductive post of the second glass core layer is electrically connected to the first conductive post of the first glass core layer through the second conductive post of the first connecting sublayer, and the glass substrate of the second glass core layer includes a first substrate opening and a second substrate opening. The first sub-chip and the second sub-chip are respectively disposed in the first substrate opening and the second substrate opening, wherein the first sub-chip and the second sub-chip are electrically connected to the first conductive post of the first glass core plate sub-layer through the second conductive post of the first connecting sub-layer. A second connection sublayer is formed on the side of the second glass core sublayer away from the first glass core sublayer, wherein the second connection sublayer includes a second connection sublayer filling around the first sub-chip and the second sub-chip; A third glass core layer is fabricated on the side of the second connecting sublayer away from the first glass core layer. The first conductive post of the third glass core layer is electrically connected to the first conductive post of the second glass core layer through the second conductive post of the second connecting sublayer. The glass substrate of the third glass core layer includes a third substrate opening, which overlaps with the second substrate opening. A third sub-chip is disposed in the opening of the third substrate, wherein the third sub-chip is electrically connected to the first conductive post of the second glass core plate sub-layer through the second conductive post of the second connecting sub-layer, and the third sub-chip, the second sub-chip, and the first sub-chip are of different types; A third connecting sublayer is formed on the side of the third glass core sublayer away from the first glass core sublayer, wherein the third connecting sublayer includes a third connecting sublayer filling around the third subchip.
[0013] In one possible implementation, prior to the step of fabricating the glass core layer, the method further includes: Provide a glass substrate; A first substrate opening and a second substrate opening are fabricated that penetrate the glass substrate. A first conductive via is fabricated through the glass substrate to obtain a patterned glass substrate. The step of fabricating a second glass core layer on the side of the first connecting sublayer away from the first glass core layer includes: The patterned glass substrate is bonded to the side of the first connecting sublayer away from the first glass core sublayer. The first conductive pillar is formed within the first conductive through-hole to obtain the second glass core layer.
[0014] Based on any of the above aspects, embodiments of this application provide a chip packaging structure and a method for fabricating the chip packaging structure. The chip packaging structure includes a glass core layer, a wiring layer, and a chip layer. The glass core layer includes a glass core sublayer and a connecting sublayer. Any glass substrate includes a substrate opening penetrating the glass substrate, or adjacent multiple glass substrates each include substrate openings, and the substrate openings overlap. At least one first chip is disposed within the substrate opening. The first chip is electrically connected to a first conductive post of the glass core sublayer adjacent to the first chip via a second conductive post, or the first chips are electrically connected to each other via second conductive posts. The wiring layer is located on opposite sides of the glass core layer, and the chip layer is located on the side of the first wiring layer away from the glass core layer. The chip layer includes at least one second chip and a packaging layer surrounding the second chip. The second chip is electrically connected to the wiring of the first wiring layer. The above structure utilizes the alternating stacking of glass core sublayers and connecting sublayers to form a vertical interconnect channel, and places some components (such as the first chip) between the glass core sublayers, thereby effectively shortening the signal transmission path between chips, reducing transmission loss, and achieving high interconnect density packaging while ensuring signal integrity. Attached Figure Description
[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a schematic diagram of a chip packaging structure provided in this embodiment; Figure 2 This is a schematic flowchart of a chip packaging structure fabrication method provided in this embodiment; Figure 3 for Figure 2 Corresponding process flow chart; Figure 4 for Figure 1 A flowchart of the sub-steps corresponding to step S11; Figure 5a and Figure 5b for Figure 4 Corresponding process flow chart; Figure 6 This is the process diagram corresponding to sub-step S112 provided in this embodiment.
[0017] Icons: Chip Packaging Structure - 1; Glass Core Layer - 10; Glass Core Sublayer - 100; Glass Substrate - 1001; First Conductive Via - 1002; First Conductive Pillar - 1003; First Glass Core Sublayer - 1004; Second Glass Core Sublayer - 1005; Third Glass Core Sublayer - 1006; First Substrate Opening - 1001a; Second Substrate Opening - 1001b; Third Substrate Opening - 1001c; Connector Sublayer - 101; First Connector Sublayer Body - 1011; Second Conductor... Through-hole - 1012; Second conductive post - 1013; Second connection sub-layer body - 1014; First connection sub-layer - 1015; Second connection sub-layer - 1016; Third connection sub-layer - 1017; Routing layer - 11; First routing layer - 110; Second routing layer - 111; Chip layer - 12; Second chip - 120; Package layer - 121; First chip - 102; Chip pin - 1020; First sub-chip - 102a; Second sub-chip - 102b; Third sub-chip - 102c. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0021] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0022] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.
[0023] The inventors discovered through research that with the continuous growth in bandwidth and computing power demands from artificial intelligence, high-performance computing, and data centers, the requirements for the speed and density of electrical signal transmission between chips and between chips and external systems are increasing daily. Co-Packaged Optics (CPO) technology packages an optical engine (including a photonic integrated circuit (PIC) and an electronic integrated circuit (EIC)) and a main control chip (ASIC) onto the same substrate to reduce signal attenuation, transmission latency, and power consumption. However, current chip packaging methods for co-packaged optics have structural limitations, making it difficult to achieve high interconnect density requirements while ensuring signal integrity.
[0024] Specifically, current co-packaged optical integrated structures typically integrate multiple chips on an interposer layer, which is either silicon-based (e.g., TSV silicon interposer) or organic (e.g., organic materials). On the one hand, when using silicon-based materials for the interposer, firstly, as a semiconductor material, silicon contains freely moving charges, leading to significant losses and crosstalk in high-frequency signals within vertical conduction structures (e.g., TSV structures), thus limiting signal integrity. Secondly, silicon-based materials are complex and costly to integrate passive components or optical devices, and their compatibility with other packaging materials such as glass and polymers is poor, further limiting the interconnect density and integration flexibility of the integrated structure. Furthermore, silicon-based materials have low utilization rates in large-size packaging scenarios, making large-scale panel-level manufacturing difficult.
[0025] On the other hand, when using organic materials in the interposer, firstly, the coefficient of thermal expansion of organic materials differs significantly from that of silicon chips. Under temperature changes and large-size packaging conditions, thermal mismatch stress between materials can lead to warping, which in turn affects the alignment accuracy and packaging yield of subsequent processes. Secondly, the linewidth / spacing of organic materials is limited by material properties and manufacturing processes, making it difficult to meet the requirements of high interconnect density.
[0026] Therefore, how to achieve a co-packaged optical integration structure with higher interconnect density while ensuring signal integrity has become a technical problem that urgently needs to be solved by those skilled in the art.
[0027] In order to solve the aforementioned technical problems, the inventors have innovatively designed the following technical solutions, and the specific implementation scheme of this application will be described in detail below with reference to the accompanying drawings.
[0028] Please see Figure 1 , Figure 1 This is a schematic diagram of a chip packaging structure 1 provided in this embodiment. The chip packaging structure 1 includes a glass core layer 10, a wiring layer 11, and a chip layer 12. The glass core layer 10 includes a plurality of glass core sub-layers 100 and a plurality of connecting sub-layers 101 stacked sequentially. At least some of the connecting sub-layers 101 are located between adjacent glass core sub-layers 100. The glass core sub-layer 100 includes a glass substrate 1001, a first conductive via 1002 penetrating the glass substrate 1001, and a first conductive post 1003 filled in the first conductive via 1002. The connecting sub-layer 101 includes a first connecting sub-layer body 1011, a second conductive via 1012 penetrating the first connecting sub-layer body 1011, and a second conductive post 1013 filled in the second conductive via 1012. The first conductive posts 1013 of adjacent glass core sub-layers 100 are connected between adjacent glass core sub-layers 100. 003 is electrically connected through the second conductive post 1013 of the connecting sublayer 101. Any layer of glass substrate 1001 includes at least one substrate opening penetrating the glass substrate 1001 (e.g., first substrate opening 1001a, second substrate opening 1001b and third substrate opening 1001c). At least one type of first chip 102 is disposed in the substrate opening. The first chip 102 is electrically connected to the first conductive post 1003 of the glass core sublayer 100 adjacent to the first chip 102 through the second conductive post 1013. Alternatively, adjacent multilayer glass substrates 1001 respectively include substrate openings penetrating the glass substrate 1001, and the substrate openings of adjacent multilayer glass substrates 1001 are overlapped. At least one type of first chip 102 is disposed in the substrate opening. The first chips 102 are electrically connected to each other through the second conductive post 1013. The wiring layer 11 includes a first wiring layer 110 and a second wiring layer 111, which are located on opposite sides of the glass core layer 10. The traces of the first wiring layer 110 and the traces of the second wiring layer 111 are electrically connected to the first conductive post 1003 of the glass core layer 10. The chip layer 12 is located on the side of the first wiring layer 110 away from the glass core layer 10. The chip layer 12 includes at least one second chip 120 and an encapsulation layer 121 surrounding the second chip 120. The second chip 120 is electrically connected to the traces of the first wiring layer 110.
[0029] In this embodiment, the glass core layer 10 serves as the core supporting foundation of the chip packaging structure 1, responsible for vertical interconnection and chip embedding. The wiring layer 11 is responsible for horizontal signal fan-out and interlayer connections. The chip package is used to place the main control chip, thus forming a complete stacked chip packaging structure 1. It is understood that this embodiment does not specifically limit the number of glass core sub-layers 100; it can include two, three, or four glass core sub-layers 100. Correspondingly, the number of connecting sub-layers 101 can be adjusted according to actual needs. Each layer of the glass core layer 10 can be entirely composed of glass core sub-layers 100, or one or more layers can be set as dielectric layers. For example, the dielectric layer can be formed of semiconductor materials or organic materials. The connecting sub-layers 101 serve as adhesive and interconnect layers, and can be located between adjacent glass core sub-layers 100, between adjacent glass core sub-layers 100 and dielectric sub-layers, between adjacent dielectric sub-layers, or between glass core sub-layers 100 and wiring layers 11. Furthermore, according to process requirements, redistribution layers can be added between adjacent glass core sub-layers 100 to achieve horizontal interconnection between layers. Specifically, when fabricating a connecting sub-layer 101 on a certain glass core sub-layer 100, a redistribution layer can be fabricated, and then another glass core sub-layer 100 can be fabricated on the redistribution layer for insulation. When fabricating this connecting sub-layer 101, a dry film with a relatively soft material and high plasticity can be used to create openings.
[0030] In this embodiment, the glass core layer 100 uses a glass substrate 1001 as the main structure and insulating medium. The glass substrate 1001 is made of glass, which is a good insulating material and will not generate substrate loss or signal crosstalk when high-frequency signals pass through. The first conductive via 1002 is used to provide an electrical channel, and the first conductive post 1003 filled in the first conductive via 1002 is the actual electrical channel. The first conductive post 1003 can be made of conductive metal materials such as copper or silver, or conductive composite materials such as conductive paste (e.g., copper paste, silver paste). Specifically, when solid copper is used as the material of the first conductive post 1003, the first conductive post 1003 not only serves as an electrical channel, but also as a heat conduction channel, efficiently conducting the heat generated by the first chip 102 in the vertical direction to the wiring layer 11 or an external heat sink, thus helping to improve the heat dissipation performance of the chip packaging structure 1. The connecting sublayer 101 can be made of insulating material (such as dry film, polyimide PI, or other organic dielectric materials). The second conductive post 1013 penetrates the entire first connecting sublayer body 1011, providing a vertical electrical path. The second conductive post 1013, filled in the second conductive through-hole 1012, cooperates with the first conductive through-hole 1002 to achieve a vertical electrical connection between two adjacent glass core sublayers 100. Specifically, the first conductive post 1003 of the upper glass core sublayer 100 is vertically connected to the first conductive post 1003 of the lower glass core sublayer 100 through the second conductive post 1013 of the connecting sublayer 101. In this way, the signal can be transmitted from one layer to the next, forming a vertical conductive path that penetrates the entire glass core layer 10.
[0031] Furthermore, components are mounted on the glass core layer 100 by setting substrate openings. Specifically, one or more substrate openings can be formed in a single glass substrate 1001, penetrating the single glass substrate 1001. The substrate openings of adjacent multi-layer glass substrates 1001 can overlap. When the substrate openings of adjacent multi-layer glass substrates 1001 overlap, different types of first chips 102 within the substrate openings are interconnected through connecting sub-layers 101 between the glass substrates 1001. Different types of first chips 102, capacitors, inductors, and other components can be mounted in different substrate openings as needed. For example, first chips 102 such as electrical chips and fiber optic array chips can be respectively mounted in the overlapping substrate openings of multiple adjacent glass substrates 1001. The two can be vertically interconnected through the second conductive post 1013 between them, significantly reducing signal loss and delay.
[0032] In the above scheme, the chip packaging structure 1, through the alternating stacking method, provides more wiring resources and chip housing space in the vertical direction, thereby achieving a high interconnection density. Furthermore, signals can be directly transmitted via the shortest path through vertical interconnection, significantly reducing signal loss and latency. Moreover, in this embodiment, components are directly embedded in the substrate through-holes in the glass core layer 10, eliminating the need for other space, significantly improving the space utilization of the chip packaging structure 1 and helping to reduce its volume.
[0033] In this embodiment, the wiring layer 11 is a horizontal interconnect layer of the chip package structure 1. The wiring layer 11 can be a redistribution layer. The wiring layer 11 is set on both sides of the glass core layer 10. The design of the double-sided wiring layer 11 provides more wiring resources, increases the fan-out density, and further improves the interconnection density of the chip package structure 1.
[0034] It is worth noting that conductive balls can be placed on the side of the second wiring layer 111 away from the glass core layer 10, such as... Figure 1 As shown.
[0035] Furthermore, please see again Figure 1 In this embodiment, the first conductive post 1003 of the glass core substrate sublayer 100 is correspondingly disposed, and the second conductive post 1013 connecting the sublayer 101 is also correspondingly disposed with the first conductive post 1003 of the glass core substrate sublayer. The first chip 102 includes chip pins 1020 arranged at intervals, and the chip pins 1020 are also correspondingly disposed with the second conductive post 1013. Thus, in the vertical direction, the first conductive post 1003, the second conductive post 1013, and the chip pins 1020 used for electrical interconnection are all connected one-to-one, ensuring that the signal is transmitted vertically without deviation, eliminating the need for horizontal bending of the traces, significantly shortening the signal transmission path, reducing signal loss and signal delay, and ensuring signal integrity. Furthermore, the aligned structural design simplifies the manufacturing process and ensures the reliability of the chip packaging structure 1 manufacturing.
[0036] Furthermore, please see again Figure 1 The connecting sublayer 101 also includes a second connecting sublayer body 1014, which is disposed around the first chip 102. In this embodiment, the second connecting sublayer body 1014 of the connecting sublayer 101 fills the area around the first chip 102, that is, fills the substrate groove formed by the substrate opening and the adjacent connecting sublayer 101, to provide mechanical protection and stress buffer for the components in the substrate through-hole, while the first connecting sublayer body 101 is located at least between adjacent glass core sublayers 100, serving as structural support and electrical isolation.
[0037] Because the first chip 102 in the chip package structure 1 generates heat during operation, if this heat cannot be dissipated, the chip junction temperature will rise. In this embodiment, the first connecting sublayer body 1011 and the second connecting sublayer body 1014 are made of thermally conductive materials. The second connecting sublayer body 1014 is in close contact with the periphery of the chip, allowing it to quickly conduct the heat generated by the chip horizontally to the connecting sublayer 101, and then vertically to the outside through the first conductive pillar 1003. In this way, an internal heat dissipation path is formed in the chip package structure 1, solving the problem of heat accumulation in 3D stacking.
[0038] Furthermore, please see again Figure 1 The glass core sublayer 100 includes a first glass core sublayer 1004, a second glass core sublayer 1005, and a third glass core sublayer 1006 stacked sequentially. The connecting sublayer 101 includes a first connecting sublayer 1015, a second connecting sublayer 1016, and a third connecting sublayer 1017. The first connecting sublayer body 1011 of the first connecting sublayer 1015 is located between the first glass core sublayer 1004 and the second glass core sublayer 1005. The first connecting sublayer body 1011 of the second connecting sublayer 1016 is located between the second glass core sublayer 1005 and the third glass core sublayer 1006. The first connecting sublayer body 1011 of the third connecting sublayer 1017 is located between the third glass core sublayer 1006 and the first wiring layer 110.
[0039] The glass substrate 1001 of the second glass core layer 1005 includes a first substrate opening 1001a and a second substrate opening 1001b, and the glass substrate 1001 of the third glass core layer 1006 includes a third substrate opening 1001c, wherein the second substrate opening 1001b and the third substrate opening 1001c are correspondingly provided.
[0040] The first chip 102 includes a first sub-chip 102a, a second sub-chip 102b, and a third sub-chip 102c of different types. The first sub-chip 102a is disposed in the opening 1001a of the first substrate. The chip pins 1020 of the first sub-chip 102a are electrically connected to the first conductive posts 1003 of the first glass core layer 1004 and the first conductive posts 1003 of the third glass core layer 1006 through the second conductive posts 1013 of the first connecting sub-layer 1015 and the second conductive posts 1013 of the second connecting sub-layer 1016, respectively.
[0041] The second sub-chip 102b is disposed in the second substrate opening 1001b, and the third sub-chip 102c is disposed in the third substrate opening 1001c. The chip pin 1020 on one side of the second sub-chip 102b is electrically connected to the first conductive post 1003 of the first glass core layer 1004 through the second conductive post 1013 of the first connecting sub-layer 1015. The chip pin 1020 on the other side of the second sub-chip 102b is electrically connected to the chip pin 1020 of the third sub-chip 102c through the second conductive post 1013 of the second connecting sub-layer 1016.
[0042] Furthermore, please see again Figure 1 The first sub-chip 102a includes a bridging chip, the second sub-chip 102b includes an electrical chip, and the third sub-chip 102c includes a fiber optic array chip.
[0043] The second chip 120 includes a switching chip or a storage chip.
[0044] In this embodiment, a bridge die is embedded in the second glass core layer 1005 for high-density local interconnection, bridging and routing signals from different chips. An electrical chip (EIC) is used to drive the laser and amplify the received signal. The fiber array chip includes an optical chip (PIC) and a fiber array (FAU). The switching chip (ASIC) located on the first wiring layer 110 serves as the main control chip, responsible for routing and switching data packets. Furthermore, the second chip 120 may include a switching chip and a storage chip, with the storage chip located on both sides of the switching chip.
[0045] In the above scheme, the chip packaging structure 1 constitutes a co-packaged optical structure, inheriting all the core modules of the co-packaged optical system within a single package. On one hand, the electrical chip and fiber array chip in the glass core layer 10 are vertically interconnected, and both are also vertically interconnected with the switching chip. This constitutes the shortest path for direct transmission between the chips, significantly reducing signal loss and delay. On the other hand, the electrical chip and fiber array chip are directly integrated into the glass core layer 10, without occupying other packaging space, significantly improving the utilization rate of the chip packaging structure 1 and helping to reduce its size.
[0046] In addition, in this embodiment, the second sub-chip 102b and the third sub-chip 102c do not need to be directly connected. Alternatively, at least one glass core sub-layer 100, a dielectric sub-layer, and a redistribution layer can be set between them to separate and connect them.
[0047] Furthermore, please see again Figure 1At least some of the glass substrates 1001 of the glass core layer 100 have different coefficients of thermal expansion (CTE). In this embodiment, the glass substrates 1001 of different glass core layers 100 can use different CTEs. For example, the glass substrate 1001 near the chip layer 12 can be selected with a CTE matching the material of the first wiring layer 110, the glass substrate 1001 near the wiring layer 11 can be selected with a CTE matching the material of the second wiring layer 111, and the CTE of the middle glass substrate 1001 is adjusted according to the actual situation, forming a CTE transition region within the chip packaging structure 1. In this way, constructing a CTE transition region within the chip packaging structure 1 avoids thermal mismatch stress caused by abrupt changes in the CTE, reduces warping of the chip packaging structure 1, and significantly improves the temperature cycle life and long-term reliability of the chip packaging structure 1.
[0048] Furthermore, please see again Figure 1 The glass core layer 10 further includes at least one dielectric sublayer (not shown in the figure), which is located between adjacent glass core layer sublayers 100. The dielectric sublayer includes a dielectric sublayer body and a third conductive post penetrating the dielectric sublayer body. The third conductive post of the dielectric sublayer is electrically connected to the first conductive post 1003 of the glass core layer 100 via a second conductive post 1013 connecting sublayer 101. The material of the dielectric sublayer body includes a semiconductor material or an organic material, and the semiconductor material includes silicon.
[0049] In this embodiment, one or more layers in the glass core layer 10 can be dielectric layers, i.e., TSV silicon interposers or organic interposers can be used, and they are connected to adjacent dielectric layers or glass core layer sub-layers 100 through connecting sub-layers 101. This improves the flexibility of the chip packaging structure 1 design to adapt to different application scenarios.
[0050] Based on the same inventive concept, please see Figure 2 and Figure 3 , Figure 2 This is a schematic flowchart of the fabrication method of a chip packaging structure 1 provided in this embodiment. Figure 3 for Figure 2 In accordance with the corresponding process flow diagram, this application also provides a method for fabricating a chip packaging structure 1, the method comprising: Step S11: Fabricate a glass core layer 10, wherein the glass core layer 10 includes a plurality of glass core sub-layers 100 and a plurality of connecting sub-layers 101 stacked sequentially, at least some of the connecting sub-layers 101 being located between adjacent glass core sub-layers 100. Each glass core sub-layer 100 includes a glass substrate 1001, a first conductive via 1002 penetrating the glass substrate 1001, and a first conductive post 1003 filling the first conductive via 1002. Each connecting sub-layer 101 includes a first connecting sub-layer body 1011, a second conductive via 1012 penetrating the first connecting sub-layer body 1011, and a second conductive post 1013 filling the second conductive via 1012. The first conductive posts 1003 of adjacent glass core sub-layers 100 are connected by the second conductive via 1013 of the connecting sub-layer 101. The conductive post 1013 is electrically connected. Any layer of glass substrate 1001 includes at least one substrate opening penetrating the glass substrate 1001 (e.g., first substrate opening 1001a, second substrate opening 1001b, and third substrate opening 1001c). At least one type of first chip 102 is disposed in the substrate opening. The first chip 102 is electrically connected to the first conductive post 1003 of the glass core sublayer 100 adjacent to the first chip 102 through the second conductive post 1013. Alternatively, adjacent multilayer glass substrates 1001 respectively include substrate openings penetrating the glass substrate 1001, and the substrate openings of adjacent multilayer glass substrates 1001 are overlapped. At least one type of first chip 102 is disposed in the substrate opening. The first chips 102 are electrically connected to each other through the second conductive post 1013.
[0051] In this step, glass core sub-layer 100 and connecting sub-layer 101 are alternately fabricated to form glass core layer 10. During the fabrication of glass core sub-layer 100, components (such as the first chip 102) are embedded layer by layer. This significantly reduces the difficulty of alignment and the complexity of the fabrication process, and avoids the stress and damage risks caused by opening cavities in the already stacked structure.
[0052] In step S12, a first wiring layer 110 and a second wiring layer 111 are respectively fabricated on opposite sides of the glass core board layer 10, wherein the wiring of the first wiring layer 110 and the wiring of the second wiring layer 111 are electrically connected to the first conductive post 1003 of the glass core board layer 10.
[0053] In this embodiment, by utilizing the high flatness of the glass substrate 1001 in the glass core layer 10, a double-sided wiring layer 11 is fabricated on both sides of the glass core layer 10, thereby improving the fan-out density.
[0054] Step S13: A chip layer 12 is fabricated on the side of the first wiring layer 110 away from the glass core layer 10. The chip layer 12 includes at least one second chip 120 and an encapsulation layer 121 surrounding the second chip 120. The second chip 120 is electrically connected to the wiring of the first wiring layer 110.
[0055] In the above scheme, vertical interconnect channels are formed by the alternating stacking of glass core board sub-layer 100 and connecting sub-layer 101, and some components (such as the first chip 102) are placed between the glass core board sub-layer 100, thereby effectively shortening the signal transmission path between chips, reducing transmission loss, and achieving high interconnect density packaging while ensuring signal integrity.
[0056] In this embodiment, after the first glass core sub-layer 100 in the glass core layer 10 is fabricated, the second wiring layer 111 can be prepared first, and then the subsequent glass core sub-layer 100, the first wiring layer 110 and the chip layer 12 can be prepared.
[0057] Further, please see Figure 4 and Figure 5a and Figure 5b , Figure 4 for Figure 1 A flowchart illustrating the sub-steps corresponding to step S11. Figure 5a and Figure 5b for Figure 4 The corresponding process diagram, step S11 can be implemented in the following way.
[0058] Sub-step S110 provides a first glass core layer 1004.
[0059] In this step, a glass substrate 1001 is first provided, then a first conductive through-hole 1002 is made through the glass substrate 1001, and then a first conductive post 1003 is made in the first conductive through-hole 1002 to form a first glass core layer 1004.
[0060] In sub-step S111, a first connecting sub-layer 1015 is fabricated on one side of the first glass core sub-layer 1004, wherein the first conductive post 1003 of the first glass core sub-layer 1004 is correspondingly disposed and electrically connected to the second conductive post 1013 of the first connecting sub-layer 1015.
[0061] In this step, a first connecting material layer is first coated on one side of the first glass core layer 1004. After the first connecting material layer is patterned, the first connecting window of the first conductive post 1003 is exposed. Then, a second conductive post 1013 is formed based on the first conductive post 1003 exposed by the first connecting window, and the first connecting sublayer 1015 is obtained.
[0062] In sub-step S112, a second glass core layer 1005 is formed on the side of the first connecting sub-layer 1015 away from the first glass core layer 1004. The first conductive post 1003 of the second glass core layer 1005 is electrically connected to the first conductive post 1003 of the first glass core layer 1004 through the second conductive post 1013 of the first connecting sub-layer 1015. The glass substrate 1001 of the second glass core layer 1005 includes a first substrate opening 1001a and a second substrate opening 1001b.
[0063] In this step, the glass substrate 1001, which has a first substrate opening 1001a, a second substrate opening 1001b and a conductive through hole, is first bonded to the first glass core layer 1004. Then, a steel mesh is set on one side of the glass substrate 1001, with only the conductive through hole exposed. Next, copper paste is injected into the conductive through hole to form the first conductive pillar 1003.
[0064] In sub-step S113, the first sub-chip 102a and the second sub-chip 102b are respectively disposed in the first substrate opening 1001a and the second substrate opening 1001b, wherein the first sub-chip 102a and the second sub-chip 102b are electrically connected to the first conductive post 1003 of the first glass core plate sub-layer 1004 through the second conductive post 1013 of the first connecting sub-layer 1015.
[0065] In this step, the chip pins 1020 of the first sub-chip 102a and the second sub-chip 102b are electrically connected to the first conductive post 1003 of the lower first glass core layer 1004.
[0066] In sub-step S114, a second connecting sub-layer 1016 is formed on the side of the second glass core sub-layer 1005 away from the first glass core sub-layer 1004, wherein the second connecting sub-layer 1016 includes a second connecting sub-layer 1016 filled around the first sub-chip 102a and the second sub-chip 102b.
[0067] In this step, a second connecting material layer is first coated on one side of the second glass core layer 1005. The flowing second connecting material layer fills the area around the first sub-chip 102a and the second sub-chip 102b, as well as the surfaces of the second glass core layer 1005, the first sub-chip 102a, and the second sub-chip 102b. After the second connecting material layer is cured, the surface of the second connecting material layer is patterned to obtain a second connecting window exposing the first conductive post 1003 and the chip pin 1020. Then, based on the second connecting window, a second conductive post 1013 is formed at the first conductive post 1003 and the chip pin 1020, resulting in the second connecting sub-layer 1016. That is, the first connecting sub-layer body 1011 of the second connecting sub-layer 1016 is located on the surface of the second glass core layer 1005, and the second connecting sub-layer body 1014 fills the substrate groove formed by the second substrate opening 1001b and the first connecting sub-layer 1015, enclosing the first sub-chip 102a and the second sub-chip 102b.
[0068] In sub-step S115, a third glass core layer 1006 is formed on the side of the second connecting sub-layer 1016 away from the first glass core layer 1004. The first conductive post 1003 of the third glass core layer 1006 is electrically connected to the first conductive post 1003 of the second glass core layer 1005 through the second conductive post 1013 of the second connecting sub-layer 1016. The glass substrate 1001 of the third glass core layer 1006 includes a third substrate opening 1001c, which overlaps with the second substrate opening 1001b.
[0069] In this step, the glass substrate 1001 with the third substrate opening 1001c and the first conductive through hole 1002 is first bonded to the second glass core layer 1005. Then, a steel mesh is set on one side of the glass substrate 1001, with only the conductive through hole exposed. Next, copper paste is injected into the first conductive through hole 1002 to form the first conductive pillar 1003.
[0070] In sub-step S116, the third sub-chip 102c is disposed in the opening 1001c of the third substrate. The third sub-chip 102c is electrically connected to the first conductive post 1003 of the second glass core layer 1005 through the second conductive post 1013 of the second connecting sub-layer 1016. The third sub-chip 102c, the second sub-chip 102b and the first sub-chip 102a are of different types.
[0071] In sub-step S117, a third connecting sub-layer 1017 is formed on the side of the third glass core sub-layer 1006 away from the first glass core sub-layer 1004, wherein the third connecting sub-layer 1017 includes a third connecting sub-layer 1017 filling around the third sub-chip 102c.
[0072] In this step, a third connecting material layer is first coated on one side of the third glass core sub-layer 1006. The flowing third connecting material layer fills the area around the third sub-chip 102c and the surfaces of the third glass core sub-layer 1006 and the third sub-chip 102c. After the third connecting material layer is cured, the third connecting material layer on the surface of the third glass core sub-layer 1006 is patterned to obtain a third connecting window exposing the first conductive pillar 1003. Then, a second conductive pillar 1013 is formed based on the third connecting window to obtain the third connecting sub-layer 1017. That is, the second connecting sub-layer body 1014 of the third connecting sub-layer 1017 fills the substrate groove formed by the third substrate opening 1001c and the second connecting sub-layer 1016, and wraps the third sub-chip 102c. The first connecting sub-layer body 1011 is located on the surfaces of the second glass core sub-layer 1005 and the second connecting sub-layer body 1014.
[0073] Furthermore, prior to step S11, the method further includes: First, a glass substrate 1001 is provided.
[0074] Next, a first substrate opening 1001a and a second substrate opening 1001b are made that penetrate the glass substrate 1001.
[0075] In this step, holes can be made in the glass substrate 1001 by etching.
[0076] Finally, a first conductive via 1002 is fabricated through the glass substrate 1001 to obtain a patterned glass substrate 1001.
[0077] In this step, the first conductive via 1002 can be fabricated using processes such as laser drilling or photochemical etching.
[0078] In this embodiment, glass substrates 1001 corresponding to different glass core sub-layers 100 can be pre-prepared, and then the glass substrates 1001 are bonded to the connecting sub-layer 101 during the fabrication of the glass core sub-layer 100 for subsequent filling of the first conductive pillars 1003. Alternatively, a complete glass substrate 1001 can be directly placed on the connecting sub-layer 101, and then patterned by opening holes, etching, etc. Furthermore, a glass substrate 1001 with solid copper can be directly bonded to the connecting sub-layer 101.
[0079] Please see Figure 6 , Figure 6 The process diagram corresponding to sub-step S112 provided in this embodiment is shown. Sub-step S112 can be implemented in the following ways.
[0080] First, the patterned glass substrate 1001 is bonded to the side of the first connecting sublayer 1015 away from the first glass core sublayer 1004.
[0081] In this step, the patterned glass substrate 1001 is bonded to the first connecting sublayer 1015 through processes such as hot pressing bonding.
[0082] Next, a first conductive post 1003 is formed in the first conductive through hole 1002 to obtain the second glass core layer 1005.
[0083] In this step, the first conductive post 1003 can be formed in the first conductive through hole 1002 by processes such as filling copper paste with steel mesh or electroplating.
[0084] In this embodiment, the subsequent preparation of the single-layer glass core board can be completed in the manner described above, and will not be elaborated here.
[0085] In summary, this application provides a chip packaging structure and a method for fabricating the chip packaging structure. The chip packaging structure includes a glass core layer, a wiring layer, and a chip layer. The glass core layer includes glass core sublayers and connecting sublayers. Any glass substrate includes a substrate opening penetrating the glass substrate, or adjacent multiple glass substrates each include substrate openings, and the substrate openings overlap. At least one first chip is disposed within the substrate opening. The first chip is electrically connected to a first conductive post of the adjacent glass core sublayer through a second conductive post, or the first chips are electrically connected to each other through second conductive posts. The wiring layer is located on opposite sides of the glass core layer, and the chip layer is located on the side of the first wiring layer away from the glass core layer. The chip layer includes at least one second chip and a packaging layer surrounding the second chip. The second chip is electrically connected to the wiring of the first wiring layer. The above structure utilizes the alternating stacking of glass core sublayers and connecting sublayers to form a vertical interconnect channel, and places some components (such as the first chip) between the glass core sublayers, thereby effectively shortening the signal transmission path between chips, reducing transmission loss, and achieving high interconnect density packaging while ensuring signal integrity.
[0086] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A chip packaging structure, characterized in that, The chip packaging structure includes: A glass core layer includes multiple glass core sub-layers and multiple connecting sub-layers stacked sequentially. At least some of the connecting sub-layers are located between adjacent glass core sub-layers. Each glass core sub-layer includes a glass substrate, a first conductive via penetrating the glass substrate, and a first conductive post filling the first conductive via. Each connecting sub-layer includes a first connecting sub-layer body, a second conductive via penetrating the first connecting sub-layer body, and a second conductive post filling the second conductive via. The first conductive posts of adjacent glass core sub-layers are electrically connected through the second conductive posts of the connecting sub-layers. Any layer of the glass substrate includes at least one substrate opening penetrating the glass substrate. At least one first chip of different types is disposed in the substrate opening. The first chip is electrically connected to the first conductive post of the glass core sub-layer adjacent to the first chip through the second conductive post. Alternatively, multiple adjacent layers of glass substrates each include a substrate opening penetrating the glass substrate, and the substrate openings of adjacent layers of glass substrates overlap. At least one first chip of different types is disposed in the substrate opening, and the first chips are electrically connected to each other through the second conductive post. The wiring layer includes a first wiring layer and a second wiring layer, the first wiring layer and the second wiring layer are located on opposite sides of the glass core layer, and the wiring of the first wiring layer and the wiring of the second wiring layer are electrically connected to the first conductive post of the glass core layer. A chip layer is located on the side of the first wiring layer away from the glass core layer. The chip layer includes at least one second chip and a packaging layer surrounding the second chip. The second chip is electrically connected to the wiring of the first wiring layer.
2. The chip packaging structure as described in claim 1, characterized in that, The first conductive post of the glass core board sub-layer is correspondingly provided, and the second conductive post connecting the sub-layer is also correspondingly provided with the first conductive post of the glass core board sub-layer; The first chip includes chip pins arranged at intervals, and the chip pins are also correspondingly arranged with the second conductive post.
3. The chip packaging structure as described in claim 2, characterized in that, The connection sublayer also includes a second connection sublayer body, which is disposed around the first chip. The materials of the first connecting sublayer body and the second connecting sublayer body include thermally conductive materials.
4. The chip packaging structure as described in claim 3, characterized in that, The glass core sublayer includes a first glass core sublayer, a second glass core sublayer, and a third glass core sublayer stacked sequentially. The connecting sublayer includes a first connecting sublayer, a second connecting sublayer, and a third connecting sublayer. The first connecting sublayer body of the first connecting sublayer is located between the first glass core sublayer and the second glass core sublayer. The first connecting sublayer body of the second connecting sublayer is located between the second glass core sublayer and the third glass core sublayer. The first connecting sublayer body of the third connecting sublayer is located between the third glass core sublayer and the first wiring layer. The glass substrate of the second glass core layer includes a first substrate opening and a second substrate opening, and the glass substrate of the third glass core layer includes a third substrate opening, wherein the second substrate opening and the third substrate opening are overlapped. The first chip includes a first sub-chip, a second sub-chip, and a third sub-chip of different types. The first sub-chip is disposed in the opening of the first substrate. The chip pins of the first sub-chip are electrically connected to the first conductive post of the first glass core layer and the first conductive post of the third glass core layer through the second conductive post of the first connecting sub-layer and the second conductive post of the second connecting sub-layer, respectively. The second sub-chip is disposed in the opening of the second substrate, and the third sub-chip is disposed in the opening of the third substrate. The chip pins on one side of the second sub-chip are electrically connected to the first conductive post of the first glass core layer through the second conductive post of the first connecting sub-layer, and the chip pins on the other side of the second sub-chip are electrically connected to the chip pins of the third sub-chip through the second conductive post of the second connecting sub-layer.
5. The chip packaging structure as described in claim 4, characterized in that, The first sub-chip includes a bridging chip, the second sub-chip includes an electrical chip, and the third sub-chip includes a fiber optic array chip. The second chip includes a switching chip or a memory chip.
6. The chip packaging structure as described in claim 1, characterized in that, The coefficients of thermal expansion of the glass substrates of at least some of the glass core layers are different.
7. The chip packaging structure as described in claim 1, characterized in that, The glass core layer further includes at least one dielectric sublayer, which is located between adjacent glass core layers; The dielectric sublayer includes a dielectric sublayer body and a third conductive post penetrating the dielectric sublayer body. The third conductive post of the dielectric sublayer is electrically connected to the first conductive post of the glass core sublayer through the second conductive post of the connecting sublayer. The material of the dielectric sublayer body includes semiconductor materials or organic materials, and the semiconductor material includes silicon.
8. A method for fabricating a chip packaging structure, characterized in that, The method includes: A glass core layer is fabricated, wherein the glass core layer comprises a plurality of glass core sub-layers and a plurality of connecting sub-layers stacked sequentially, at least some of the connecting sub-layers being located between adjacent glass core sub-layers. Each glass core sub-layer includes a glass substrate, a first conductive via penetrating the glass substrate, and a first conductive post filling the first conductive via. Each connecting sub-layer includes a first connecting sub-layer body, a second conductive via penetrating the first connecting sub-layer body, and a second conductive post filling the second conductive via. The first conductive posts of adjacent glass core sub-layers are electrically connected through the second conductive posts of the connecting sub-layers. Any layer of the glass substrate includes at least one substrate opening penetrating the glass substrate, and at least one first chip of different types is disposed within the substrate opening. The first chip is electrically connected to the first conductive post of the adjacent glass core sub-layer through the second conductive post. Alternatively, adjacent layers of glass substrates each include substrate openings penetrating the glass substrate, and the substrate openings of adjacent layers of glass substrates overlap. At least one first chip of different types is disposed within the substrate opening, and the first chips are electrically connected to each other through the second conductive post. A first wiring layer and a second wiring layer are respectively fabricated on opposite sides of the glass core layer, wherein the wiring of the first wiring layer and the wiring of the second wiring layer are electrically connected to the first conductive post of the glass core layer. A chip layer is fabricated on the side of the first wiring layer away from the glass core layer, wherein the chip layer includes at least one second chip and an encapsulation layer surrounding the second chip, and the second chip is electrically connected to the wiring of the first wiring layer.
9. The method for fabricating the chip packaging structure as described in claim 8, characterized in that, The steps for fabricating the glass core layer include: Provide a first glass core layer; A first connecting sublayer is formed on one side of the first glass core sublayer, wherein the first conductive post of the first glass core sublayer is correspondingly and electrically connected to the second conductive post of the first connecting sublayer. A second glass core layer is formed on the side of the first connecting sublayer away from the first glass core layer, wherein the first conductive post of the second glass core layer is electrically connected to the first conductive post of the first glass core layer through the second conductive post of the first connecting sublayer, and the glass substrate of the second glass core layer includes a first substrate opening and a second substrate opening. The first sub-chip and the second sub-chip are respectively disposed in the first substrate opening and the second substrate opening, wherein the first sub-chip and the second sub-chip are electrically connected to the first conductive post of the first glass core plate sub-layer through the second conductive post of the first connecting sub-layer. A second connection sublayer is formed on the side of the second glass core sublayer away from the first glass core sublayer, wherein the second connection sublayer includes a second connection sublayer filling around the first sub-chip and the second sub-chip; A third glass core layer is fabricated on the side of the second connecting sublayer away from the first glass core layer. The first conductive post of the third glass core layer is electrically connected to the first conductive post of the second glass core layer through the second conductive post of the second connecting sublayer. The glass substrate of the third glass core layer includes a third substrate opening, which overlaps with the second substrate opening. A third sub-chip is disposed in the opening of the third substrate, wherein the third sub-chip is electrically connected to the first conductive post of the second glass core plate sub-layer through the second conductive post of the second connecting sub-layer, and the third sub-chip, the second sub-chip, and the first sub-chip are of different types; A third connecting sublayer is formed on the side of the third glass core sublayer away from the first glass core sublayer, wherein the third connecting sublayer includes a third connecting sublayer filling around the third subchip.
10. The method for fabricating the chip packaging structure as described in claim 9, characterized in that, Prior to the step of fabricating the glass core layer, the method further includes: Provide a glass substrate; A first substrate opening and a second substrate opening are fabricated that penetrate the glass substrate. A first conductive via is fabricated through the glass substrate to obtain a patterned glass substrate. The step of fabricating a second glass core layer on the side of the first connecting sublayer away from the first glass core layer includes: The patterned glass substrate is bonded to the side of the first connecting sublayer away from the first glass core sublayer. The first conductive pillar is formed within the first conductive through-hole to obtain the second glass core layer.