Packaging structure and forming method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a packaging structure and a forming method thereof, and the packaging structure comprises an interconnection device which is a thinned bridge chip and is provided with a first surface and a second surface which are opposite to each other; the first chip is positioned on one side of the first surface of the interconnection device, and the projection surface of the first chip is partially overlapped with the first surface of the interconnection device; the second chip is located on one side of the first face of the interconnection device, the projection face of the second chip is partially overlapped with the first face of the interconnection device, and the first chip and the second chip are electrically connected through the interconnection device. Based on the above technical scheme, the structure packaging density and the chip interconnection density are significantly improved, the signal transmission distance is reduced, and the electrical performance is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a packaging structure and a method for forming the same. Background Art

[0002] As communication speed and storage requirements double, multi-chip packaging has become an important packaging technology for saving space, power consumption and achieving high-speed communication. In order to integrate multiple chips into the same package, an interposer is usually formed or a bridge chip is used to achieve multi-chip interconnection. However, the preparation process of the interposer is relatively high and through-silicon vias (TSV) need to be formed, which increases the cost; the bridge chip needs to be embedded in the substrate or copper pillars need to be formed in the same layer to compensate for the height difference introduced by the bridge chip attachment. The former has a high preparation cost, and the latter is not conducive to the high-density integration of multi-chip interconnection. Summary of the invention

[0003] In view of the above problems in the prior art, the present application provides a packaging structure and a method for forming the same. The specific technical solutions are as follows:

[0004] In one aspect, the present application provides a packaging structure, the packaging structure comprising:

[0005] The interconnection device is a thinned bridge chip having a first surface and a second surface opposite to each other;

[0006] A first chip is located on one side of the first surface of the interconnection device, and a projection surface of the first chip partially overlaps with the first surface of the interconnection device;

[0007] The second chip is located on one side of the first surface of the interconnection device, the projection surface of the second chip partially overlaps with the first surface of the interconnection device, and the first chip and the second chip are electrically connected through the interconnection device.

[0008] On the other hand, the present application provides a method for forming a package structure, the method comprising:

[0009] Providing a first carrier, a bridge chip, a first chip and a second chip, wherein the bridge chip has a first surface and a second surface opposite to each other, and the second surface of the bridge chip is attached to the first carrier;

[0010] Integrate the first chip and the second chip on one side of the first surface of the bridge chip, wherein the projection surface of the first chip partially overlaps with the first surface of the bridge chip, and the projection surface of the second chip partially overlaps with the first surface of the bridge chip;

[0011] Peeling off the first carrier to expose the second side of the bridge chip;

[0012] The bridge chip is thinned to form an interconnection device, and the first chip and the second chip are electrically connected through the interconnection device.

[0013] On the other hand, the present application provides an integrated circuit, which includes an electronic device manufactured by the above-mentioned packaging structure or the method for forming the packaging structure.

[0014] On the other hand, the present application provides an electronic device, which includes an electronic device manufactured using the above-mentioned packaging structure or the method for forming the packaging structure.

[0015] Based on the above technical solution, this application has the following beneficial effects:

[0016] The technical solution of the present application integrates the first chip and the second chip on the first surface side of the interconnection device formed by the thinned bridge chip, and the projection surfaces of the first chip and the second chip respectively overlap with the first surface of the interconnection device, thereby reducing the height difference and packaging size requirements introduced by the interconnection device, shortening the electrical connection distance between chips, improving the chip integration density and interconnection density of multi-chip packaging, reducing resistance, improving heat dissipation efficiency and communication speed between chips, and reducing signal delay; and there is no need to prepare an intermediate layer or perform substrate and wiring layer trenching and etching, thereby reducing the complexity of the chip packaging process and the packaging cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments or prior art descriptions. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 : A cross-sectional view of a packaging structure provided in an embodiment of the present application;

[0019] Figure 2 : A schematic diagram of a process for forming a packaging structure provided in an embodiment of the present application;

[0020] Figure 3 : A cross-sectional view of a first carrier provided in an embodiment of the present application;

[0021] Figure 4 : A cross-sectional view of a first carrier chip attached with a bridge chip provided in an embodiment of the present application;

[0022] Figure 5 : A cross-sectional view of a first carrier sheet with a bridge chip and an initial packaging layer attached thereto provided in an embodiment of the present application;

[0023] Figure 6: A cross-sectional view of a first carrier wafer provided with a redistribution structure, a bridge chip and an initial packaging layer according to an embodiment of the present application;

[0024] Figure 7 : A cross-sectional view of a packaging structure during a formation process provided by an embodiment of the present application;

[0025] Figure 8 : A cross-sectional view of another packaging structure during the formation process provided by an embodiment of the present application;

[0026] Fig. 9 : A cross-sectional view of another packaging structure during the formation process provided by an embodiment of the present application;

[0027] Fig.10 : A cross-sectional view of another packaging structure during the formation process provided by an embodiment of the present application;

[0028] Fig.11 : A cross-sectional view of another packaging structure provided in an embodiment of the present application;

[0029] Fig.12 : A cross-sectional view of another packaging structure provided in an embodiment of the present application;

[0030] Fig.13 : A cross-sectional view of another packaging structure provided in an embodiment of the present application;

[0031] Fig.14 : A cross-sectional view of another packaging structure provided in an embodiment of the present application;

[0032] Figure numerals: 100-packaging structure, 101-interconnection device, 101a-first side of the interconnection device, 101b-second side of the interconnection device, 101c-sidewall of the interconnection device, 102-first chip, 103-second chip, 104-substrate, 105-rewiring structure, 105a-metal wiring, 106-first packaging layer, 106a-through hole, 107-conductive structure, 108-first bump structure, 109-second bump structure, 110-second packaging layer, 111-first filling structure, 112-second filling structure, 113-third bump structure, 200-bridge chip, 300-first carrier, 301-adhesion layer, 400-initial packaging layer, 500-second carrier. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0034] It should be noted that in the description of the present application, for the following defined terms, unless a different definition is given in the claims or elsewhere in this specification, these definitions should be applied. All numerical values, whether or not explicitly indicated, are defined herein as being modified by the term "about". The term "about" generally refers to a numerical range that a person of ordinary skill in the art would consider to be equivalent to the stated value to produce substantially the same properties, functions, results, etc. A numerical range indicated by a low value and a high value is defined to include all numerical values ​​included in the numerical range and all subranges included in the numerical range.

[0035] It should be noted that, in the description of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0036] It should be noted that, in the description of the present application, the meaning of the terms "on", "above", "above", and "above" should be interpreted in the broadest sense, meaning that the description containing these terms is interpreted as "the component can be set on another component in direct contact, or there can be an intermediate component or layer between the components". In addition, for the convenience of description, the present application may also use spatial relative terms such as "under", "below", "under", "on", "above", "above", "lower", "upper", etc. to describe the relationship between an element or component and another element or component shown in the drawings. In addition to the orientations described in the figures, the spatially relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90° or in other orientations), and the spatially relative descriptors used in the present application can be interpreted accordingly.

[0037] The term "layer" as used in this application refers to a portion of a material including an area having a certain thickness. A layer may extend over the entire underlying or superstructure, or may extend over a localized area of ​​the underlying or superstructure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically and / or along a tapered surface. A layer may include multiple layers. For example, a redistribution layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0038] It should be understood that the “surface” used in this application, such as the “first surface”, “second surface”, etc., refers to the XY plane of the chip or substrate 104, etc., corresponding to the XY plane of the packaging structure 100, and the “thickness direction” refers to the Z direction perpendicular to the XY plane. The “thickness” or “height” mentioned in this application all refer to the Z-direction thickness or Z-direction height.

[0039] The following combination Figure 1 and 3 -14 introduces the package structure 100 of the present application. It can be understood that the package structure 100 in the accompanying drawings is only a technical solution of a specific embodiment of the present application, and the package structure 100 of the present application may include fewer or more structural features, and is not limited to the device structure described in the accompanying drawings. Figure 1 The package structure 100 includes: an interconnection device 101, which is a thinned bridge chip 200 and has a first surface and a second surface opposite to each other; a first chip 102, which is located on one side of the first surface 101a of the interconnection device, and the projection surface of the first chip 102 partially overlaps with the first surface 101a of the interconnection device; a second chip 103, which is located on one side of the first surface 101a of the interconnection device, and the projection surface of the second chip 103 partially overlaps with the first surface 101a of the interconnection device, and the first chip 102 and the second chip 103 are electrically connected through the interconnection device 101.

[0040] Specifically, the bridge chip 200 may include but is not limited to a silicon bridge (Si-bridge) chip. In one embodiment, the bridge chip 200 is a silicon bridge chip, and accordingly, the interconnect device 101 is a thinned silicon bridge chip. The silicon bridge chip is called FOCoSB (bridge), which uses a tiny silicon wafer with a routing layer as an intra-package interconnect between small chips, such as a graphics computing chip (GPU) and an HBM (High Bandwidth Memory) core. In some embodiments, the first side 101a of the interconnect device is the reverse side of the thinned bridge chip 200, and the second side 101b of the interconnect device is the front side of the thinned bridge chip 200.

[0041] Specifically, the bridge chip 200 may be thinned by a grinding or lapping process to form the interconnection device 101 by thinning the second surface of the bridge chip 200 to a preset thickness, and the second surface of the bridge chip 200 corresponds to the second surface 101 b of the interconnection device.

[0042] Specifically, the first chip 102 and the second chip 103 can be chips of the same category, such as a memory chip or a logic chip, or the first chip 102 and the second chip 103 can be chips of different categories. In one embodiment, the first chip 102 is a logic chip and the second chip 103 is a memory chip. Exemplarily, the second chip 103 is an HBM (High Bandwidth Memory) chip. It can be understood that in addition to memory chips or logic chips, the package structure 100 can also include other types of chips. The first chip 102 and the second chip 103 are electrically connected through the interconnect device 101 to realize multi-chip packaging, thereby forming a package structure 100 with corresponding functions.

[0043] In some embodiments, the first chip 102 and the second chip 103 are physically separated to avoid chip package compression damage or signal crosstalk.

[0044] It can be understood that each interconnection device 101 can connect more than one first chip 102 or more than one second chip 103, and a package group is formed by the first chip 102 and the second chip 103 electrically connected by the interconnection device 101. The package structure 100 can include more than one package group, and different package components can be electrically connected through the substrate 104, thereby forming more chip packages and signal transmission.

[0045] Specifically, refer to Figure 1 and 11 -14, the first chip 102 and the second chip 103 are integrated on one side of the first surface 101a of the interconnection device, and are electrically connected to the interconnection device 101 through wiring and / or electrical connection structures to form a signal transmission path between the first chip 102 and the second chip 103. The projection surface of the first chip 102 and the projection surface of the second chip 103 overlap with different areas on the first surface 101a of the interconnection device, so as to improve the integration and form electrical connection structures and / or wiring of different chips.

[0046] In this way, the first chip 102 and the second chip 103 are integrated on the first surface 101a side of the interconnection device formed by the thinned bridge chip 200, and the projection surfaces of the first chip 102 and the second chip 103 respectively overlap with the first surface 101a of the interconnection device, thereby reducing the height difference and packaging size requirements introduced by the interconnection device 101, shortening the electrical connection distance between chips, improving the chip integration density and interconnection density of the multi-chip package, reducing resistance, improving heat dissipation efficiency and communication speed between chips, and reducing signal delay; and there is no need to prepare an intermediate layer or perform trenching and etching of the substrate 104 and the wiring layer, thereby reducing the complexity of the chip packaging process and the packaging cost.

[0047] In some embodiments, the thickness of the interconnect device 101, i.e., the aforementioned preset thickness, is 2 μm to 15 μm, preferably 2 μm to 10 μm; it can be understood that the thickness of the interconnect device 101 can be any point value within the above range, such as the upper limit of the thickness of the interconnect device 101 can be 15 μm, 14 μm, 13 μm, 12 μm, 11 μm, 10 μm, 9 μm, 8 μm, etc., and the lower limit of the thickness can be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, etc., and can also be 5 μm, 6 μm, 7 μm, etc. The lateral size of the interconnect device 101 can be selected based on the packaging requirements and is not limited here. By forming the interconnect device 101 of the above thickness, the power consumption requirements are met while the integration density is improved, and the thickness of the electrical connection structure between the substrate 104 and the first chip 102 and the second chip 103 is reduced, thereby reducing the difficulty of forming the transmission path and the electrical connection structure.

[0048] Based on some or all of the above embodiments, in some embodiments, reference Figure 1 and 14 The package structure 100 also includes a substrate 104, which is located on the second surface 101b of the interconnection device, is physically separated from the interconnection device 101, and is electrically connected to the first chip 102 and the second chip 103 respectively to achieve electrical signal transmission and processing, and provide protection, support and heat dissipation for the chips. In one example, in the thickness direction, there is a gap between the interconnection device 101 and the substrate 104, and the interconnection device 101 is placed between the layer formed by the first chip 102 and the second chip 103 and the substrate 104, and is encapsulated by the encapsulation material to enhance the stable connection of the interconnection device 101. In one example, the substrate 104 is a PCB (Printed Circuit Board).

[0049] Specifically, the interconnection device 101 is not directly electrically connected to the substrate 104 , that is, the interconnection device 101 is not directly physically connected to the substrate 104 to form an electrical connection or is not directly electrically connected through the attached conductive structure 107 to serve as a signal transmission device between the first chip 102 and the second chip 103 .

[0050] Based on some or all of the above implementations, in the specific embodiments, reference Figure 1 and 11-14, the packaging structure 100 also includes a rewiring structure 105, which is in contact with the first surface 101a of the interconnection device, and is located between the first chip 102 and the first surface 101a of the interconnection device, and between the second chip 103 and the first surface 101a of the interconnection device. The projection area of ​​the rewiring structure 105 on the substrate 104 exceeds the projection area of ​​the interconnection device 101 on the substrate 104, so as to improve the chip integration density and realize chip interconnection and substrate 104 / chip electrical connection; the interconnection device 101 is electrically connected to the first chip 102 and the second chip 103 respectively through the rewiring structure 105, and the substrate 104 is electrically connected to the first chip 102 and the second chip 103 respectively through the rewiring structure 105.

[0051] Specifically, the rewiring structure 105 may include at least one rewiring layer (Re-distributed layer, RDL) for chip interconnection and electrical extension of the XY plane, where the XY plane refers to the XY plane of the chip or substrate 104. The rewiring layer can be formed by at least photolithography, metal layer deposition and dielectric layer deposition processes, and metal wiring 105a is formed in the layer to achieve the rearrangement of the IO port and redistribution of electrical signals, power signals or ground signals. The dielectric layer in the rewiring layer can be prepared using a polymer material, and the material of the metal wiring 105a includes but is not limited to one or more of copper, titanium, tungsten, aluminum, gold, nickel, tantalum, titanium nitride and tantalum nitride, or other alternative conductive materials. In some embodiments, the thickness of the rewiring structure 105 is 3-5μm.

[0052] Specifically, the first side 101a of the interconnection device is bonded to one side of the rewiring structure 105, and the side of the rewiring structure 105 facing away from the interconnection device 101 is connected to the first chip 102 and the second chip 103, so as to realize the interconnection of the first chip 102 and the second chip 103 through the rewiring structure 105 and the interconnection device 101. Compared with the chip interconnection method using hybrid bonding or the chip embedded in the substrate 104, the chip thinning bridge method of the present application does not need to use bonding equipment and complex bonding steps, nor does it need to be grooved and aligned on the substrate 104, thereby reducing the process difficulty and preparation cost of the chip interconnection package. The hybrid bonding here refers to bonding the bridge chip 200 to the functional chip through heterogeneous metal. In addition, the interconnection device 101 is attached and packaged in the fan-out RDL layer to form a 2.5D packaging solution that does not use an interposer. Compared with the 2.5D packaging using a silicon interposer, the interconnection device 101 such as a silicon wafer is only used in the area where the two chips are connected, which greatly reduces the cost.

[0053] Based on some or all of the above embodiments, in some embodiments, reference Figure 1 and 11-14, the package structure 100 further includes a plurality of second bump structures 109 which are arranged at intervals on a side of the rewiring structure 105 away from the interconnection device 101 and are used to electrically connect the first chip 102 and the rewiring structure 105 , and to electrically connect the second chip 103 and the rewiring structure 105 .

[0054] Specifically, part of the second bump structure 109 forms a solder joint between the first chip 102 and the rewiring structure 105, and part of the second bump structure 109 forms a solder joint between the second chip 103 and the rewiring structure 105, so as to perform chip integration and electrical connection, and realize signal transmission between the first chip 102 and the second chip 103 through the second bump structure 109, the rewiring structure 105 and the interconnection device 101 that are electrically connected in sequence, and realize signal transmission between the first chip 102 / substrate 104 and the second chip 103 / substrate 104 through the electrically connected second bump structure 109 and the rewiring structure 105. Reducing the size of the package structure 100 based on the second bump structure 109 is conducive to batch production and increasing the number of I / O ports between chips and between chips and between chips and substrates 104.

[0055] Optionally, the material of the second bump structure 109 may include but is not limited to copper, nickel, aluminum, palladium, gold, silver, tin, etc. or a combination thereof, or may be other conductive materials that meet the bump formation process. Preferably, the material of the second bump structure 109 includes tin.

[0056] Optionally, the second bump structure 109 may be, but is not limited to, a solder ball, a controlled collapse chip connection (ControlledCollapse Chip Connection, C4) or a micro bump (Chip Connection, C2), etc., preferably a micro bump (Chip Connection, C2) to improve the interconnect packaging density.

[0057] In some embodiments, the height of the second bump structure 109 is 3-50 μm, preferably 5-20 μm, to further reduce the size of the package structure 100 and the signal transmission distance, reduce signal inductance and voltage noise, and thus improve the electrical performance of the chip.

[0058] Based on some or all of the above embodiments, in some embodiments, reference Figure 1 and 11-14, the package structure 100 also includes a second package layer 110, which is stacked on the rewiring structure 105 and is used to cover the side walls of the first chip 102 and the second chip 103. The second package layer 110 exposes a side of the first chip 102 away from the rewiring structure 105 and a side of the second chip 103 away from the rewiring structure 105. The second package layer 110 covers the side walls of the first chip 102 and the second chip 103 to achieve chip plastic sealing, strengthen the interconnection between the chip and the rewiring structure 105, improve the reliability of the package structure 100, enhance the heat dissipation and shock resistance of the package structure 100, and reduce signal noise.

[0059] Specifically, the second encapsulation layer 110 can be made of plastic packaging materials or flexible substrate materials, such as including but not limited to epoxy molding compound (EMC), Ajinomoto build up film (ABF), polyimide (PI), etc., or other alternative materials that can be cured into layers can be used.

[0060] In some embodiments, reference Figure 1 and 8 -14, the package structure 100 also includes a second filling structure 112, which is used to fill the gap between the first chip 102 and the redistribution structure 105 and the gap between the second chip 103 and the redistribution structure 105. Specifically, the second filling structure 112 covers the second bump structure 109. The second filling structure 112 strengthens the interconnection between the second package layer 110, the redistribution structure 105, and the second bump structure 109, alleviates the stress concentration problem caused by the mismatch of thermal expansion coefficients between different materials, improves the reliability of the package structure 100, and at the same time improves the temperature and humidity resistance and impact resistance, and reduces the vibration noise of the device.

[0061] Specifically, the material of the second filling structure 112 can be an adhesive, which can include one or more of epoxy resin, modified epoxy resin, polyimide resin, etc., or other alternative adhesive materials. The material of the second filling structure 112 can also include auxiliary components such as fillers, hardeners, adhesion promoters, flame retardants and dispersants.

[0062] Based on some or all of the above embodiments, in some embodiments, reference Figure 1 and 11 -14, the packaging structure 100 also includes a first packaging layer 106, which is located between the substrate 104 and the redistribution structure 105, covers the side wall 101c of the interconnection device and exposes the first surface 101a and the second surface of the interconnection device; by forming the first packaging layer 106, the connection stability and processing strength of the interconnection device 101 are improved, which is beneficial to the grinding and thinning process and improves the yield rate.

[0063] Specifically, the first packaging layer 106 covers the side wall 101c of the interconnect device and can be made of a plastic packaging material or a flexible substrate material, such as but not limited to epoxy molding compound (EMC), Ajinomoto build up film (ABF), polyimide (PI), etc.

[0064] In a specific embodiment, a plurality of spaced conductive structures 107 are provided through the first packaging layer 106, and the conductive structures 107 are used to connect the substrate 104 and the redistribution structure 105. The material of the conductive structure 107 may be one or more of copper, titanium, tungsten, aluminum, gold, nickel, etc., or other alternative conductive materials. Accordingly, a plurality of spaced through holes 106a are formed in the first packaging layer 106, and the conductive structures 107 are formed in the through holes 106a by metal filling.

[0065] Specifically, the thickness of the first encapsulation layer 106 is 2 μm to 15 μm, preferably 2 μm to 10 μm. It is understandable that the thickness of the first encapsulation layer 106 can be any point value within the above range, such as the upper limit of the thickness can be 15 μm, 14 μm, 13 μm, 12 μm, 11 μm, 10 μm, 9 μm, 8 μm, etc., the lower limit of the thickness can be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, etc., and can also be 5 μm, 6 μm, 7 μm, etc. The intermediate value. By forming the above-mentioned thinner first encapsulation layer 106, the side wall 101c of the interconnection device is covered, the thickness requirement of the chip interconnection and the difficulty of forming the subsequent conductive structure 107 are reduced, and the efficiency of forming the conductive structure 107 is improved.

[0066] Specifically, the thickness of the conductive structure 107 is 2 μm to 15 μm, preferably 2 μm to 10 μm. It is understandable that the thickness of the conductive structure 107 can be any point value within the above range, such as the upper limit of the thickness can be 15 μm, 14 μm, 13 μm, 12 μm, 11 μm, 10 μm, 9 μm, 8 μm, etc., and the lower limit of the thickness can be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, etc., and can also be 5 μm, 6 μm, 7 μm, etc. The intermediate value. Based on the thinning configuration of the interconnect device 101, the thickness requirements of the packaging layer and the conductive structure 107 therein are reduced, the difficulty of metal filling is reduced, and the preparation efficiency and formation effect of the conductive structure 107 are improved.

[0067] In some embodiments, solder joints can be formed directly through the conductive structure 107 to connect the substrate 104 and the redistribution structure 105 and realize electrical connection; in other embodiments, the package structure 100 further includes a plurality of first bump structures 108, which are arranged at intervals between the first package layer 106 and the substrate 104, and the first bump structures 108 are respectively connected to the substrate 104 and the conductive structure 107, so as to realize electrical connection between the substrate 104 and the redistribution structure 105 through the conductive structure 107 and the first bump structures 108. The first bump structures 108 can form solder joints between the substrate 104 and the redistribution structure 105, cooperate to realize the integration and electrical connection of the substrate 104, reduce the size of the package structure 100, and effectively increase the number of I / O ports.

[0068] Optionally, the material of the first bump structure 108 may include but is not limited to copper, nickel, aluminum, palladium, gold, silver, tin, etc. or a combination of multiple thereof, or other alternative conductive materials. Preferably, the material of the first bump structure 108 includes tin.

[0069] Optionally, the first bump structure 108 may be, but is not limited to, a ball grid array (BGA), a solder ball, a controlled collapse chip connection (C4) or a micro bump (Chip Connection, C2), etc., preferably a micro bump.

[0070] In some embodiments, the height of the first bump structure 108 is 30-80 μm, preferably 30-50 μm. The pitch between the first bump structures is 60-160 μm, preferably 60-140 μm. The interconnect device 101 is obtained by thinning the bridge chip, and the height difference formed by attaching the interconnect device 101 is reduced, so that the interconnect device 101 and the substrate 104 can be connected through the bump structure, thereby realizing the miniaturization of the packaging structure and the complexity of the substrate electrical connection; and based on the thinner first packaging layer 106 and the conductive structure 107 running through the first packaging layer 106, the size requirement of the first bump structure 108 is reduced, and the packaging structure 100 is further miniaturized, thereby further reducing the signal inductance and reducing the voltage noise.

[0071] In some embodiments, reference Figure 1 and 14The package structure 100 further includes a first filling structure 111, which is used to fill the gap between the first package layer 106 and the substrate 104. Specifically, the first filling structure 111 covers the first bump structure 108. The first filling structure 111 strengthens the connection between the first package layer 106, the substrate 104, and the first bump structure 108, alleviates the stress concentration problem introduced by the mismatch of thermal expansion coefficients, improves the package reliability, and improves the temperature and humidity resistance, as well as the impact resistance, and reduces the vibration noise of the device.

[0072] Specifically, the material of the first filling structure 111 can be an adhesive, which can include one or more of epoxy resin, modified epoxy resin, polyimide resin, etc., or include other alternative adhesive materials. The material of the first filling structure 111 can also include auxiliary components such as fillers, hardeners, adhesion promoters, flame retardants and dispersants.

[0073] Based on some or all of the above embodiments, in some embodiments, reference Figure 1 The package structure 100 further includes a plurality of third bump structures 113, which are arranged at intervals on a side of the substrate 104 away from the interconnection device 101, for electrical interconnection between the substrate 104 and other devices. The material of the third bump structure 113 may include, but is not limited to, copper, nickel, aluminum, palladium, gold, silver, tin, etc., or a combination of multiple thereof, or other alternative conductive materials. Preferably, the material of the third bump structure 113 includes tin. Optionally, the first bump structure 108 may be, but is not limited to, a ball array, a solder ball, or a controlled collapse chip connection.

[0074] The following combination Figure 1-14 The following describes a method for forming a packaging structure 100 provided in an embodiment of the present application. Figure 1 It is a flow chart of the method for forming the package structure 100. This specification provides method operation steps such as the embodiment or the flow chart, but more or fewer operation steps may be included based on conventional or non-creative labor. The order of steps listed in the embodiment is only one way of executing the order of many steps and does not represent the only execution order. When the actual preparation method is executed, it can be executed in the order of the method shown in the embodiment or the figure or in parallel. The method for forming the package structure 100 may include S11-S14:

[0075] S11 : providing a first carrier 300 , a bridge chip 200 , a first chip 102 and a second chip 103 .

[0076] Specifically, refer to Figure 3The first carrier 300 is used to provide packaging support, chip protection, etc., and can be, but not limited to, a glass carrier, a ceramic carrier, a metal carrier, etc. An adhesive layer 301 can be formed on the first carrier 300 to facilitate the attachment of the bridge chip 200. The lateral size of the bridge chip 200 can be selected based on actual needs, and it has a first surface and a second surface opposite to each other. It can be understood that the first surface of the bridge chip 200 corresponds to the first surface 101a of the interconnection device, and the second surface of the bridge chip 200 corresponds to the second surface 101b of the interconnection device.

[0077] Specifically, refer to Figure 4 The second surface of the bridge chip 200 is attached to the first carrier 300. The bridge chip 200 can be attached to the first carrier 300 by bonding or plastic sealing. For example, the bridge chip 200 can be bonded to the first carrier 300 with its face facing upward.

[0078] In some embodiments, the step of attaching the bridge chip 200 to the first carrier 300 may specifically include: bonding the second side of the bridge chip 200 to the first carrier 300; forming an initial packaging layer 400 on the first carrier 300, the initial packaging layer 400 covering the side wall of the bridge chip 200 and exposing the first side of the bridge chip 200.

[0079] Specifically, refer to Figure 5 , the second side of the bridge chip 200 is attached to the base surface of the first carrier 300, and then sealed with glue to form a packaging layer to cover the bridge chip 200. After grinding, the first side of the bridge chip 200 is exposed, specifically the pad area of ​​the bridge chip 200 is exposed to form an initial packaging layer 400, which is used to form a first packaging layer 106 after coordinated thinning with the bridge chip 200.

[0080] S12 : Integrate the first chip 102 and the second chip 103 on one side of the first surface of the bridge chip 200 .

[0081] Specifically, the projection surface of the first chip 102 partially overlaps with the first surface of the bridge chip 200, and the projection surface of the second chip 103 partially overlaps with the first surface of the bridge chip 200. The projection surface of the first chip 102, the projection surface of the second chip 103, and the projection surface of the bridge chip 200 are arranged nearly parallel. Based on the above arrangement, the size of the package structure 100 is reduced, and the signal transmission distance between the bridge chip 200, the first chip 102, and the second chip 103 is shortened.

[0082] In some embodiments, the first chip 102 and the second chip 103 are physically separated.

[0083] In some embodiments, S12 may include the following steps S121-S122:

[0084] S121: forming a rewiring structure 105 on the first surface of the bridge chip 200;

[0085] S122 : Attach the first chip 102 and the second chip 103 to the side of the redistribution structure 105 facing away from the bridge chip 200 , respectively.

[0086] Specifically, refer to Figure 6 and Figure 7 , the projection area of ​​the rewiring structure 105 on the first carrier 300 exceeds the projection area of ​​the bridge chip 200 on the first carrier 300, and the bridge chip 200 is electrically connected to the first chip 102 and the second chip 103 respectively through the rewiring structure 105. The projection surface of the rewiring structure 105 covers the first surface of the bridge chip 200, and the first chip 102, the bridge chip 200 and the second chip 103 are interconnected through the metal wiring 105a in the corresponding coverage area of ​​the rewiring structure 105, and the first chip 102 / substrate 104 and the second chip 103 / substrate 104 are interconnected through the metal wiring 105a in the area exceeding the bridge chip 200, so as to realize the rearrangement of I / O ports, improve the interconnection density and chip integration capability, and shorten the circuit length to improve the signal quality.

[0087] In some embodiments, the redistribution structure 105 may be formed with at least one redistribution layer (RDL), and illustratively, may have multiple stacked redistribution layers. The redistribution layer may be formed by at least photolithography, metal layer deposition, and dielectric layer deposition.

[0088] In some embodiments, the first chip 102 and the second chip 103 may be attached to the rewiring structure 105 in a manner that specifically includes: forming a plurality of second bump structures 109 arranged at intervals on a side of the rewiring structure 105 that faces away from the bridge chip 200; and attaching the first chip 102 and the second chip 103 to a side of the rewiring structure 105 that faces away from the bridge chip 200 through the plurality of second bump structures 109. The first chip 102 and the second chip 103 are electrically connected to the rewiring structure 105 respectively through the second bump structures 109.

[0089] In a feasible embodiment, the second bump structure 109 can be obtained by reflowing a solder layer formed by processes such as evaporation, electroplating, printing, and solder formation.

[0090] In some embodiments, after S12, the forming method may further include forming a second encapsulation layer 110 and a second filling structure 112, referring to Figure 8Accordingly, after the first chip 102 and the second chip 103 are attached to the rewiring structure 105, a second filling structure 112 is formed to cover the second bump structure and fill the gap between the first chip 102 and the rewiring structure 105, and between the second chip 103 and the rewiring structure 105, thereby strengthening the chip interconnection strength, alleviating the problem of thermal expansion stress concentration, and improving temperature and humidity resistance and impact resistance.

[0091] Furthermore, a second encapsulation layer 110 is formed on the rewiring structure 105 to cover the rewiring structure 105, the sidewalls of the first chip 102, and the sidewalls of the second chip 103, and fill the gap between the first chip 102 and the second chip 103, so as to protect the chips, strengthen the interconnection strength and reliability of the devices, enhance the heat dissipation and shock resistance of the encapsulation structure 100, and reduce signal noise. Specifically, the second encapsulation layer 110 covers the second filling layer; the second encapsulation layer 110 exposes the first chip 102 and the second chip 103 on one side away from the rewiring structure 105.

[0092] S13 : peeling off the first carrier sheet 300 to expose the second surface of the bridge chip 200 .

[0093] Specifically, refer to Fig. 9 and Fig.10 , peel off the first carrier sheet 300 and then flip it over so as to thin the bridge chip 200 from the second surface.

[0094] In some embodiments, before S13, the forming method further includes:

[0095] S21: providing a second carrier 500;

[0096] S22 : attaching a second carrier 500 to the surface of the first chip 102 and the second chip 103 facing away from the bridge chip 200 .

[0097] Specifically, the second carrier 500 is used to provide packaging support and chip protection for the peeling of the first carrier 300 and subsequent processes. After the second carrier 500 is attached to the first chip 102 and the second chip 103 to form a support, the step of peeling the first carrier 300 is performed. The material of the second carrier 500 is similar to that of the first carrier 300, and will not be described in detail.

[0098] S14 : thinning the bridge chip 200 to form an interconnection device 101 .

[0099] Specifically, refer to Fig.11, the bridge chip 200 is thinned to a preset thickness to serve as the interconnection device 101, and the first chip 102 and the second chip 103 are electrically connected through the interconnection device 101. Specifically, a transmission line between the first chip 102 and the second chip 103 is formed by sequentially connecting the second bump structure 109, the metal wiring 105a of the redistribution structure 105, and the interconnection device 101. The preset thickness is 2μm to 15μm, preferably 2μm to 10μm.

[0100] In some embodiments, during the step of thinning the bridge chip 200 to form the interconnect device 101 , the initial packaging layer 400 is thinned simultaneously to form a first packaging layer 106 , which covers the sidewalls 101 c of the interconnect device and exposes the first side 101 a and the second side of the interconnect device.

[0101] In some embodiments, after S14, the forming method further includes:

[0102] S31: forming a plurality of through holes 106 a arranged at intervals in the first packaging layer 106 ;

[0103] S32 : forming a conductive structure 107 in the through hole 106 a to connect the substrate 104 and the redistribution structure 105 .

[0104] Specifically, the first encapsulation layer 106 may be patterned and etched by a photolithography process to form a through hole 106a. Fig.12 The through hole 106a exposes the metal wiring 105a in the redistribution structure 105, and then the through hole 106a is filled with a conductive material to form a conductive structure 107 connected to the metal wiring 105a in the redistribution structure 105 (refer to Fig.13 ) to achieve electrical connection. Optionally, before filling the conductive material, a barrier layer and / or adhesion layer is deposited in the through hole 106a. The material of the barrier layer or adhesion layer may include but is not limited to titanium, titanium oxide, titanium nitride, tantalum, tantalum nitride or other alternative materials; the material of the conductive structure 107 may include but is not limited to one or more of copper, titanium, tungsten, aluminum, gold, nickel, etc., or other alternative conductive materials. The barrier layer and / or adhesion layer can be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition or thermal oxidation. The above-mentioned etching can be dry etching or wet etching, etc., wherein the dry etching process can be reactive ion etching, ion beam etching, plasma etching, laser ablation or any combination of these methods.

[0105] In some embodiments, after forming the conductive structure 107, refer to Fig.13The formation method further includes S41: forming a plurality of first bump structures 108 arranged at intervals on the first packaging layer 106, the first bump structure 108 being connected to the conductive structure 107 and used to connect and integrate the substrate 104. The first bump structure 108 is formed on the conductive structure 107, is physically and electrically connected to the conductive structure 107, and is integrated with the substrate 104 to form a transmission line in which the substrate 104, the first bump structure 108, the conductive structure 107, and the metal wiring 105a of the redistribution structure 105 are sequentially connected. Among them, the formation method and material of the first bump structure 108 are similar to those of the aforementioned second bump structure 109, and are not described in detail.

[0106] In some embodiments, after S14, the forming method further includes:

[0107] S51: providing a substrate 104;

[0108] S52: Integrate the substrate 104 on one side of the second surface 101b of the interconnection device. The second surface 101b of the interconnection device is the side away from the first chip 102 and the second chip 103. The substrate 104 is physically separated from the interconnection device 101 and is electrically connected to the first chip 102 and the second chip 103 respectively.

[0109] Specifically, refer to Fig.14 The substrate 104 can be attached through the aforementioned first bump structure 108 and physically isolated from the interconnect device 101, and a transmission line between the substrate 104 and the first chip 102, or between the substrate 104 and the second chip 103 is formed through the first bump structure 108, the metal wiring 105a of the reconstructed wiring structure, the conductive structure 107, and the second bump structure in sequence.

[0110] Based on the packaging structure 100 and its formation method of the present application, the Z-direction spacing between the layer formed by the first chip 102 and the second chip 103 and the substrate 104 can be reduced to 40-150μm, preferably 40-85μm, which effectively improves the packaging density, reduces the signal transmission distance, and thereby reduces the resistance and increases the communication speed.

[0111] In some embodiments, after S52, the forming method further includes: forming a first filling structure 111 on the substrate 104 to fill the gap between the substrate 104 and the first encapsulation layer 106. Fig.14 , the first filling structure 111 covers the first bump structure.

[0112] Furthermore, a plurality of third bump structures 113 may be formed on the substrate 104. The plurality of third bump structures 113 are arranged at intervals on a side of the substrate 104 away from the interconnection device 101, so as to be used for electrical interconnection between the substrate 104 and other devices. Figure 1The package structure 100 is shown.

[0113] It can be understood that the above-mentioned embodiment of the package structure 100 and the embodiment of the method for forming the package structure 100 are based on the same application concept, and the package structure 100 can be manufactured by using the above-mentioned method for forming the package structure 100 .

[0114] On the other hand, the present application provides an integrated circuit, which includes an electronic device manufactured by the above-mentioned package structure 100 or the method for forming the package structure 100 .

[0115] On the other hand, the present application provides an electronic device, which includes an electronic device manufactured using the above-mentioned packaging structure 100 or the method for forming the packaging structure 100. The electronic device may include any electronic component such as an integrated circuit, an electronic device, etc. Since the working performance of the packaging structure 100 is better, the performance of the electronic device is correspondingly improved.

[0116] The electronic device of the embodiment of the present application can be selected from any electronic product or device such as a mobile phone, a personal digital assistant (PDA), a tablet computer (pad), a laptop computer, a game console, a television, a video compact disc (VCD), a digital video disc (DVD), a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a handheld game console (PlayStation Portable, PSP), etc., and can also be any intermediate product of the electronic device made of the above-mentioned packaging structure 100.

[0117] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0118] The above description has fully disclosed the specific implementation methods of the present application. It should be pointed out that any changes made by technicians familiar with the field to the specific implementation methods of the present application do not deviate from the scope of the claims of the present application. Accordingly, the scope of the claims of the present application is not limited to the above specific implementation methods.

Claims

1. A packaging structure, characterized in that: The packaging structure comprises: The interconnection device is a thinned bridge chip having a first surface and a second surface opposite to each other; A first chip is located on one side of the first surface of the interconnection device, and a projection surface of the first chip partially overlaps with the first surface of the interconnection device; The second chip is located on one side of the first surface of the interconnection device, the projection surface of the second chip partially overlaps with the first surface of the interconnection device, and the first chip and the second chip are electrically connected through the interconnection device.

2. The packaging structure according to claim 1, characterized in that: Also includes: The substrate is located on one side of the second surface of the interconnection device, is physically spaced apart from the interconnection device, and is electrically connected to the first chip and the second chip respectively.

3. The packaging structure according to claim 2, characterized in that: Also includes: a redistribution structure, which is in contact with the first surface of the interconnection device, and is located between the first chip and the first surface of the interconnection device, and between the second chip and the first surface of the interconnection device, wherein a projection area of ​​the redistribution structure on the substrate exceeds a projection area of ​​the interconnection device on the substrate; The interconnection device is electrically connected to the first chip and the second chip respectively through the rewiring structure, and the substrate is electrically connected to the first chip and the second chip respectively through the rewiring structure.

4. The packaging structure according to claim 3, characterized in that: Also includes: The first packaging layer is located between the substrate and the redistribution structure, covers the sidewalls of the interconnection device and exposes the first side and the second side of the interconnection device.

5. The packaging structure according to claim 4, characterized in that: A plurality of conductive structures arranged at intervals are disposed through the first packaging layer, and the conductive structures are used to connect the substrate and the redistribution structure.

6. The packaging structure according to claim 4, characterized in that: Also includes: A plurality of first bump structures are arranged at intervals between the first packaging layer and the substrate, and the first bump structures are respectively connected to the substrate and the conductive structure.

7. The packaging structure according to claim 3, characterized in that: Also includes: A plurality of second bump structures are arranged at intervals on a side of the rewiring structure away from the interconnection device, and are used to electrically connect the first chip and the rewiring structure, and to electrically connect the second chip and the rewiring structure.

8. The packaging structure according to claim 3, characterized in that: Also includes: The second packaging layer is stacked on the rewiring structure and is used to cover the side walls of the first chip and the second chip. The second packaging layer exposes a side of the first chip away from the rewiring structure and a side of the second chip away from the rewiring structure.

9. The packaging structure according to any one of claims 1 to 8, characterized in that: The bridge chip is a silicon bridge chip.

10. The packaging structure according to any one of claims 1 to 8, characterized in that: The thickness of the interconnection device is 2 μm to 15 μm.

11. The packaging structure according to any one of claims 1 to 8, characterized in that: The first chip is a logic chip, and the second chip is a memory chip.

12. A method for forming a packaging structure, characterized in that: The forming method comprises: Providing a first carrier, a bridge chip, a first chip and a second chip, wherein the bridge chip has a first surface and a second surface opposite to each other, and the second surface of the bridge chip is attached to the first carrier; Integrate the first chip and the second chip on one side of the first surface of the bridge chip, wherein the projection surface of the first chip partially overlaps with the first surface of the bridge chip, and the projection surface of the second chip partially overlaps with the first surface of the bridge chip; Peeling off the first carrier to expose the second side of the bridge chip; The bridge chip is thinned to form an interconnection device, and the first chip and the second chip are electrically connected through the interconnection device.

13. The forming method according to claim 12, characterized in that: After thinning the bridge chip to form an interconnection device, the forming method further includes: providing a substrate; The substrate is integrated on one side of the second surface of the interconnection device, the second surface of the interconnection device is the side away from the first chip and the second chip, the substrate is physically spaced from the interconnection device and is electrically connected to the first chip and the second chip respectively.

14. The forming method according to claim 12, characterized in that: The step of integrating the first chip and the second chip on one side of the first surface of the bridge chip comprises: forming a fitted redistribution structure on the first surface of the bridge chip, wherein a projection area of ​​the redistribution structure on the first carrier exceeds a projection area of ​​the bridge chip on the first carrier; The first chip and the second chip are respectively attached to a side of the rewiring structure away from the bridge chip; the bridge chip is electrically connected to the first chip and the second chip respectively through the rewiring structure.

15. The forming method according to claim 14, characterized in that: The step of attaching the first chip and the second chip to a side of the rewiring structure away from the bridge chip comprises: forming a plurality of second bump structures arranged at intervals on a side of the redistribution structure away from the bridge chip; The first chip and the second chip are attached to a side of the rewiring structure away from the bridge chip through the plurality of second bump structures, and the first chip and the second chip are electrically connected to the rewiring structure respectively through the second bump structures.

16. The forming method according to any one of claims 12 to 15, characterized in that: The step of attaching the second surface of the bridge chip to the first carrier chip comprises: Bonding the second surface of the bridge chip to the first carrier chip; An initial packaging layer is formed on the first carrier wafer, wherein the initial packaging layer covers the sidewalls of the bridge chip and exposes the first surface of the bridge chip.

17. The forming method according to claim 16, characterized in that: In the step of thinning the bridge chip to form an interconnection device, the initial packaging layer is thinned simultaneously to form a first packaging layer, wherein the first packaging layer covers the sidewalls of the interconnection device and exposes the first side and the second side of the interconnection device.

18. The forming method according to claim 17, characterized in that: After thinning the bridge chip to form an interconnection device, the forming method further includes: forming a plurality of through holes arranged at intervals in the first packaging layer; A conductive structure is formed in the through hole for connecting the substrate and the redistribution structure.

19. The forming method according to claim 18, characterized in that: The forming method further comprises: A plurality of first bump structures arranged at intervals are formed on the first packaging layer. The first bump structures are connected to the conductive structures and are used to connect and integrate the substrate.

20. The forming method according to any one of claims 12 to 15, characterized in that: Before peeling off the first carrier to expose the second surface of the bridge chip, the forming method further includes: providing a second slide; The second carrier is attached to a surface of the first chip and the second chip facing away from the bridge chip.

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