A method for preparing a miniaturized high-density three-dimensional packaging structure and the packaging structure

Abstract

The application relates to a preparation method of a miniaturized high-density three-dimensional packaging structure and the packaging structure, and the preparation steps comprise the following steps: providing a base material with vertical metal columns and etching a through groove to form a frame; being attached to a slide with a temporary bonding film; flip-chip A is in the through groove; after pre-preparing a chip adhesive film on the back of chip B, electroplating micro copper columns on the front, and being vertically mounted on the back of chip A; filling by adopting epoxy resin vacuum compression; removing the bonding by pyrolysis to form a resin-based wafer; preparing a dielectric layer and a metal layer on the front of the wafer, turning over and thinning to expose the micro copper columns, and then preparing a dielectric layer, a metal layer and solder balls on the back to complete single-layer packaging; and finally realizing three-dimensional integration through solder ball stacking. The application utilizes the frame through groove double-sided embedded chip and vertical interconnection structure, can be reduced by about 50% compared with planar integration, the insertion loss is reduced by about 1dB under the 30-100GHz frequency band, and the requirements of miniaturization, high-density heterogeneous integration of high-frequency micro systems are effectively met.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a method for fabricating a miniaturized, high-density three-dimensional packaging structure and the packaging structure thereof. Background Technology

[0002] With the rapid development of consumer electronics, 5G communications, and the Internet of Things (IoT), terminal applications are placing higher demands on the functionality, bandwidth, and energy consumption control of electronic systems. In consumer electronics, the functions of smartphones and smartwatches are continuously expanding, while the overall thickness of the devices is constantly being reduced. Multiple camera modules and large-capacity batteries are encroaching on the internal space of these devices. In 5G radio frequency (RF) scenarios, the RF front-end needs to be compatible with more communication frequency bands, resulting in a significant increase in the number of integrated RF components. Therefore, the industry has an urgent need for miniaturized and high-density chip and packaging structures.

[0003] As Moore's Law continues to slow, the challenge of improving chip performance and reducing production costs solely by shrinking process nodes is steadily increasing. Against this backdrop, advanced packaging technologies that leverage chip integration and 3D stacking have become the core technological path to achieving miniaturized and high-density integration of modules.

[0004] Currently, the mainstream packaging solutions mainly include the following two types: 1. The CoWoS packaging solution arranges multiple chips in parallel, interconnects them with an interposer through bump bonding, and then the entire structure is further bump-bonded to the substrate to complete the packaging process. This solution introduces an interposer interconnect structure, which can significantly improve the packaging density.

[0005] Second, the EMIB packaging solution is adopted, in which silicon bridge chips are pre-embedded during the substrate preparation stage. Each chip is soldered to the surface of the silicon bridge through bumps and then encapsulated. This solution can also significantly improve the packaging integration density by utilizing the silicon bridge structure.

[0006] However, in high-frequency phased array applications, multiple packages need to be arrayed within a limited area. The antenna size and array spacing are fixed and tiny, and the effective integration area that the chip can set is very limited. The above two solutions cannot further improve the integration density within a limited area, making it difficult to meet the miniaturization and high integration requirements of high-frequency phased array devices. Summary of the Invention

[0007] Therefore, the purpose of this invention is to provide a three-dimensional packaging method and a packaging structure for finished products that meet the requirements of miniaturized high-density projects, so as to solve the problem that existing packaging solutions cannot achieve ultra-high-density chip integration within a limited area.

[0008] To address the aforementioned technical problems, this invention provides a method for fabricating a miniaturized, high-density three-dimensional packaging structure, comprising the following steps: Step S1: Provide a substrate with vertical metal columns, form through grooves in the substrate to obtain a frame structure, wherein the position of the through grooves does not overlap with the vertical metal columns; Step S2: The frame structure is attached to a temporary carrier sheet, the surface of which has a temporary bonding film, and the temporary bonding film is a heat-release tape or a UV-release tape. Step S3: Flip-mount chip A into the through slot of the frame structure; Step S4: Pre-fabricate a chip bonding film on the back side of chip B, and electroplate micro copper pillars on the front side; Step S5: Mount chip B onto the back of chip A in a positive orientation; Step S6: Cover the temporary carrier with epoxy resin material, fill the through groove through vacuum pressing process, and remove the temporary bonding film by pyrolysis to separate the temporary carrier from the resin material to form a resin-based disc; Step S7: Prepare a dielectric layer and a metal layer on the front side of the resin-based wafer; Step S8: Flip the resin-based wafer and mechanically grind it until the micro copper pillars on the back are exposed. Prepare the dielectric layer, metal layer and solder balls on the back to complete the preparation of the single-layer package. Step S9: The single-layer package is stacked with solder balls to complete the three-dimensional integration of heterogeneous chips.

[0009] In one embodiment of the present invention, the substrate is made of any one of silicon, glass, resin, or a mixture of resin and glass fiber, and the thickness is at least 200 μm.

[0010] In one embodiment of the present invention, the diameter of the vertical metal column is 30-250 μm, and the metal in the vertical metal column is copper or tungsten.

[0011] In one embodiment of the present invention, the through groove is prepared by mechanical, laser, dry or wet process, and the shape of the through groove is circular, square or arbitrary.

[0012] In one embodiment of the present invention, the chip A is made of silicon, germanium silicon, gallium arsenide, gallium nitride, silicon carbide, indium phosphide, ceramic or glass, and is an active device, a passive device or a MEMS device, with a minimum thickness of 50 μm and a minimum size of 0.5 × 0.5 mm².

[0013] In one embodiment of the present invention, the thickness of the chip bonding film in chip B is 10-50 μm, and the minimum spacing between the micro copper pillars is 70 μm; the size of chip B is smaller than the size of chip A, and the size of chip A is smaller than the size of the through slot.

[0014] In one embodiment of the present invention, the sum of the thicknesses of chip A, chip B, chip bonding film, and micro copper pillars is less than the thickness of the frame structure.

[0015] In one embodiment of the present invention, the current density of electroplating in step S4 is 1-10 ASD and the electroplating temperature is 30-50℃; after mechanical grinding and thinning in step S8, the surface roughness of the resin material is 40-300nm.

[0016] In one embodiment of the present invention, the pyrolysis temperature in step S6 is 150-200°C, the heating rate is 60°C / min, and the process does not require a vacuum environment; the dielectric layer in steps S7 and S8 is polyimide, prepared by spin coating or dry film lamination process, and the metal layer is copper, prepared by electroplating method.

[0017] The present invention also provides a miniaturized high-density packaging structure prepared according to any of the above-described three-dimensional packaging structure preparation methods.

[0018] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: The three-dimensional packaging structure fabrication method of the present invention can achieve ultra-high density integration of heterogeneous chips within a limited area. For high-frequency phased array applications, it is necessary to achieve antenna array arrangement and multi-package integration within a limited area. Within a single package, heterogeneous chips can be embedded on both sides of the frame slot, meeting the requirements for multi-chip integration; simultaneously, multiple types of passive devices can be mounted, significantly shortening the interconnection distance between passive devices and active chips, reducing parasitic capacitance and inductance, and effectively reducing transmission loss; furthermore, by utilizing the vertical interconnection structure inside the frame, interconnection between the front and back sides of the package can be achieved, and multiple packages can be stacked using solder balls to achieve three-dimensional integrated packaging, further significantly improving chip integration density. Attached Figure Description

[0019] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0020] Figure 1 This is a schematic diagram of the substrate in this invention; Figure 2 This is a schematic diagram of a through groove formed in the substrate described in this invention; Figure 3 This is a schematic diagram of the substrate being mounted onto the carrier sheet in this invention; Figure 4 This is a schematic diagram of chip A being mounted into a through groove in a substrate; Figure 5 This is a schematic diagram of mounting chip B onto chip A; Figure 6 This is a schematic diagram of the resin material covering the carrier and pyrolysis described in this invention; Figure 7This is a schematic diagram of the preparation of the dielectric layer and metal layer on the front side of the resin-based disc in this invention; Figure 8 This is a schematic diagram of the thinning of the back side of the resin-based disc described in this invention; Figure 9 This is a schematic diagram of the preparation of a dielectric layer, a metal layer, and the growth of solder balls on the back side of the resin-based wafer described in this invention; Figure 10 This is a schematic diagram of the multi-layer stacked package in this invention.

[0021] As shown in the figure, 101: Vertical metal pillar; 102: Substrate; 103: Through groove; 104: Frame structure; 105: Temporary carrier; 106: Chip A; 107: Chip B; 108: Chip bonding film; 109: Micro copper pillar; 110: Resin-based wafer; 111: Dielectric layer; 112: Metal layer; 113: Solder ball. Detailed Implementation Example 1

[0022] This embodiment provides a method for fabricating a miniaturized, high-density three-dimensional packaging structure. The specific fabrication steps are as follows: First, a glass substrate (102) with vertical copper pillars (101) is provided, the plane of which is as follows: Figure 1 As shown, the minimum thickness of the glass substrate is 200 μm, and the minimum diameter of the vertical copper pillar is 30 μm. Two square through-grooves (103) are formed in the glass substrate to obtain a frame structure (104), the plane of which is as shown. Figure 2 As shown. The position of the through groove (103) does not overlap with the vertical metal column (101). Specifically, the through groove (103) can be formed by laser drilling process to ensure the verticality of the hole wall and the quality of the sidewall.

[0023] Next, as Figure 3 As shown, a glass frame structure (104) is attached to a temporary carrier (105), the surface of which has a temporary bonding film. Preferably, the temporary bonding film is a heat-release tape or a UV-release tape. If the carrier is a transparent material such as glass, UV-release tape or heat-release tape can be used; if the carrier is a non-transparent material such as steel plate, only heat-release tape can be used.

[0024] Please see Figure 4 Chip A (106) is flip-chip mounted into the through slot (103) of the glass frame structure. Chip A (106) can be a chip of any material, thickness, and function. Preferably, the material of chip A (106) is silicon, germanium silicon, gallium arsenide, gallium nitride, silicon carbide, indium phosphide, ceramic, or glass, and the type may include active devices, passive devices, or MEMS devices, etc., with a minimum thickness of 50 μm and a minimum size of 0.5 × 0.5 mm².

[0025] A chip bonding film (108) is prefabricated on the back of chip B (107), and electroplated micro copper pillars (109) are prefabricated on the front. Chip B (107) can be any material, thickness, and function. Specifically, the electroplating solution for the micro copper pillars (109) mainly contains copper sulfate, sulfuric acid, chloride ions, and additives; the electroplating current density is 1-10 ASD; and the electroplating temperature is 30-50℃. Preferably, the thickness of the chip bonding film (108) is 10-50 μm, and the minimum spacing between the micro copper pillars (109) is 70 μm.

[0026] like Figure 5 As shown, chip B (107) is mounted upright on the back of chip A (106). To ensure flatness and reliability of the integration, preferably, the size of chip B (107) is smaller than the size of chip A (106), and the size of chip A (106) is smaller than the size of the through slot (103). At the same time, the sum of the thicknesses of chip A (106), chip B (107), chip bonding film (108), and micro copper pillar (109) must be less than the thickness of the glass frame structure (104).

[0027] Continue reading Figure 6 A temporary carrier (105) is covered with epoxy resin material. During epoxy resin filling, a vacuum pressing process is used to avoid defects such as bubbles and ensure the quality of the filling; preferably, the thickness of the resin material is greater than the thickness of the substrate (102). Then, the temporary bonding film is removed by pyrolysis, separating the temporary carrier (105) from the resin material to form a resin-based disc (110). Specifically, the pyrolysis process conditions are: pyrolysis temperature 150-200℃, heating rate 60℃ / min, and maintaining a constant temperature after reaching the desired temperature. This pyrolysis process does not require a vacuum environment.

[0028] like Figure 7 As shown, a dielectric layer (111) and a metal layer (112) are prepared on the front side of a resin-based disc. The dielectric layer (111) is made of an organic material such as polyimide and can be prepared by spin coating or dry film lamination. The metal layer (112) is made of copper and is prepared by electroplating.

[0029] like Figure 8 As shown, the resin-based disc (110) is flipped over and thinned until the micro-copper pillars (109) on the back side are exposed. The thinning process is mainly achieved by mechanical grinding, including rough grinding and fine grinding processes. The surface roughness of the resin material after thinning is controlled at 40-300 nm.

[0030] like Figure 9 As shown, a dielectric layer (111), a metal layer (112), and solder balls (113) are then fabricated on the back side to complete the fabrication of the single-layer package. Finally, different single-layer packages are stacked using solder balls (113) to complete the final product. Figure 10The three-dimensional integration of heterogeneous core particles is shown.

[0031] Corresponding to the above preparation method, the miniaturized high-density three-dimensional packaging structure finally obtained in this embodiment has the following characteristics: The packaging structure includes a frame structure (104), which has vertical metal pillars (101) and a through groove (103) inside; Chip A (106) is flip-chip attached to the bottom layer in the through groove (103); Chip B (107) is upright attached to the back of Chip A (106) through a chip bonding film (108), and micro copper pillars (109) are provided on the front of Chip B (107); epoxy resin layer A resin-based wafer (110) is formed by filling the through-slot (103) and covering the chip and frame structure. The resin-based wafer (110) has a dielectric layer (111) and a metal layer (112) on its front and back sides, respectively. The metal layer (112) on the front side is electrically connected to the vertical metal pillars (101), and the metal layer (112) on the back side is electrically connected to the micro copper pillars (109). Solder balls (113) are disposed on the metal layer (112) on the back side for three-dimensional stacking interconnection between multi-level packages. This structure achieves ultra-high density heterogeneous integration through vertical interconnection inside the frame and double-sided embedded chip stacking.

[0032] Compared to other planar heterogeneous integration solutions, the package structure fabricated using the method of this invention is expected to reduce the planar area by 50%. When used in the radio frequency field, in the 30-100 GHz band, the insertion loss is expected to be reduced by approximately 1 dB, exhibiting excellent high-frequency performance and ultra-high integration density.

[0033] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for fabricating a miniaturized, high-density three-dimensional packaging structure, characterized in that, Includes the following steps: Step S1: Provide a substrate (102) with vertical metal columns (101), form a through groove (103) in the substrate (102) to obtain a frame structure (104), wherein the position of the through groove (103) does not overlap with the vertical metal column (101); Step S2: The frame structure (104) is attached to a temporary carrier (105), the surface of which is covered with a temporary bonding film, and the temporary bonding film is a heat-release tape or a UV-release tape. Step S3: Flip-mount chip A (106) onto the slot (103) of the frame structure (104); Step S4: Pre-fabricate a chip bonding film (108) on the back side of chip B (107) and electroplate micro copper pillars (109) on the front side. Step S5: Mount chip B (107) onto the back of chip A (106) in a positive orientation; Step S6: Cover the temporary carrier (105) with epoxy resin material, fill the through groove through vacuum pressing process, and remove the temporary bonding film by pyrolysis to separate the temporary carrier (105) from the resin material to form a resin-based disc (110). Step S7: Prepare a dielectric layer (111) and a metal layer (112) on the front side of the resin-based disc (110). Step S8: Flip the resin-based wafer (110) and cut it thin by mechanical grinding until the micro copper pillars (109) on the back are exposed. Prepare a dielectric layer (111), a metal layer (112) and solder balls (113) on the back to complete the preparation of the single-layer package. Step S9: Stack the single-layer package using solder balls (113) to complete the three-dimensional integration of heterogeneous chips.

2. The method for fabricating a three-dimensional packaging structure according to claim 1, characterized in that: The substrate (102) is made of any one of silicon, glass, resin or a mixture of resin and glass fiber, and has a minimum thickness of 200 μm.

3. The method for fabricating a three-dimensional packaging structure according to claim 1, characterized in that: The diameter of the vertical metal column (101) is 30-250 μm, and the metal in the vertical metal column (101) is copper or tungsten.

4. The method for fabricating a three-dimensional packaging structure according to claim 1, characterized in that: The through groove (103) is prepared by mechanical, laser, dry or wet process, and the shape of the through groove (103) is circular, square or arbitrary.

5. The method for fabricating a three-dimensional packaging structure according to claim 1, characterized in that: Chip A (106) is made of silicon, germanium silicon, gallium arsenide, gallium nitride, silicon carbide, indium phosphide, ceramic or glass, and is an active device, a passive device or a MEMS device. The minimum thickness is 50um and the minimum size is 0.5×0.5mm².

6. The method for fabricating a three-dimensional packaging structure according to claim 1, characterized in that: The thickness of the chip bonding film (108) in chip B (107) is 10-50um, and the minimum spacing of the micro copper pillars (109) is 70um; the size of chip B (107) is smaller than that of chip A (106), and the size of chip A (106) is smaller than that of the through slot (103).

7. The method for fabricating a three-dimensional encapsulation structure according to claim 1, characterized in that: Furthermore, the sum of the thicknesses of chip A (106), chip B (107), chip bonding film (108), and micro copper pillar (109) is less than the thickness of the frame structure (104).

8. The method for fabricating a three-dimensional packaging structure according to claim 1, characterized in that: The current density of electroplating in step S4 is 1-10 ASD, and the electroplating temperature is 30-50℃; after mechanical grinding and thinning in step S8, the surface roughness of the resin material is 40-300nm.

9. The method for fabricating a three-dimensional packaging structure according to claim 1, characterized in that: The pyrolysis temperature in step S6 is 150-200℃, the heating rate is 60℃ / min, and the process does not require a vacuum environment; the dielectric layer (111) in steps S7 and S8 is polyimide, which is prepared by spin coating or dry film lamination process, and the metal layer (112) is copper metal, which is prepared by electroplating method.

10. A miniaturized high-density packaging structure prepared by the three-dimensional packaging structure preparation method according to any one of claims 1-9.

Images