Improved step coverage and damage control pulsed voltage waveform delivery

Abstract

Embodiments of the present disclosure include a method for manufacturing a semiconductor component, the method comprising: forming a first layer on a surface of a substrate comprising a plurality of features formed in the substrate using a physical vapor deposition (PVD) process within a PVD chamber, wherein forming the first layer comprises applying a bias to a target within the processing chamber; and etching at least a portion of the first layer within the PVD chamber. The etching process comprises: applying a substrate bias to an electrode disposed within a substrate support proximate a substrate receiving surface, wherein applying the substrate bias comprises delivering a pulsed voltage (PV) waveform to the electrode; and exposing the substrate to a plasma generated within the PVD chamber.

Description

background Technical Field

[0001] Embodiments of this disclosure generally relate to a substrate processing method. More specifically, embodiments of this disclosure relate to a method for improving step coverage and damage control using pulsed voltage waveforms. Background Technology

[0002] The semiconductor device manufacturing field continues to evolve as new materials, processes, and equipment develop to meet the growing demand for smaller, faster, and more complex components. One challenge in device manufacturing is the need for high-quality, uniform, and precise deposition of thin films from a wide variety of materials. Another challenge is the reliable production of high aspect ratio features.

[0003] Physical vapor deposition (PVD) is a common technique for depositing thin films of various metals and metal alloys. However, PVD deposition can damage the underlying layers of the substrate, especially when using high-energy ions to increase the deposition rate or when the substrate features are small and have a high aspect ratio. This damage can lead to poor step coverage and other defects, which can compromise the performance and reliability of the device. Furthermore, when depositing thin films on high aspect ratio features, the film material may form steps, overhangs, or other undesirable geometries in portions or entirely of the high aspect ratio feature. Including overhangs that create suboptimal film profiles, these overhangs can also obstruct or reduce deposition of the lower portions of the high aspect ratio feature. Therefore, improvements in step coverage and damage control are needed in the art. Summary of the Invention

[0004] Embodiments of this disclosure generally relate to a substrate processing method. More specifically, this embodiment relates to a method for improving step coverage and damage control in physical vapor deposition (PVD) processes using pulsed voltage waveforms.

[0005] Embodiments of this disclosure include a method for manufacturing a semiconductor device, comprising: forming a first layer on a surface of a substrate comprising a plurality of features formed therein using a physical vapor deposition process within a physical vapor deposition chamber, wherein forming the first layer includes applying a bias voltage to a target material within a processing chamber; and etching at least a portion of the first layer within the physical vapor deposition chamber. The etching process includes: applying a substrate bias voltage to electrodes disposed within a substrate support near a substrate receiving surface, wherein applying the substrate bias voltage includes transmitting a pulsed voltage (PV) waveform to the electrodes; and exposing the substrate to plasma generated within the physical vapor deposition chamber.

[0006] Embodiments of this disclosure include a method of manufacturing a semiconductor device, comprising: forming a first layer on a surface of a substrate including a plurality of features formed therein within a first physical vapor deposition (PVD) chamber, wherein forming the first layer includes applying a bias voltage to a target within the first PVD chamber; transferring the substrate from the first PVD chamber to a second PVD chamber; and etching at least a portion of the first layer within the second PVD chamber. The etching process includes: applying a substrate bias voltage to electrodes disposed within a substrate support near a substrate receiving surface, wherein applying the substrate bias voltage includes transmitting a PV waveform to the electrodes; and exposing the substrate to plasma generated within the second PVD chamber. Attached Figure Description

[0007] To gain a more detailed understanding of the features described above, reference can be made to embodiments of the present disclosure, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings are merely exemplary embodiments and should not be construed as limiting their scope, and may allow for other equally effective embodiments.

[0008] Figure 1 The figure shows a schematic top view of a multi-chamber processing system according to one or more embodiments described herein.

[0009] Figure 2 It is a cross-sectional view of a chamber according to one or more embodiments described herein.

[0010] Figure 3 The illustration is a process flow diagram of a method according to one or more embodiments described herein.

[0011] Figure 4A The illustration shows a voltage waveform established on a substrate due to a voltage waveform applied to an electrode in a processing chamber, according to one or more embodiments described herein.

[0012] Figure 4B It is a diagram of an IED function (IEDF) according to one or more embodiments described herein.

[0013] Figures 5A to 5D The illustrations depict various aspects of different chamber processing modes according to one or more embodiments described herein.

[0014] To facilitate understanding, the same reference numerals have been used as much as possible to identify common elements in the figures. It is anticipated that elements and features of one embodiment may be advantageously incorporated into other embodiments without further description. Detailed Implementation

[0015] Embodiments of this disclosure generally relate to a substrate processing method. More specifically, embodiments of this disclosure relate to a method for improving step coverage and damage control using pulsed voltage waveforms.

[0016] Physical vapor deposition (PVD) is a common technique for depositing thin films of various metals and metal alloys. However, PVD deposition can damage the underlying layers of the substrate, especially when using high-energy ions to increase the deposition rate or when the substrate features are small and have a high aspect ratio. This damage can lead to poor step coverage and other defects, which can compromise the performance and reliability of the device. Furthermore, when depositing thin films over high aspect ratio features, the film material may form steps, overhangs, or other undesirable geometries over a portion or the entire high aspect ratio feature. Overhangs, including suboptimal film profiles, can also obstruct or reduce deposition of the lower portion of the high aspect ratio feature. Therefore, there is a need in the art for improved step coverage and damage control.

[0017] Example processing system

[0018] Figure 1 This is a schematic top view of an exemplary processing system 100 (also referred to as a "processing platform") according to certain embodiments. The processing system 100 generally includes a device front-end module (EFEM) 102 for loading a substrate into the processing system 100; a first load-locking chamber 104 coupled to the EFEM 102; a transfer chamber 108 coupled to the first load-locking chamber 104; and a plurality of other chambers coupled to the transfer chamber 108, as detailed below. The EFEM 102 generally includes one or more robots 105 configured to transfer a substrate from a FOUP 103 to at least one of the first load-locking chamber 104 or a second load-locking chamber 106. The processing system 100, proceeding counterclockwise from the buffer portion 108A of the first load-locking chamber 104 around the transfer chamber 108, includes a first degassing chamber 109, a first pre-cleaning chamber 110, a first through chamber 112, a second through chamber 113, a second pre-cleaning chamber 114, a second degassing chamber 116, and a second load-locking chamber 106. The buffer portion 108A of the transfer chamber 108 includes a first robot 115 configured to transfer a substrate to each of the load-locking chambers 104, 106, the degassing chambers 109, 116, the pre-cleaning chambers 110, 114, and the through chambers 112, 113.

[0019] The rear end portion 108B of the transfer chamber 108 includes a second robot 135 configured to transfer a substrate to each of the through chambers 112, 113 and the processing chambers coupled to the rear end portion 108B of the processing system 100. These processing chambers may include a first processing chamber 132, a second processing chamber 134, a third processing chamber 136, and a fourth processing chamber 138. Generally, processing chambers 132, 134, 136, and 138 may include at least one of the following: atomic layer deposition (ALD) chambers, chemical vapor deposition (CVD) chambers, physical vapor deposition (PVD) chambers, etching chambers, degassing chambers, annealing chambers, and other types of semiconductor substrate processing chambers. In some embodiments, one or more of processing chambers 132, 134, 136, and 138 are PVD chambers similar to the configuration of processing chamber 200 described below.

[0020] The buffer portion 108A and the rear portion 108B of the transfer chamber 108, as well as each chamber coupled to the transfer chamber 108, are maintained under vacuum. As used herein, the term "vacuum" may refer to a pressure below 760 Torr and will typically be maintained close to 10. -5 Torr (approximately 10) -3 The pressure range is within the range of 10 Pa. However, some high vacuum systems may be able to operate below close to 10 Pa. - 7 Torr (approximately 10) -5 Operation at (Pa). In some embodiments, a roughing pump and / or turbomolecular pump coupled to each of the transfer chamber 108 and one or more processing chambers (e.g., processing chambers 109-138) is used to generate a vacuum. However, other types of vacuum pumps are also contemplated.

[0021] System controller 126, such as a programmable computer, is coupled to processing system 100 to control one or more components within the processing system. For example, system controller 126 may control the operation of processing chamber 200, as described later. In operation, system controller 126 enables data fetching and feedback from appropriate components to coordinate processing within processing system 100. System controller 126 includes a programmable central processing unit (CPU) 152, which is operable using memory 154 (e.g., non-volatile memory) and support circuitry 156. Support circuitry 156 (e.g., cache, clock circuitry, input / output subsystems, power supply, etc., and combinations thereof) is typically coupled to CPU 152 and to various components within processing system 100.

[0022] In some implementations, CPU 152 is any form of general-purpose computer processor used in an industrial environment, such as a programmable logic controller (PLC), to control various monitoring system components and subprocessors. Memory 154 is coupled to CPU 152, is non-transient, and is typically one or more of the following: easily accessible memory, such as random access memory (RAM), read-only memory (ROM), floppy disk drive, hard disk, or any other form of digital storage device, whether local or remote.

[0023] In this document, memory 154 is in the form of a computer-readable storage medium (e.g., non-volatile memory) containing instructions that, when executed by CPU 152, facilitate the operation of processing system 100. The instructions in memory 154 are in the form of a program product, such as a program implementing the methods of this disclosure (e.g., middleware application, device software application, etc.). The program code may conform to any of a variety of different programming languages. In one embodiment, this disclosure may be implemented as a program product stored on a computer-readable storage medium for use by a computer system. The program of the program product defines the functionality of such embodiments (including the methods described herein). Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media (e.g., read-only memory devices within a computer, such as CD-ROM disks readable by a CD-ROM drive, flash memory, ROM chips, or any type of solid-state non-volatile semiconductor memory) on which information is permanently stored; and (ii) writable storage media (e.g., floppy disks or hard disk drives within a disk drive, or any type of solid-state random access semiconductor memory) on which changeable information is stored. Such computer-readable storage media constitute an embodiment of this disclosure when carrying computer-readable instructions that direct the functionality of the methods described herein.

[0024] Processing chamber examples

[0025] Figure 2An exemplary processing chamber 200 is shown, having an upper processing assembly 208, a processing sleeve 250, and a base assembly 220, all configured to process a substrate 205 disposed in a processing region 210. The processing sleeve 250 includes an integrally formed grounding shield 260, a deposition ring 268, a cover ring 270, and an isolation ring assembly 280. In the illustrated version, the processing chamber 200 includes a sputtering chamber, also referred to as a PVD chamber, capable of depositing single or multiple components of material from a sputtering target 232 onto the substrate 205. Processing chamber 200 can also be used to deposit aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), zirconium (Hf), silver (Ag), chromium (Cr), gold (Au), molybdenum (Mo), silicon (Si), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), lanthanum (La), and alumina (AlO). x lanthanum oxide (LaO) x Nickel-platinum alloys (NiPt) and titanium (Ti), or combinations thereof. Such processing chambers are available from Applied Materials, Inc., located in Santa Clara, California. Other processing chambers, including equipment from other manufacturers, are anticipated to be adapted to benefit from one or more embodiments described in this disclosure.

[0026] Processing chamber 200 includes a chamber body 201 having sidewalls 204, a bottom wall 206, and an upper processing assembly 208, which encloses a processing region 210 or plasma region. The chamber body 201 is typically made of welded stainless steel sheet or a single piece of aluminum. In one embodiment, the sidewalls are made of aluminum, while the bottom portion of the chamber includes one or more walls formed of stainless steel sheet. The sidewalls 204 typically have a slit valve (not shown) to allow a substrate 205 to enter and exit the processing chamber 200. Components in the upper processing assembly 208 of the processing chamber 200 work in conjunction with a grounding shield 260, a base assembly 220, and a cover ring 270 to confine the plasma formed in the processing region 210 to the area above the substrate 205.

[0027] The base assembly 220 is supported by the bottom wall 206 of the processing chamber 200. During processing, the base assembly 220 supports the deposition ring 268 and the substrate 205. The base assembly 220 is coupled to the bottom wall 206 of the processing chamber 200 via a lifting mechanism 222 configured to move the base assembly 220 between an upper processing position and a lower transfer position. Furthermore, in the lower transfer position, a lifting rod 223 moves through the base assembly 220 to position the substrate at a distance from the base assembly 220, facilitating substrate exchange with a substrate transfer mechanism (such as a single-blade robot (not shown)) located outside the processing chamber 200. Typically, a bellows 224 is provided between the base assembly 220 and the bottom wall 206 to isolate the processing area 210 from the interior of the base assembly 220 and the exterior of the chamber.

[0028] The base assembly 220 typically includes a support member 226 that is hermetically coupled to a platform housing 228. The platform housing 228 is typically made of a metallic material such as stainless steel or aluminum. A cooling plate (not shown) is typically disposed within the platform housing 228 to enable thermal regulation of the support member 226.

[0029] The support member 226 may be made of aluminum or ceramic. The substrate support member 226 has a substrate receiving surface 227 that receives and supports the substrate 205 during processing, and the substrate receiving surface 227 is substantially parallel to the sputtering surface 233 of the sputtering target 232. The support member 226 also has a periphery 229 that terminates before the cantilever edge 205A of the substrate 205. The support member 226 may be an electrostatic chuck, a ceramic body, a heater, or a combination thereof. In one embodiment, the support member 226 is an electrostatic chuck in which a dielectric body with electrodes 226A is embedded. This dielectric body is typically made of a dielectric material with high thermal conductivity, such as pyrolytic boron nitride, aluminum nitride, silicon nitride, bauxite, or equivalent materials. Other aspects of the base assembly 220 and the support member 226 are further described below. In one embodiment, electrode 226A is configured such that when a DC voltage is applied to electrode 226A via electrostatic chuck power supply 243, substrate 205 disposed on substrate receiving surface 227 will be electrostatically clamped to substrate receiving surface, thereby improving heat transfer between substrate 205 and support 226. In one embodiment, bias source 241 is electrically coupled to electrode 226A and configured to generate a pulsed voltage signal (hereinafter referred to as pulsed voltage signal) containing a pulsed voltage (PV) waveform. Figure 4A and Figure 4B (as described in the text) so that a pulsed voltage signal can be provided to the substrate during processing to influence and control the interaction between the plasma and the surface of the substrate 205.

[0030] The system controller 126 can read a program (or computer instructions) that determines which tasks can be performed on the substrate. Preferably, the program is software readable by the system controller 126 that contains code for performing monitoring, execution, and control of movement, as well as various processing formulation tasks and steps performed within the processing system 100 and processing chamber 200. For example, the system controller 126 may contain program code including a substrate positioning instruction set for operating the base assembly 220; a gas flow control instruction set for operating a gas flow control valve to set the flow rate of sputtering gas to the processing chamber 200; a pressure control instruction set for operating a throttle valve or gate valve to maintain pressure within the processing chamber 200; a temperature control instruction set for controlling a temperature control system (not shown) within the base assembly 220 or sidewall 204 to set the temperature of the substrate or sidewall 204 respectively; and a process monitoring instruction set for monitoring the processing within the processing chamber 200.

[0031] Processing chamber 200 also includes processing sleeve 250, which contains various components that can be easily removed from processing chamber 200, for example, for cleaning sputtering deposits from component surfaces, replacing or repairing eroded components, or adapting processing chamber 200 to other processes. In one embodiment, processing sleeve 250 includes an isolation ring assembly 280, a grounding shield 260, and a deposition ring 268 for placement around a periphery 229 of support 226, which terminates before the overhanging edge of substrate 205.

[0032] The upper processing assembly 208 may also include an RF source 281, a direct current (DC) source 282, an adapter 202, a motor 293, and a cover assembly 230. The cover assembly 230 generally includes a sputtering target 232, a magnetron system 289, and a cover housing 291. When in the closed position, the upper processing assembly 208 is supported by sidewalls 204, such as... Figure 2 As shown. A ceramic target isolator 236 is disposed between the isolation ring assembly 280, the sputtering target 232, and the adapter 202 of the cap assembly 230 to prevent vacuum leakage therebetween. The adapter 202 is sealingly coupled to the sidewall 204 and is configured to assist in the removal of the upper processing assembly 208 and the isolation ring assembly 280.

[0033] When in the processing position, the sputtering target 232 is positioned near the adapter 202 and exposed to the processing area 210 of the processing chamber 200. The sputtering target 232 contains material deposited onto the substrate 205 during a PVD or sputtering process. An isolation ring assembly 280 is disposed between the sputtering target 232 and the shield 260 and the chamber body 201, thereby electrically isolating the sputtering target 232 from the shield 260 and the chamber body 201.

[0034] During processing, the sputtering target 232 is biased relative to the grounded region of the processing chamber (e.g., chamber body 201 and adapter 202) by a power source disposed in the RF source 281 and / or the DC source 282. It is believed that during high-voltage PVD processes, by delivering RF energy and DC power to the sputtering target 232, significant process advantages over conventional low-voltage DC plasma processing techniques can be achieved when used in conjunction with sputtering materials such as, to name only, titanium, copper, nickel, platinum, aluminum, tantalum, molybdenum, and tungsten. In one embodiment, the RF source 281 includes an RF power supply 281A and an RF matcher 281B, configured to efficiently deliver RF energy to the sputtering target 232. In one example, the RF power supply 281A is capable of generating an RF current at a power between approximately 0 kW and approximately 5 kW at a frequency between approximately 13.56 MHz and approximately 228 MHz. In another example, the DC power supply 282A in the DC source 282 is capable of delivering DC power between approximately 0 kW and approximately 50 kW.

[0035] The central portion of the processing chamber 200 includes an induction coil assembly 255 positioned within the central region of the processing assembly 250 and configured to form an inductively coupled plasma 211 during processing. This inductively coupled plasma is used to ionize atoms ejected from the sputtering target 232 and / or ionize the processing gas disposed within the processing region 210 during processing. The induction coil assembly 255 includes an RF power supply 256 and an impedance matching device 257, which are coupled to an RF coil 258 disposed within the central portion of the processing region 210 of the processing chamber 200. In some embodiments, the RF coil 258 is positioned at a vertical midpoint in the processing region 210, or at a location between the vertical midpoint and the surface of the substrate 205. The vertical midpoint is defined as the midpoint distance between the substrate receiving surface 227 of the base assembly 220 and the target 232. In some embodiments, the RF coil 258 comprises a single-turn coil made of metal, wherein a first end of the single-turn coil is coupled to the RF power supply 256 via an impedance matching device 257, and a second end is coupled to a ground reference. In one configuration, the RF coil 258 is formed of a conductive material made of the same material as the sputtering target 232. In some configurations, the RF power supply 256 is capable of generating RF current in the RF coil 258 at a frequency between about 13.56 MHz and about 228 MHz with a power between about 0 kW and about 5 kW.

[0036] In some embodiments, the processing chamber 200 also includes one or more auxiliary electromagnet assemblies, such as a first electromagnet assembly 261, a second electromagnet assembly 263, and a third electromagnet assembly 265, which are vertically aligned around the processing chamber. In some embodiments, the first, second, and third electromagnet assemblies each include an independent current source so that each assembly can individually generate a magnetic field configured to limit and / or control the movement of electrons and ions generated in the plasma formed in the processing region 210 of the processing chamber.

[0037] In some embodiments, the first electromagnet assembly 261 includes a first current source 261A configured to bias a first magnetic coil assembly 261B. The first magnetic coil assembly 261B is positioned near the sputtering target 232 and configured to regulate the magnetron-controlled plasma 213. The second electromagnet assembly 263 includes a second current source 263A configured to bias a second magnetic coil assembly 264B. The second magnetic coil assembly 264B is positioned adjacent to the induction coil assembly 255 and configured to regulate the inductively coupled plasma 211. The third electromagnet assembly 265 includes a third current source 265A configured to bias a third magnetic coil assembly 265B. The third magnetic coil assembly 265B is positioned near the support 226 and configured to regulate the plasma near the surface of the substrate 205. In some configurations, the first current source 261A, the second current source 263A, and the third current source 265A are capable of generating DC or RF current or voltage at a power between about 0 kW and about 5 kW.

[0038] In operation, one or more electromagnet assemblies 261, 263, and 265 are vertically distributed and positioned outside the processing unit 250 to generate a magnetic field within the processing region 210 to help modify and / or shape the radial distribution of plasma formed within the processing region 210 during processing. In some embodiments, the one or more electromagnet assemblies include a single electromagnet, a pair of electromagnets, or a quadruple electromagnet array. The quadruple electromagnet array includes four solenoid coils that are generally circularly symmetrically wrapped around the central axis 294 of the processing chamber 200. In one configuration, the four electromagnets are configured as a top inner electromagnet (TIM), a top outer electromagnet (TOM), a bottom inner electromagnet (BIM), and a bottom outer electromagnet (BOM) (not shown). The magnetic field generated by the quadruple electromagnet array is adjusted by controlling the direction and magnitude of the current flowing through each coil, or by selectively powering specific coil combinations (e.g., outer / inner coil or top / bottom coil).

[0039] During processing, a gas (such as argon) is supplied from a gas source 242 to the processing zone 210 via a conduit 244. The gas source 242 may include an inert gas, such as argon, krypton, helium, or xenon, which is capable of impacting and sputtering material from the sputtering target 232 and / or the surface of the substrate 205 at high energy based on a bias applied by a bias source 241. The gas source 242 may also contain a reactive gas, such as one or more of an oxygen-containing gas or a nitrogen-containing gas, which is capable of reacting with the sputtered material to form a layer on the substrate. Consumed processing gases and byproducts are discharged from the processing chamber 200 through an exhaust port 246, which receives the consumed processing gases and directs them to an exhaust conduit 248 having an adjustable position gate valve 247 to control the pressure in the processing zone 210 within the processing chamber 200. The exhaust conduit 248 is connected to one or more exhaust pumps 249, such as cryogenic pumps. Typically, during processing, the pressure of the sputtering gas in the processing chamber 200 is set to a subatmospheric level, such as a vacuum environment, with a pressure of about 0.6 mTorr to about 300 mTorr. In one embodiment, the processing pressure is set to about 20 mTorr to about 100 mTorr. Plasma is formed by gas between the substrate 205 and the sputtering target 232. Ions within the plasma are accelerated toward the sputtering target 232, causing material to detach from the sputtering target 232. The detached target material is deposited on the substrate.

[0040] The outer casing 291 generally includes a conductive wall 285, a center power supply 284, and a shielding component 286. Figure 2 In this configuration, a portion of the conductive wall 285, center feed 284, sputtering target 232, and motor 293 encapsulates and forms a back region 234. The back region 234 is a sealed area disposed on the back side of the sputtering target 232 and is typically filled with a flowing liquid during processing to remove heat generated at the sputtering target 232 during processing. In one embodiment, the conductive wall 285 and center feed 284 are configured to support the motor 293 and magnetron system 289 so that the motor 293 can rotate the magnetron system 289 during processing. In one embodiment, the motor 293 is electrically isolated from RF or DC power supplied from a power supply using a dielectric layer 294B (such as Delrin, G10, or Ardel).

[0041] Shielding element 286 may be composed of one or more dielectric materials, which are positioned to encapsulate and prevent RF energy transmitted to sputtering target 232 from interfering with and affecting other processing chambers located in processing system 100. Figure 1 In one configuration, shielding 286 may comprise Delrin, G10, Ardel or other similar materials and / or a thin grounded metal RF shield.

[0042] To provide effective sputtering, a magnetron system 289 is positioned behind a sputtering target 232 in an upper processing assembly 208 to create a magnetic field in a processing region 210 adjacent to the sputtering surface 233 of the sputtering target 232. This magnetic field generates magnetron-controlled plasma 213. The magnetic field of the magnetron system 289 is created to capture electrons and ions, thereby increasing the plasma density above one or more regions of the target 232 and improving target utilization, controlling deposition uniformity, and sputtering rate. According to one embodiment of this disclosure, the magnetron system 289 includes a source magnetron assembly 221, which includes an outer pole (not shown) and an inner pole (not shown). The magnetron system 289 is rotated about a central axis 294 of the processing chamber 200 by a motor 293. In some embodiments, a "closed-loop" magnetron configuration is formed within the magnetron system 289, such that the outer pole (not shown) of the magnetron surrounds the inner pole (not shown), thereby creating a gap as a continuous loop between the poles. In the closed-loop configuration, the magnetic field emitted from and re-entering the surface of the sputtering target forms a "closed-loop" pattern, which can be used to confine electrons in a closed pattern near the surface of the sputtering target; this is often referred to as a "racetrack" pattern. Compared to an open-loop magnetron configuration, the closed-loop magnetron configuration can confine electrons and generate high-density plasma near the sputtering surface 233 of the sputtering target 232, thereby increasing sputtering yield. In some other embodiments, an "open-loop" magnetron configuration is formed within the magnetron system 289, such that the outer pole of the magnetron surrounds the inner pole, thereby creating a gap as a continuous loop between the poles. In an open-loop magnetron configuration, electrons trapped between the inner and outer poles migrate, leak, and escape from the B-field created at the open end of the magnetron. Therefore, during the sputtering process, electrons can only be held for a short period due to reduced confinement. It has been found that the use of an open-loop magnetron configuration, when combined with RF and DC sputtering of multi-component targets as described herein, provides significant improvements in stepped coverage and enhances material composition uniformity on the substrate surface.

[0043] In some embodiments of the processing chamber 200, a bias source 241 is coupled between the electrodes and RF ground to adjust the bias voltage of the substrate 205 during processing, thereby controlling the degree of bombardment on the substrate surface. In some embodiments, electrodes are disposed near the substrate receiving surface 227 of the support 226 and include electrode 226A. In a PVD reactor, tuning the bombardment of the substrate surface by controlling the impedance of the electrodes to ground will affect the stepped coverage, overhang geometry, and properties of the deposited film, such as grain size, film stress, crystal orientation, film density, roughness, characteristic bottom coverage, characteristic stepped coverage, and in some cases, the film composition. Therefore, the bias source 241 can thus be used to change the deposition rate, etching rate, and even composition of multi-composition films at the substrate surface. In one embodiment, the bias source 241 is used to enable the deposition or etching of the deposited film by appropriately adjusting the impedance of the electrodes / substrate to ground. In one embodiment of the bias source 241, the bias source 241 has a variable capacitor tuning circuit and a feedback circuit to control the properties of the metal or non-metal layer deposited on the substrate.

[0044] In some embodiments, bias source 241 includes an RF source (not shown) coupled to electrode 226A and an impedance matching device (not shown). In some embodiments, the RF power supply is capable of generating RF current at a power between about 0 kW and about 5 kW at a frequency between about 11 MHz and about 228 MHz, for example, 13.56 MHz.

[0045] Exemplary sputtering process

[0046] During the sputtering (deposition) process, a substrate is loaded into the processing chamber, and the chamber is evacuated to approximately 1 × 10⁻⁶. - 6 Torr to 1×10 -9 The predetermined reference pressure of Torr. Next, sputtering gas (e.g., argon, krypton, helium, or xenon) is introduced into the processing chamber via gas source 242, and the pressure of the sputtering gas is controlled in the range of about 0.6 mTorr to about 300 mTorr, and preferably between about 20 mTorr and about 100 mTorr. The gas flow rate can be controlled using a mass flow controller (not shown) to achieve the desired pressure range. One or more of sources 281, 282 are configured to bias the target 232 when the source magnetron assembly 221 is in motion, and the RF coil 258 is biased to generate plasma in the processing region 210, the plasma containing metal ions (e.g., ... Figures 5A to 5B and Figure 5DBoth M+ ions and process gas ions are involved. The pressure within the chamber can be increased to levels higher than in a standard deposition process, which leads to an increase in the number of collisions in the plasma and thus reduces the ion energy near the surface of substrate 205. In one example, the pressure in processing region 210 during operation 310 is between approximately 1 mTorr and approximately 100 mTorr, compared to between approximately 0.5 mTorr and approximately 50 mTorr in a standard deposition process. The plasma is formed by collisions between electrons generated in the plasma and metal and / or gas ions or neutral particles in the processing region of the processing chamber. The plasma generates a large number of low-energy ions, which cause less damage to the substrate and the deposited layer.

[0047] During the sputtering process, the sputtering target 232 is biased by at least one of RF power and DC power using an RF source 281 and / or a DC source 282. The power supplied to the sputtering target 232 in one or more operations of method 300 is also referred to herein as the first target bias power. To create an efficient sputtering process, the magnetron system 289 located behind the sputtering target 232 in the upper processing assembly 208 utilizes a generated magnetic field (e.g., a first magnetic field) that penetrates the processing region 210 adjacent to the sputtering surface 233 of the sputtering target 232 and allows the formation of a magnetron-controlled plasma 213. During operation 310, low power is supplied to the first RF source 281 and / or the DC source 282 to generate a magnetron-controlled plasma 213 with a low plasma density, which results in the escape of lower-energy metal ions and neutral particles from the target surface 233 during the sputtering process, and thus a deposition process with a lower deposition rate. This creates a slower sputtering process, gentler ion bombardment, and less damage to the material disposed on the surface of the substrate. During operation 310, RF power is also supplied to RF coil 258, which is configured to form a plasma with a relatively medium to high plasma density (e.g., inductively coupled plasma 211) to improve the ionization of process gases and sputtered metal atoms compared to the plasma density of a metal ion plasma (e.g., magnetron-controlled plasma 213). The power supplied to induction coil 258 is also referred to as the first RF bias power. In this configuration, the reduced or lower plasma density in the metal ion plasma is achieved by reducing the supply voltage and / or power supplied to target 232 compared to the voltage and / or power supplied to target 232 in a standard deposition process. In one embodiment, the bias power applied to target 232 is between about 5 kW and about 30 kW of DC power, supplied by DC source 282, and the RF power applied to RF coil 258 at a frequency of 13.56 MHz is between about 0.5 kW and about 3 kW. In some implementations, a collimator is placed between the target and the induction coil, and a pulsed voltage (PV) bias is applied to the collimator to adjust the ion directionality.

[0048] In some embodiments, during the sputtering process, substrate 205 is biased with a negative DC voltage, pulsed voltage, or RF power to attract positively charged ions ionized by the plasma; this is referred to herein as substrate bias. Metal ions in the plasma are attracted toward substrate 205 and deposited as a thin film. In other embodiments, during the sputtering process, substrate 205 is subjected to a pulsed voltage (PV) waveform. The conditions used during the sputtering process, such as the amount of bias applied to the conductor coil, the amount of bias applied to the target, the chamber pressure, and the substrate bias level, are all designed to produce a deposition film formed by sputtered metal ions and neutral particles with reduced energy, thereby minimizing damage to the material disposed on the surface of substrate 205.

[0049] Exemplary pulse voltage waveform

[0050] Figure 4A The illustration shows exemplary graphs 400 of different types of pulse waveforms (i.e., substrate bias) at the substrate surface caused by different voltage waveforms established at the electrodes by the bias source 241 within the processing chamber, waveforms 425 and 430. These waveforms include two phases: an ion current phase during a first time period and a sheath collapse phase during a second time period, as illustrated. At the beginning of the ion current phase, the decrease in substrate voltage creates a high-voltage sheath above the substrate, thereby accelerating positive ions to the substrate. During the ion current phase, positive ions bombarding the substrate surface deposit positive charges on the substrate surface, which, without compensation, will cause the substrate voltage to gradually increase during the ion current phase, as shown in the figure. Figure 4A The voltage waveform 425 is shown in the figure. However, the uncontrolled accumulation of positive charge on the substrate surface will undesirably and gradually release the sheath and clamping capacitor, thereby slowly reducing the sheath voltage drop and bringing the substrate potential close to zero, as shown in voltage waveform 425. The accumulation of positive charge leads to a voltage drop in the voltage waveform established at the substrate surface ( Figure 4A However, a pulsed voltage (PV) waveform (e.g., substrate bias) established at the electrode can be generated that has a negative slope during the ion current phase, in order to create a square region (e.g., near-zero slope) for the established substrate voltage waveform, such as... Figure 4ACurve 430 is shown in the figure. The first voltage of the PV waveform can range from approximately -100 volts (V) to -2000 volts. For example, the first voltage of the PV waveform can be approximately -200V. For example, the first voltage of the PV waveform can be approximately -600V. For example, the first voltage of the PV waveform can be approximately -1500V. The waveform slope established at the electrode during the ion current phase can be called current compensation. The voltage difference between the start and end of the ion current phase determines the width of the ion energy distribution function (IEDF). The larger the voltage difference, the wider the IEDF. To achieve single-energy ions and a narrower IEDF width, an operation is performed to flatten the substrate voltage waveform during the ion current phase using current compensation.

[0051] Figure 4B Figure 450, according to certain embodiments of this disclosure, illustrates the ion energy distribution function (IEDF). Figure 450 includes a vertical axis plotting the ion population of the IEDF and a horizontal axis plotting the ion energies. Figure 450 depicts IEDF curves for three different waveforms: a 400 kHz pulse voltage (PV) waveform 402, a 13 MHz RF waveform 404, and a 2 MHz RF waveform 406.

[0052] As shown in the figure, the 400kHz PV waveform 402 exhibits a high-value, narrow single-peak IEDF. The IEDF of the 400kHz PV waveform 402 also occurs within a relatively narrow ion energy band. This is due to the pulsed characteristics of the 400kHz PV waveform 402. Compared to the 400kHz PV waveform 402, the 13MHz RF waveform 404 exhibits a double-peak (double-energy) IEDF. The peak value of the double-peak IEDF of the 13MHz RF waveform 404 is approximately half the peak value of the single-peak IEDF of the 400kHz PV waveform 402. Furthermore, the double-peak IEDF of the 13MHz RF waveform 404 occurs over a wider ion energy range than that of the 400kHz PV waveform 402. The wider range of double-peak IEDF is due to the sinusoidal characteristics of the RF waveform. The 2MHz RF waveform 406 also exhibits a double-peak (double-energy) IEDF. In this case, the peak magnitude of the bimodal IEDF of the 2MHz RF waveform 406 is approximately one-fifth of the peak magnitude of the single-peak IEDF of the 400kHz PV waveform 402. Besides the lower magnitude, the bimodal IEDF of the 2MHz RF waveform 406 also occurs over a larger ion energy range compared to the 13MHz RF waveform 404 and the 400kHz PV waveform 402.

[0053] The 400kHz PV waveform 402 exhibits a high-magnitude single-peak narrow ion energy band, which is superior to the wider ion energy band and bimodal IEDF exhibited by the 13MHz RF waveform 404 and the 2MHz RF waveform 406. Compared to the 13MHz RF waveform 404 and the 2MHz RF waveform 406, the single-peak of the 400kHz PV waveform 402 provides higher peak power, better power control, and improved bombardment angle (e.g., better verticality). Some implementations are designed for use with PV waveform tuning techniques. Figure 4B The method for the distribution of ion energy is shown, as described in more detail herein.

[0054] Exemplary process sequence

[0055] Figure 3 A flowchart of method 300 according to one or more embodiments described herein is illustrated. Method 300 includes multiple operations. Operation 310 includes forming a buffer layer. Operation 320 includes forming a second layer over the buffer layer. Operation 330 includes resputtering at least a portion of the first and second layers. Method 300 may be referenced... Figures 4A to 4B and Figures 5A to 5D To understand. In some implementations, the operation of method 300 can be used... Figure 2 The process chamber 200 shown is used for execution. Although the operation of method 300 is described using process chamber 200, other types of process chambers and plasma generation techniques are also considered to be within the scope of this disclosure. In other embodiments, the operation of method 300 may be performed in a series of process chambers. For example, operations 310 and 320 may be performed in a first process chamber, while operation 330 may be performed in a second process chamber, or any combination of process chambers and operations of method 300.

[0056] In method 300, operation 310 is used to form a thin deposited layer 512 on the substrate surface to isolate the substrate surface and mitigate damage to the substrate during subsequent processing activities. The thin deposited layer 512 is generally referred to herein as a “solid buffer layer,” or simply a “buffer layer,” and in some embodiments, it may differ from a diffusion barrier layer, a liner, or a wetting layer. Operation 310 is followed by operation 320 to ensure the desired stepped coverage, and operation 330 employs an etching process to remove or adjust the profile of any material overhangs within the features formed on the substrate.

[0057] At operation 310 of method 300, such as Figure 5A As seen in the image, a buffer layer 512 is formed. The buffer layer 512 can be formed using the sputtering process described above. The buffer layer 512 (e.g., the first deposition layer) is formed on the dielectric element feature 510 (…). Figure 5AThe buffer layer is formed on the field, sidewalls, and bottom. It is typically a thin-film coating with desired stepped, sidewall, and bottom coverage, such as... Figure 5A The deposited film shown includes a field portion 514, a sidewall portion 516, and a bottom portion 518. The combination of all three portions of the thin film coating acts as a protective buffer layer, preventing subsequent deposition steps with higher ion energies from damaging underlying layers, such as previously deposited diffusion barrier layers, liners, wetting layers, or dielectric materials in device features. In some embodiments, the low-energy deposition process results in minimal damage to the substrate 205 and / or previously deposited layers, making operation 310 ideal for precision materials such as low-dielectric-constant dielectric materials. In some embodiments, operation 310 is designed as a low-damage process that forms a thin buffer layer to protect the underlying dielectric material from any damage caused by subsequent high-energy and / or high-deposition-rate material deposition steps performed in the same processing chamber. Operation 310 can be used to deposit various materials on the substrate 205 with minimal damage, including molybdenum (Mo), copper (Cu), tungsten (W), titanium (Ti), aluminum (Al), tantalum (Ta), and nickel (Ni). In some embodiments, the thickness of the resulting thin film buffer layer 512 (e.g., the first deposition layer) deposited during operation 310 is between about 10 angstroms (Å) and about 100 Å at different locations.

[0058] Once operation 310 is completed, operation 320 of method 300 begins. Operation 320 of method 300 includes forming a second layer 522, such as sputtering a copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), cobalt (Co), or tungsten (W) film, or a combination thereof. In some embodiments, operation 320 is performed in the same processing chamber as operation 310. The second layer 522 formed by operation 320 may contain a bottleneck or narrowing structure formed by overhangs of the deposited material, such as... Figure 5B As shown. The overhang 524 is caused by the rapid accumulation of deposited metal near the entrance of the element feature. The overhang 524 narrows the entrance, blocks metal from entering the feature, and casts shadows on the sidewall deposition, thus resulting in poor sidewall coverage 526 of the element feature. The overall thickness of the second layer 522 is between approximately 100 Å and approximately 1000 Å. The parameters of operation 320 can be controlled to optimize the film thickness, uniformity, stepped coverage, undercover, and morphology. For example, the applied DC power, PV waveform characteristics, substrate bias, deposition time, and gas pressure can be adjusted to control ion flux and ion energy, which all affect the film profile, morphology, and properties. In one example, the applied DC power, substrate bias (e.g., PV waveform), deposition time, and gas pressure can be adjusted to control ion flux, IEDF, and ion energy, which all affect the film profile, morphology, and properties. The temperature of the substrate 205 can also be controlled to optimize film adhesion and crystal orientation.

[0059] After operation 320 is completed, operation 330 is performed. Operation 330 of method 300 includes resputtering, or sometimes referred to herein as an etching process, a film (e.g., a Cu, Mo, Ru, Co, or W film) formed on the surface of substrate 205. Figure 5C As shown, operation 330 removes and / or redistributes material present in the overhangs 524 that may have formed on substrate 205 during operation 320. Operation 330 has also been found to improve sidewall coverage 526 through a resputtering process. During operation 330, an inert gas, such as argon, krypton, helium, or xenon, is introduced into the processing chamber 200 via gas source 242 and conduit 244. This inert gas then flows into processing region 210 and interacts with the plasma 211 formed during operation 320 and / or plasma generated or maintained by a bias applied by bias source 241. The plasma then interacts with the process gas to generate energetic ion species (e.g., gaseous ions and sputtered atomic ions) that are directed toward substrate 205 by a PV voltage waveform applied to substrate 205 by bias source 241. As described above... Figure 4A As shown, the voltage (substrate bias) of the PV voltage waveform applied to substrate 205 by bias source 241 may include voltage waveform pulses with an "enable" period (e.g., ion current phase), during which the applied bias is between approximately -100 volts (V) and approximately -2000 volts. In some embodiments, by providing a PV voltage waveform of 100-500 kHz, or a PV voltage waveform of 350 kHz to 450 kHz, such as a 400 kHz PV voltage waveform, during the sputtering process performed during operation 320, a single-peak IEDF is generated for the ions in the plasma formed within the processing volume to create higher ion energy peak power, better ion energy control of the delivered power, and improved control of the ion bombardment angle (e.g., better verticality) during operation 320.

[0060] In some embodiments of operation 320, the plasma is generated or maintained by the induction coil assembly 255 to enhance the resputtering process by increasing the ionization of gas atoms and the resulting ion species. By altering the radial distribution of the plasma, the electromagnet assembly can also be used to help improve etching or material redistribution processes on the surface of substrate 205 and provide more precise control over the etching or material redistribution processes.

[0061] During operation 330, ionized argon atoms substantially bombard the surface, ballistically ejecting and / or etching the shape of the film. Because the directionality of the ions in the plasma (e.g., inert gas ions) is controlled by the substrate bias, overhanging portions of the deposited film can be etched faster and in a more controlled manner than other areas of the device features. For example...Figure 5C As shown, the resputtering process removes and redistributes deposited metal from component features, particularly in the bottom region, resulting in an improved metal film 532 with improved sidewall and bottom coverage. As described above, during the resputtering process, the generated plasma can be used to redistribute metal atoms located on the bottom portion of the feature and redeposit metal atoms on the sidewall portions, resulting in a reduction of material on the overhangs and bottom portions, and an increase of material on the sidewall portions. This material redistribution improves sidewall coverage and film thickness uniformity. Operating parameters, such as gas composition, gas flow rate, pressure, and substrate bias characteristics, can be optimized to achieve the desired etching rate, selectivity, and profile. For example, by adjusting the applied voltage of the PV waveform (e.g., substrate bias), the depth and energy of ion bombardment can be adjusted, and thus the resputtering process allows for fine-tuning of material removal, redeposition, and feature profile control. Similar to the discussion above, in some embodiments of operation 330, by providing a PV waveform of 100-500 kHz, or a PV waveform of 350 kHz to 450 kHz, such as a PV waveform of 400 kHz, a single-peak IEDF is generated for the ions formed in the plasma formed within the processing volume, in order to create higher ion energy peak power, better ion energy control of the delivered power, and improved control of the ion bombardment angle (e.g., better verticality).

[0062] In some embodiments, operations 320 and 330 are performed simultaneously, hereinafter referred to as simultaneous deposition and etching (SIE). Prior to SIE, operation 310 is performed to create a thinner and more conformal buffer layer on the substrate surface, as described above. During SIE, deposition and etching are performed simultaneously (e.g. Figure 5C (As shown). This processing mode combines operations 320 and 330. This is achieved by using magnetron-controlled plasma 213 and biasing the substrate using a PV waveform in a synchronous process step.

[0063] The combination of sputtering and etching processes resulting from the implementation of PV waveform substrate bias allows for simultaneous deposition and etching of substrate 205, thereby increasing deposition rates, improving step coverage process results, and increasing yield. Combined operations 320 and 330 offer several advantages over conventional PVD and etching processes. First, SIE eliminates the need for separate PVD and etching steps, reducing the time and resources required for such processes, thus improving process efficiency and yield. Furthermore, simultaneous deposition and etching operations ensure that deposited and re-deposited material reaches all desired areas of the features formed in substrate 205, thereby improving step coverage. Additionally, simultaneous deposition and etching operations reduce overhangs that typically form during PVD processes. In summary, combined operations 320 and 330 provide a low-damage deposition process for metal layers with high aspect ratios and good step coverage, while minimizing damage to underlying layers and reducing contaminants. This is particularly advantageous for applications requiring low-damage processes, such as those for low-dielectric-constant materials.

[0064] In other embodiments, operations 310, 320, and 330 of method 300 are sequential processes, making them easier to control than some other process sequences. Each operation is built upon the previous one, ensuring that the desired result is achieved at each operation.

[0065] In some embodiments of method 300, the sputtering process used to form the buffer layer 512 during operation 310 may also utilize a sputtering process similar to that described in operations 320 and 330. In one example, the buffer layer target is biased using DC power, and the substrate is biased using a PV waveform to form a substantially conformal buffer layer. Furthermore, during operation 310, the DC power, PV waveform, deposition time, and gas pressure can be adjusted to control the ion flux, IEDF, and ion energy, which affect the profile, morphology, and properties of the buffer layer film.

[0066] Additional considerations

[0067] Although this specification contains numerous specific implementation details, these should not be construed as limiting the scope that can be claimed, but rather as a description of features that may be specific to a particular implementation. Some features described in this specification are described in the context of a single implementation, or may be implemented in combination within a single implementation. Conversely, various features described in the context of a single implementation may be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although previously described features may be described as acting in certain combinations, and even initially so requested, one or more features from a requested combination may, in some cases, be excluded from that combination, and a requested combination may point to a sub-combination or a variation of a sub-combination.

[0068] Specific embodiments of this objective have been described. Other implementations, modifications, and arrangements fall within the scope of the following claims and will be apparent to those skilled in the art. Although operations are shown in a specific order in the illustrations or claims, this should not be construed as requiring such operations to be performed in the specific order or sequence shown in the illustrations, or that all illustrated operations must be performed (some operations may be considered optional) to achieve the desired result. In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and may be performed as appropriate. Although the various steps in the methods or processes of the embodiments are presented and described sequentially, those skilled in the art will understand that some or all steps may be performed in a different order, may be combined or omitted, and some or all steps may be performed in parallel. Such steps may be performed actively or passively. The method or process may be repeated or extended to support multiple components or multiple users in a field environment. Therefore, the scope should not be considered limited to the specific arrangement of steps shown in the flowcharts or illustrations.

[0069] Furthermore, any of the requested implementations is considered suitable for at least one computer-implemented method; a non-transitory computer-readable medium storing computer-readable instructions for performing the computer-implemented method; and a computer system including computer memory interconnected to a hardware processor configured to perform the computer-implemented method or instructions stored on a non-transitory computer-readable medium.

[0070] As used herein, “CPU,” “controller,” “processor,” “at least one processor,” or “one or more processors” generally refers to a single processor configured to perform one or more operations, or multiple processors configured to collectively perform one or more operations. In the case of multiple processors, one or more operations may be distributed among different processors, although a single processor may perform multiple operations, while multiple processors may collectively perform a single operation. Similarly, “memory,” “at least one memory,” or “one or more memory” generally refers to a single memory configured to store data and / or instructions, or multiple memory modules configured to collectively store data and / or instructions.

[0071] As used in this article, "gas" and "fluid" can be used interchangeably. Both generally refer to elements, compounds, materials, etc. that have gaseous, fluid, or both gaseous and fluid properties.

[0072] Unless otherwise defined, all technical and scientific terms used have the same meaning as understood by one of ordinary skill in the art to which such systems, devices, methods, processes and components pertain.

[0073] In this disclosure, the terms “top,” “bottom,” “side,” “above,” “below,” “up,” “down,” “upward,” “downward,” “horizontal,” “vertical,” etc., do not refer to absolute directions. Rather, these terms refer to directions relative to an unspecified reference plane. This unspecified reference plane can be vertical, horizontal, or other angular orientations.

[0074] The singular forms of “a,” “an,” and “the,” including plural references, are used unless the context clearly indicates otherwise. In a claim, a reference to a singular element is not intended to mean “one and only one,” unless specifically stated otherwise, but rather “one or more.” Unless specifically stated otherwise, the word “some” refers to one or more.

[0075] Embodiments of this disclosure may suitably include, consist of, or substantially consist of the disclosed limiting features, and may be implemented where undisclosed limiting features are absent. In this and the appended claims, the words “comprising,” “having,” and “including,” and all their grammatical variations, are intended to have an open, non-limiting meaning and do not exclude other elements or steps.

[0076] "Optional" and "optionally" indicate that the material, event, or situation described below may or may not occur. The description includes both the circumstances under which the material, event, or situation may occur and the circumstances under which it may not occur.

[0077] "Coupled" and "phase-coupled" indicate that the material described below is connected to the material described above. Such connection can be direct or indirect and may or may not include intervening elements such as pipes, wiring, fasteners, mechanical power transmission, electrical communication, wired and / or wireless transmission, all of which may be suitable to affect the operation of the components.

[0078] In usage, the term "OK" encompasses a variety of actions. For example, "OK" might include calculation, processing, derivation, investigation, and consulting, such as querying in a table, database, or other data structure, and confirming the result. Furthermore, "OK" might also include receiving, such as receiving information, and accessing, such as accessing data in memory. Additionally, "OK" might include resolving, selecting, and establishing.

[0079] When the words “about” or “approximately” are used, this term may mean that the value can vary by as much as ±10%, up to 5%, up to 2%, up to 1%, up to 0.5%, up to 0.1%, or up to 0.01%.

[0080] A range can be expressed as from approximately one particular value to approximately another particular value, inclusive. When such a range is expressed, it should be understood that another implementation is from one particular value to another particular value, as well as all particular values ​​within that range and combinations thereof.

[0081] In use, terms such as “first” and “second” are arbitrarily assigned and are intended only to distinguish two or more components of a system, apparatus, or composition. It should be understood that the terms “first” and “second” have no other purpose, are not part of the name or description of the components, and do not necessarily define the relative position or location of the components. Furthermore, the use of the terms “first” and “second” alone does not require the existence of any “third” component, although such a possibility is foreseeable within the scope of various embodiments.

[0082] Although only a few exemplary embodiments have been described, those skilled in the art will readily recognize that numerous modifications can be made to these exemplary embodiments without substantially departing from the scope of the disclosure. Therefore, all such modifications are intended to be included in this disclosure and limited to the scope of the following claims. In the claims, the function plus means clause is intended to cover structures that perform the described function, including not only structural equivalents but also equivalent structures. The applicant expressly intends not to impose any limitation on any claim under 35 U.S.SC §112(f), except for claims that expressly use the phrase “means for…” and combine it with the relevant function.

[0083] The claims above are not intended to limit the embodiments provided, but should be given the full scope consistent with the language of the claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: In a physical vapor deposition (PVD) chamber, a first layer is formed on the surface of the substrate, which includes multiple features formed in the substrate, using a PVD process, wherein forming the first layer includes applying a bias voltage to a target material in the processing chamber. as well as Etching at least a portion of the first layer within the PVD chamber, wherein the etching comprises: A substrate bias voltage is applied to an electrode disposed within a substrate support near a substrate receiving surface, wherein applying the substrate bias voltage includes transmitting a pulse voltage (PV) waveform to the electrode; as well as The substrate is exposed to plasma generated within the PVD chamber.

2. The method of claim 1, wherein transmitting the PV waveform comprises: A first voltage is transmitted to the electrode disposed within the substrate support for a first time period; as well as The transmission of the first voltage to the electrode disposed within the substrate support is stopped for a second time period.

3. The method of claim 2, wherein the first voltage is about -100V to about -2000V.

4. The method of claim 1, the method further comprising adjusting a first voltage of the PV waveform to adjust the etching depth of at least the portion of the first layer, wherein the first voltage is about -100V to about -2000V.

5. The method of claim 1, wherein forming the first layer and etching at least a portion of the first layer are performed simultaneously.

6. The method of claim 5, wherein the simultaneous formation and etching of the first layer results in the simultaneous deposition and redeposition of one or more materials of the first layer to improve step coverage.

7. The method of claim 1, further comprising altering the radial distribution of the plasma generated within the processing chamber, wherein altering the radial distribution of the plasma further comprises transmitting current to one or more electromagnet assemblies aligned around the processing chamber.

8. A method for manufacturing a semiconductor device, the method comprising: In a first physical vapor deposition (PVD) chamber, a first layer is formed on the surface of the substrate, which includes a plurality of features formed in the substrate, wherein forming the first layer includes applying a bias voltage to a target material in the first PVD chamber; The substrate is transferred from the first PVD chamber to the second PVD chamber; as well as At least a portion of the first layer is etched within the second PVD chamber, wherein the etching includes: A substrate bias voltage is applied to an electrode disposed within a substrate support near the substrate receiving surface, wherein applying the substrate bias voltage includes transmitting a PV waveform to the electrode; as well as The substrate is exposed to plasma generated in the second PVD chamber.

9. The method of claim 8, wherein transmitting the PV waveform comprises: A first voltage is transmitted to the electrode disposed within the substrate support for a first time period; as well as The transmission of the first voltage to the electrode disposed within the substrate support is stopped for a second time period.

10. The method of claim 9, wherein the first voltage is about -100V to about -2000V.

11. The method of claim 8, the method further comprising adjusting a first voltage of the PV waveform to adjust the etching depth of at least the portion of the first layer, wherein the first voltage is about -100V to about -2000V.

12. The method of claim 8, further comprising simultaneously applying a bias voltage to the target and etching at least a portion of the first layer within the second processing chamber.

13. The method of claim 12, wherein the target is simultaneously biased and the first layer is etched within the second processing chamber, resulting in simultaneous deposition and re-deposition of one or more materials of the first layer to improve step coverage.

14. The method of claim 8, the method further comprising altering the radial distribution of the plasma generated within the second processing chamber, wherein altering the radial distribution of the plasma further comprises transmitting current to one or more electromagnet assemblies aligned around the second processing chamber.

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