Structure design of preamble, midamble and postamble

Abstract

The present disclosure provides systems, methods, and apparatus, including computer programs encoded on computer storage media, for receiving a preamble, midamble, or postamble of a data transmission. A receiving device receives a designated symbol indicating a start of the preamble, midamble, or postamble. The receiving device receives a first designated data pattern after the designated symbol, where a duration of the designated symbol is greater than a duration of the first designated data pattern. The receiving device performs frequency synchronization based on the first designated data pattern. The receiving device identifies a chip duration of the data transmission based on the first designated data pattern or a second designated data pattern after the first designated data pattern.

Description

Technical Field

[0001] This disclosure relates to wireless communications including transmissions having a preamble, an intermembrane, and / or a posttermembrane. Related technical descriptions

[0002] Wireless communication systems are widely deployed to provide a variety of telecommunications services, such as telephone, video, data, messaging, and broadcasting. Typical wireless communication systems may employ multiple access technologies capable of supporting communication with multiple users by sharing available system resources. Examples of such multiple access technologies include Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, Orthogonal Frequency Division Multiple Access (OFDMA) systems, Single Carrier Frequency Division Multiple Access (SC-FDMA) systems, and Time Division Synchronous Code Division Multiple Access (TD-SCDMA) systems.

[0003] These multiple access technologies have been adopted in various telecommunications standards to provide a common protocol that enables different wireless devices to communicate at the city, national, regional, and even global levels. An example telecommunications standard is 5G New Radio (NR). 5G NR is part of the continuous evolution of mobile broadband, promulgated by the 3rd Generation Partnership Project (3GPP) to meet new requirements related to latency, reliability, security, scalability (such as with the Internet of Things (IoT), and other requirements). 5G NR includes services associated with enhanced mobile broadband (eMBB), massive machine-type communications (mMTC), and ultra-reliable low-latency communications (URLLC). Some aspects of 5G NR are based on the 4G Long Term Evolution (LTE) standard. Summary of the Invention

[0004] The systems, methods, and apparatus disclosed herein each have several innovative aspects, and no single aspect is solely responsible for the desired properties disclosed herein.

[0005] In some aspects, the technology described herein relates to an apparatus for receiving a preamble, intermezzo, or postamble for data transmission, the apparatus comprising: one or more memories storing executable instructions; and one or more processors coupled to the one or more memories and configured to execute the instructions to: receive a designated symbol indicating the start of a preamble, intermezzo, or postamble; receive a first designated data pattern after the designated symbol, wherein the duration of the designated symbol is greater than the duration of the first designated data pattern; perform frequency synchronization based on the first designated data pattern; and identify the chip duration of data transmission based on the first designated data pattern or a second designated data pattern following the first designated data pattern.

[0006] In some aspects, the technology described herein relates to an apparatus for receiving a preamble, introductory code, or postamble for data transmission, the apparatus comprising: one or more memories storing executable instructions; and one or more processors coupled to the one or more memories and configured to execute the instructions to: receive a first specified data pattern comprising a plurality of symbols encoded in line codes, wherein the first specified data pattern has a symbol rule violation of the line code in a violation symbol indicating the preamble, introductory code, or postamble; perform frequency synchronization based on the first specified data pattern; and identify the chip duration of data transmission based on the first specified data pattern or a second specified data pattern following the first specified data pattern.

[0007] In some aspects, the technology described herein relates to a method for receiving a preamble, introductory code, or postamble for data transmission, the method comprising: receiving a designated symbol indicating the start of the preamble, introductory code, or postamble; receiving a first designated data pattern after the designated symbol, wherein the duration of the designated symbol is greater than the duration of the first designated data pattern; performing frequency synchronization based on the first designated data pattern; and identifying the chip duration of data transmission based on the first designated data pattern or a second designated data pattern following the first designated data pattern.

[0008] Details of one or more specific embodiments of the subject matter described in this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. Note that the relative dimensions in the following drawings may not be drawn to scale. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating an example of a wireless communication system that includes access to a network.

[0010] Figure 2A This is an example illustration of the first frame.

[0011] Figure 2B This is a diagram illustrating an example of a DL channel within a subframe.

[0012] Figure 2C This is an example illustration of the second frame.

[0013] Figure 2D This is an example diagram illustrating a subframe.

[0014] Figure 3 This is a diagram illustrating examples of base stations (BS) and user equipment (UE) in an access network.

[0015] Figure 4 This is a diagram illustrating an example of a decomposed base station architecture.

[0016] Figure 5 This is a diagram illustrating an example of transmission using a preamble that includes one or more designated symbols used to indicate the preamble.

[0017] Figure 6 This is a diagram illustrating an example of a transmission using a line code violation with Manchester code, which is used to indicate the guide code.

[0018] Figure 7 This is a diagram illustrating an example of a transmission using a line code violation with pulse interval coding (PIE) code, which is used to indicate the preamble.

[0019] Figure 8 This is a diagram illustrating an example of a line code violation using frequency modulation (FM) code, which is used to indicate the lead code.

[0020] Figure 9 This is a diagram illustrating an example of a transmission using Miller code for a line code violation, where the Miller code is used to indicate the guide code.

[0021] Figure 10 This is a diagram illustrating examples of preambles and data transmission with different line codes.

[0022] Figure 11 This is a diagram illustrating an example of a preamble with chip duration, where the chip duration is a multiple of the chip duration of the data transmission.

[0023] Figure 12 This is a diagram showing the transmission of preamble at a single frequency and data at multiple frequencies.

[0024] Figure 13 This is a conceptual data flow diagram illustrating the data flow between different parts / components in an example receiving device.

[0025] Figure 14 This is a flowchart of an example method for a receiving device to receive transmitted preambles (e.g., preambles, intermembs, or postambles).

[0026] Figure 15 This is a flowchart of an example method for a receiving device to receive transmitted preambles (e.g., preambles, intermembs, or postambles).

[0027] Similar reference numerals and names in the various figures indicate similar elements. Detailed Implementation

[0028] For the purpose of describing the innovative aspects of this disclosure, the following description relates to certain specific implementations. However, those skilled in the art will readily recognize that the teachings herein can be applied in a variety of different ways. Some examples in this disclosure are based on wireless and wired local area network (LAN) communications according to the Institute of Electrical and Electronics Engineers (IEEE) 802.11 wireless standard, the IEEE 802.3 Ethernet standard, and the IEEE 1901 Power Line Communication (PLC) standard. However, the specific implementations described can be implemented in any device, system, or network capable of transmitting and receiving RF signals according to any wireless communication standard, including: any of the IEEE 802.11 standards, Bluetooth, etc. ® Standard, Code Division Multiple Access (CDMA), Frequency Division Multiple Access (FDMA), Time Division Multiple Access (TDMA), Global System for Mobile Communications (GSM), GSM / General Packet Radio Service (GPRS), Enhanced Data GSM Environment (EDGE), Terrestrial Trunking Radio (TETRA), Wideband-CDMA (W-CDMA), Evolved Data Optimized (EV-DO), 1xEV-DO, EV-DO Rev A, EV-DO Rev B, High-Speed ​​Packet Access (HSPA), High-Speed ​​Downlink Packet Access (HSDPA), High-Speed ​​Uplink Packet Access (HSUPA), Evolved High-Speed ​​Packet Access (HSPA+), Long Term Evolution (LTE), AMPS, or other known signals used for communication within wireless networks, cellular networks, or Internet of Things (IoT) networks (such as systems utilizing 3G, 4G, or 5G, or further specific implementations thereof).

[0029] Environmental IoT devices can refer to wireless devices with relatively low power consumption. In some specific implementations, environmental IoT devices can be designed to have a maximum coverage distance of 10 to 50 meters. Environmental IoT devices can be designed to operate in topologies where the UE is an intermediate node under network control. Environmental IoT devices may not have Radio Resource Control (RRC) status, may not have cell mobility, and may not have Hybrid Automatic Repeat Request (HARQ). For example, a first type of environmental IoT device can be characterized by a peak power consumption of approximately 1 microwatt (μW). Such environmental IoT devices can have energy storage up to 10 X The initial sampling frequency offset (SFO) is in parts per million (ppm), and there is neither downlink (DL) amplification nor uplink (UL) amplification in the environmental IoT device. The environmental IoT device can transmit UL backscattered on an externally provided carrier. For example, the second type of environmental IoT device can have a peak power consumption of several hundred μW and 10 XThe initial SFO (Signal Optimization Factor) in ppm, and one or both of DL (Dual Optimization) and / or UL (Ultra-Low Optimization) amplification within the device, are used to characterize the device. Type II environmental IoT devices can generate UL transmission internally or backscatter UL transmission on an externally provided carrier. The exact peak power consumption and SFO (e.g., the value of X) can be specified by standards.

[0030] In environmental IoT systems, preambles can be used to indicate the start of transmission. For example, transmission can be a downlink transmission, forward link transmission, uplink transmission, reverse link transmission, or sidelink transmission. Preambles can also be used for synchronization of receiving devices. Similarly, indices or postambles can be used for synchronization. The term "preamble" can refer to a preamble, indices, or postamble. In some implementations, preamble-based synchronization may utilize delimiters as part of the preamble or as a separate signal. In some implementations, delimiters are not required.

[0031] In one aspect, this disclosure provides a structure for preambles (such as preambles, middle preambles, or postambles). For example, a preamble may be used by a receiving device (such as an environmental IoT device, user equipment (UE), or network node) to identify the start of transmission, perform frequency synchronization, or determine the bit or chip duration for data transmission. The preamble can be signaled using two states: high output voltage and low output voltage. The preamble includes at least one specified data pattern that can be used for frequency synchronization and / or to identify the chip duration for data transmission. In some embodiments, the preamble may include a specified symbol indicating the start of the preamble. In some embodiments, the specified data pattern may include an indication of a line code rule violation of the preamble.

[0032] In one respect, the techniques disclosed herein offer the following technical advantages. The preamble structure disclosed herein allows for low-complexity detection of signals, enabling devices to determine whether to perform further processing of data transmission and providing frequency and time synchronization for such processing. Furthermore, the use of preambles reduces signaling overhead. For example, a preamble can indicate the start of transmission, and a middle or postamble can indicate the end of transmission or a portion thereof.

[0033] Various apparatuses and methods will now be used to present several aspects of a telecommunications system. These apparatuses and methods will be described in detail below and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively, “elements”). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole.

[0034] As an example, elements, any portion of elements, or any combination of elements may be implemented as a "processing system" including one or more processors. Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, system-on-a-chip (SoCs), baseband processors, field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gate logic components, discrete hardware circuitry, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. A processor may include an interface or an interface coupled to acquire or output signals. The processor may acquire signals via the interface and output signals via the interface. In some embodiments, the interface may be a printed circuit board (PCB) transmit line. In some other embodiments, the interface may include a wireless transmitter, a wireless transceiver, or a combination thereof. For example, the interface may include a radio frequency (RF) transceiver that may be implemented to receive or transmit signals, or both. One or more processors in the processing system may execute software. Whether referred to as software, firmware, middleware, microcode, hardware description language, or other names, software should be broadly interpreted as meaning instructions, instruction sets, code, code segments, program code, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc.

[0035] Therefore, in one or more example implementations, the described functionality can be implemented in hardware, software, or any combination thereof. If implemented in software, the functionality can be stored or encoded as one or more instructions or code on a computer-readable medium. A computer-readable medium includes a computer storage medium, which may be referred to as a non-transitory computer-readable medium. A non-transitory computer-readable medium may not include transient signals. The storage medium can be any available medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disc storage devices, magnetic disk storage devices, other magnetic storage devices, combinations of computer-readable media of the foregoing types, or any other medium capable of storing computer-executable code having instructions or data structures accessible by a computer.

[0036] Figure 1This is an illustration of an example of a wireless communication system and access network 100. The wireless communication system (also referred to as a wireless wide area network (WWAN)) includes base station 102, UE 104, evolved packet core (EPC) 160, and another core network 190 (such as a 5G core (5GC)). Base station 102 may include macro cells (high-power cellular base stations) or small cells (low-power cellular base stations). Macro cells include base stations. Small cells include femtocells, picocells, and microcells. Base station 102 may be configured as a decomposed RAN (D-RAN) or open RAN (O-RAN) architecture, where functionality is split among multiple units (such as a central unit (CU), one or more distributed units (DU), or radio units (RU)). Such an architecture may be configured to utilize a protocol stack logically split among one or more units (such as one or more CUs and one or more DUs). In some respects, the CU can be implemented within an edge RAN node, and in other respects, one or more DUs can be co-located with the CU, or can be geographically distributed across one or more RAN nodes. A DU can be implemented to communicate with one or more RUs.

[0037] Base stations may include or be referred to as gNB, Node B, eNB, access point, base transceiver station, radio base station, radio transceiver, transceiver function, Basic Service Set (BSS), Extended Service Set (ESS), Transmitter Receiver Point (TRP), or any other suitable term. Base station 102 provides access to EPC 160 or core network 190 for UE 104. Examples of UE 104 include cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, personal digital assistants (PDAs), satellite radios, GPS devices, multimedia devices, video devices, digital audio players (such as MP3 players), cameras, game consoles, tablets, smart devices, wearable devices, vehicles, electricity meters, gas pumps, large or small kitchen appliances, healthcare devices, implants, sensors / actuators, displays, or any other similarly functional devices. Some UE 104s may be referred to as IoT devices (such as parking timers, oil pumps, ovens, vehicles, heart monitors, etc.). In some implementations, the Ambient Internet of Things (A-IoT) device 106 may have relatively low peak power consumption. For example, the A-IoT device 106 may be a sensor, tag, or identification tag. The A-IoT device 106 may be connected to the UE 104 via a wireless link 108. The UE 104 may also be referred to as a station, mobile station, subscriber station, mobile unit, subscriber unit, wireless unit, remote unit, mobile device, wireless device, wireless communication device, remote device, mobile subscriber station, access terminal, mobile terminal, wireless terminal, remote terminal, handheld device, user agent, mobile client, client, or any other suitable term.

[0038] In some specific implementations, one or more of the UE 104 or A-IoT device 106 include a preamble receiving component 140, which is configured to receive transmissions having a preamble, introductory preamble, or postamble. The preamble receiving component 140 includes a preamble detection component 142, a pattern recognition component 144, a rule violation component 146, a frequency synchronization component 148, and a duration component 149. The preamble detection component 142 is configured to receive a designated symbol indicating the start of a preamble, introductory preamble, or postamble. The pattern recognition component 144 is configured to receive a first designated data pattern after the designated symbol, wherein the duration of the designated symbol is greater than the duration of the first designated data pattern. The rule violation component 146 is configured to detect symbol rule violations of the line code in a violation symbol of the designated data pattern, the violation symbol indicating a preamble, introductory preamble, or postamble. The frequency synchronization component 148 is configured to perform frequency synchronization based on the first designated data pattern. The duration component 149 is configured to identify the chip duration of data transmission based on a first specified data pattern or a second specified data pattern following the first specified data pattern.

[0039] In some implementations, one or more of the base station 102 or UE 104 include a preamble transmission component 120 for transmitting a preamble, introductory preamble, and / or postamble in association with data transmission.

[0040] Base station 102 configured for 4G LTE (collectively referred to as Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN)) can interface with EPC 160 via a first backhaul link 132 (such as an S1 interface), which can be wired or wireless. Base station 102 configured for 5G NR (collectively referred to as Next Generation RAN (NG-RAN)) can interact with core network 190 via a second backhaul link 184, which can be wired or wireless. Among other functions, base station 102 can also perform one or more of the following functions: user data delivery, radio channel encryption and decryption, integrity protection, header compression, mobility control functions (such as handover, dual connectivity), inter-cell interference coordination, connection establishment and release, load balancing, distribution of Non-Access Stratum (NAS) messages, NAS node selection, synchronization, Radio Access Network (RAN) sharing, Multimedia Broadcast Multicast Service (MBMS), subscriber and equipment tracking, RAN Information Management (RIM), paging, location, and delivery of warning messages. Base stations 102 can communicate with each other directly or indirectly (e.g., via EPC 160 or core network 190) on a third backhaul link 134 (such as an X2 interface). The third backhaul link 134 can be wired or wireless.

[0041] Base station 102 can wirelessly communicate with UE 104. Each base station in base station 102 can provide communication coverage for a corresponding geographic coverage area 110. Overlapping geographic coverage areas 110 may exist. For example, small cell 102' may have a coverage area 110' that overlaps with the coverage areas 110 of one or more macro base stations 102. A network that includes both small cells and macro cells can be referred to as a heterogeneous network. The heterogeneous network may also include evolved home B-nodes (eNBs) (HeNBs) that can provide services to restricted groups referred to as closed subscriber groups (CSGs). The communication link 112 between base station 102 and UE 104 may include UL (also referred to as a reverse link) transmission from UE 104 to base station 102 or DL ​​(also referred to as a forward link) transmission from base station 102 to UE 104. The communication link 112 may use multiple-input multiple-output (MIMO) antenna technologies, including spatial multiplexing, beamforming, or transmit diversity. The communication link may carry one or more carriers. For a total of up to one carrier used for transmission in each direction. Yx MHz ( xFor each carrier allocated in carrier aggregation (of component carriers), base station 102 / UE 104 can use up to [number missing] carriers. Y A spectrum with a bandwidth of MHz (such as 5MHz, 10MHz, 15MHz, 20MHz, 100MHz, 400MHz, etc.). Carriers may be adjacent to each other or may not be adjacent to each other. Carrier allocation may be asymmetric for DL ​​and UL (e.g., more or fewer carriers may be allocated for DL ​​compared to UL). Component carriers may include primary component carriers and one or more secondary component carriers. The primary component carrier may be referred to as the primary cell (PCell) and the secondary component carrier may be referred to as the secondary cell (SCell).

[0042] Some UEs 104 can communicate with each other using device-to-device (D2D) communication link 158. D2D communication link 158 can use DL / UL WWAN spectrum. D2D communication link 158 can use one or more sidelink channels, such as Physical Sidelink Broadcast Channel (PSBCH), Physical Sidelink Discovery Channel (PSDCH), Physical Sidelink Shared Channel (PSSCH), and Physical Sidelink Control Channel (PSCCH). D2D communication can be achieved through various wireless D2D communication systems, such as FlashLinQ, WiMedia, Bluetooth, ZigBee, Wi-Fi based on the IEEE 802.11 standard, LTE, or NR.

[0043] The wireless communication system may also include a Wi-Fi access point (AP) 150 that communicates with a Wi-Fi station (STA) 152 via a communication link 154 in the 5 GHz unlicensed spectrum. When communicating in the unlicensed spectrum, the STA 152 / AP 150 may perform a free channel assessment (CCA) to determine the availability of a channel before communication.

[0044] Small cell 102' can operate in licensed or unlicensed spectrum. When operating in unlicensed spectrum, small cell 102' can employ NR, and uses the same 5 GHz unlicensed spectrum as the Wi-Fi AP 150. Small cell 102' employing NR in unlicensed spectrum can enhance coverage of the access network or increase the capacity of the access network.

[0045] Whether it is a small cell 102' or a large cell (such as a macro base station), base station 102 may include an eNB, gNodeB (gNB) or other types of base stations. Some base stations (such as gNB 180) can operate in one or more frequency bands within the electromagnetic spectrum.

[0046] The electromagnetic spectrum is typically subdivided into various categories, bands, channels, etc., based on frequency / wavelength. In 5G NR, two initial operating bands have been designated as frequency ranges FR1 (410MHz to 7.125GHz) and FR2 (24.25GHz to 52.6GHz). The frequencies between FR1 and FR2 are generally referred to as mid-band frequencies. Although a portion of FR1 is greater than 6GHz, in various documents and articles, FR1 is often (interchangeably) referred to as the "sub-6GHz" band. Similar naming issues sometimes arise with FR2, although it is often (interchangeably) referred to as the "millimeter wave" (mmW) band in various documents and articles, despite being different from the extremely high frequency (EHF) band (30GHz to 300GHz) as defined by the International Telecommunication Union (ITU).

[0047] Considering the above aspects, unless otherwise specifically stated, it should be understood that, as used herein, the term "below 6 GHz" and the like can broadly refer to frequencies less than 6 GHz, within FR1, or including intermediate frequency band frequencies. Furthermore, unless otherwise specifically stated, it should be understood that, as used herein, the term "millimeter wave" and the like can broadly refer to frequencies including intermediate frequency band frequencies, within FR2, or within the EHF band. Communication using the mmW radio frequency band has extremely high path loss and short range. The mmW base station 180 can utilize beamforming 182 with the UE 104 to compensate for path loss and short range.

[0048] EPC 160 may include Mobility Management Entity (MME) 162, other MMEs 164, Serving Gateway 166, Multimedia Broadcast Multicast Service (MBMS) Gateway 168, Broadcast Multicast Service Center (BM-SC) 170, and Packet Data Network (PDN) Gateway 172. MME 162 can communicate with Home Subscriber Server (HSS) 174. MME 162 is the control node that handles signaling between UE 104 and EPC 160. Generally, MME 162 provides bearer and connection management. All user Internet Protocol (IP) packets are delivered through Serving Gateway 166, which is itself connected to PDN Gateway 172. PDN Gateway 172 provides UE IP address allocation and other functions. PDN Gateway 172 and BM-SC 170 are connected to IP Service 176. IP Service 176 may include the Internet, intranet, IP Multimedia Subsystem (IMS), PS streaming service, or other IP services. The BM-SC 170 provides functions for MBMS user service dispatch and delivery. The BM-SC 170 can act as an entry point for content provider MBMS transmission, authorize and initiate MBMS bearer services in a Public Land Mobile Network (PLMN), and schedule MBMS transmissions. The MBMS gateway 168 can allocate MBMS services to base station 102 belonging to a Broadcast-Specific Service Multicast Single Frequency Network (MBSFN) area, and is responsible for session management (start / stop) and collecting eMBMS-related billing information.

[0049] The core network 190 may include Access and Mobility Management Functions (AMF) 192, other AMFs 193, Session Management Functions (SMF) 194, and User Plane Functions (UPF) 195. AMF 192 can communicate with Unified Data Management (UDM) 196. AMF 192 is the control node that handles signaling between UE 104 and the core network 190. Generally, AMF 192 provides QoS flow and session management. All user Internet Protocol (IP) packets are delivered through UPF 195. UPF 195 provides UE IP address allocation and other functions. UPF 195 connects to IP services 197. IP services 197 may include the Internet, intranets, IP Multimedia Subsystem (IMS), PS streaming service, or other IP services.

[0050] While the following description may focus on 5G NR, the concepts described herein may apply to other similar areas such as LTE, LTE-A, CDMA, GSM and other wireless technologies, including future 6G technologies.

[0051] Figure 2A This is an example illustration of the first frame, shown in Figure 200. Figure 2BFigure 230 illustrates an example of a DL channel within a subframe. Figure 2C This is an example illustration of the second frame, shown in Figure 250. Figure 2D Figure 280 illustrates an example of a subframe. The 5G NR frame structure can be FDD, where subframes within a specific set of subcarriers (carrier system bandwidth) are dedicated to either DL or UL, or it can be TDD, where subframes within a specific set of subcarriers (carrier system bandwidth) are dedicated to both DL and UL. A subset of the total cell bandwidth is called a bandwidth portion (BWP), and bandwidth adaptation is achieved by using BWPs to configure the UE and informing the UE which of the configured BWPs is currently active. In one aspect, a narrow bandwidth portion (NBWP) refers to a BWP with a bandwidth less than or equal to the maximum configurable bandwidth of the BWP. The bandwidth of an NBWP is less than the carrier system bandwidth.

[0052] exist Figure 2A , Figure 2C In the provided example, the 5G NR frame structure is assumed to be TDD, where subframe 4 is configured using slot format 28 (most of which are DL), where D is DL, U is UL, and X can be flexibly used between DL / UL, and subframe 3 is configured using slot format 34 (most of which are UL). Although subframes 3 and 4 are shown as having slot formats 34 and 28 respectively, any particular subframe can be configured using any of the various available slot formats 0-61. Slot formats 0 and 1 are both DL and UL, respectively. Other slot formats 2-61 include a mixture of DL, UL, and flexible symbols. The slot format is configured for the UE via the received Slot Format Indicator (SFI) (dynamically configured via DL Control Information (DCI) or semi-statically / statically configured via Radio Resource Control (RRC) signaling). Note that the following description also applies to the 5G NR frame structure as TDD.

[0053] Other wireless communication technologies may have different frame structures or different channels. A frame (10 milliseconds (ms)) can be divided into 10 subframes of equal size (1ms). Each subframe may include one or more time slots. Subframes may also include mini-time slots, which may include 7, 4, or 2 symbols. Each time slot may include 7 or 14 symbols, depending on the time slot configuration. For time slot configuration 0, each time slot may include 14 symbols, and for time slot configuration 1, each time slot may include 7 symbols. Symbols on the DL can be Cyclic Prefix (CP) OFDM (CP-OFDM) symbols. Symbols on the UL can be CP-OFDM symbols (for high-throughput scenarios) or Discrete Fourier Transform (DFT) Extended OFDM (DFT-s-OFDM) symbols (also known as Single Carrier Frequency Division Multiple Access (SC-FDMA) symbols) (for power-constrained scenarios; limited to single-stream transmission). The number of time slots within a subframe is based on the time slot configuration and parameter set (numerology). For slot configuration 0, different parameter sets µ 0 through 5 allow each subframe to have 1, 2, 4, 8, 16, and 32 slots, respectively. For slot configuration 1, different parameter sets 0 through 2 allow each subframe to have 2, 4, and 8 slots, respectively. Accordingly, for slot configuration 0 and parameter set µ, there are 14 symbols per slot and 2 per subframe. µ Each time slot. Subcarrier spacing and symbol length / duration are functions of the parameter set. Subcarrier spacing can be equal to... ,in The parameter sets are 0 to 5. Therefore, the subcarrier spacing is 15 kHz for parameter set µ=0 and 480 kHz for parameter set µ=5. The symbol length / duration is negatively correlated with the subcarrier spacing. Figures 2A to 2D Examples are provided for slot configuration 0 with 14 symbols per slot and parameter set µ=2 with 4 slots per subframe. The slot duration is 0.25 ms, the subcarrier spacing is 60 kHz, and the symbol duration is approximately 16.67 microseconds (μs).

[0054] A resource grid can be used to represent the frame structure. Each time slot consists of a resource block (RB) extending for 12 consecutive subcarriers (also known as a physical RB (PRB)). The resource grid is divided into multiple resource elements (REs). The number of bits carried by each RE depends on the modulation scheme.

[0055] like Figure 2A As illustrated, some of the REs carry reference (pilot) signals (RS) for the UE. The RS may include a demodulated RS (DM-RS) for channel estimation at the UE (indicated as R for a particular configuration). x(where 100x is the port number, but other DM-RS configurations are possible) and Channel State Information Reference Signal (CSI-RS). RS may also include Beam Measurement RS (BRS), Beam Refinement RS (BRRS), and Phase Tracking RS (PT-RS).

[0056] Figure 2B Examples of various DL channels within a subframe of a frame are illustrated. The Physical Downlink Control Channel (PDCCH) carries the DCI within one or more Control Channel Elements (CCEs), each CCE comprising nine RE Groups (REGs), each REG comprising four consecutive REs in an OFDM symbol. The Primary Synchronization Signal (PSS) is located within symbol 2 of a specific subframe of the frame. The PSS is used by the UE 104 to determine subframe / symbol timing and L1 identification. The Secondary Synchronization Signal (SSS) is located within symbol 4 of a specific subframe of the frame. The SSS is used by the UE to determine the L1 Cell Identifier Group Number and radio frame timing. Based on the L1 Identifier and L1 Cell Identifier Group Number, the UE can determine the Physical Cell Identifier (PCI). Based on the PCI, the UE can determine the location of the aforementioned DM-RS. The Physical Broadcast Channel (PBCH) carrying the Primary Information Block (MIB) can logically group with the PSS and SSS to form a Synchronization Signal (SS) / PBCH Block (SSB). The MIB provides the System Frame Number (SFN) and the number of Restricted Blocks (RBs) in the system bandwidth. The Physical Downlink Shared Channel (PDSCH) carries user data, broadcast system information (such as System Information Blocks (SIBs)) not transmitted via the PBCH, and paging messages.

[0057] like Figure 2C As illustrated, some REs in the REs carry DM-RS (indicated as R for one particular configuration, but other DM-RS configurations are possible) for channel estimation at the base station. The UE can transmit DM-RS for the Physical Uplink Control Channel (PUCCH) and DM-RS for the Physical Uplink Shared Channel (PUSCH). The PUSCH DM-RS can be transmitted in the first or first two symbols of the PUSCH. Depending on whether a short or long PUCCH is transmitted and depending on the specific PUCCH format used, the PUCCH DM-RS can be transmitted in different configurations. The UE can transmit a Sounding Reference Signal (SRS). The SRS can be transmitted in the last symbol of a subframe. The SRS can have a comb structure, and the UE can transmit the SRS on one of the comb teeth. The SRS can be used by the base station for channel quality estimation to enable frequency-dependent scheduling of the UL.

[0058] Figure 2DExamples of various UL channels within a subframe of a frame are illustrated. The PUCCH can be located as indicated in one configuration. The PUCCH carries uplink control information (UCI), such as scheduling requests, channel quality indicators (CQI), pre-decoding matrix indicators (PMI), rank indicators (RI), and HARQ ACK / NACK feedback. The PUSCH carries data, and can also be used to carry buffer status reports (BSR), power clearance reports (PHR), or UCI.

[0059] Figure 3 This is an example diagram of base station 310 and UE 350 in the access network. In the DL, IP packets from EPC 160 can be provided to controller / processor 375. Controller / processor 375 implements Layer 3 and Layer 2 functionality. Layer 3 includes the Radio Resource Control (RRC) layer, and Layer 2 includes the Service Data Adaptation Protocol (SDAP) layer, Packet Data Convergence Protocol (PDCP) layer, Radio Link Control (RLC) layer, and Media Access Control (MAC) layer. The controller / processor 375 provides RRC layer functionality associated with broadcasting system information (such as MIB, SIB), RRC connection control (such as RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release), inter-Radio Access Technology (RAT) mobility, and measurement configuration for UE measurement reporting; PDCP layer functionality associated with header compression / decompression, security (encryption, decryption, integrity protection, integrity verification), and handover support functions; RLC layer functionality associated with the delivery of upper-layer packet data units (PDUs), error correction via ARQ, concatenation, segmentation, and reassembly of RLC service data units (SDUs), resegmentation of RLC data PDUs, and reordering of RLC data PDUs; and MAC layer functionality associated with mapping between logical channels and transport channels, multiplexing of MAC SDUs onto transport blocks (TBs), demultiplexing of MAC SDUs from TBs, scheduling information reporting, error correction via HARQ, priority handling, and logical channel priority ordering.

[0060] Transmit (TX) processor 316 and receive (RX) processor 370 implement Layer 1 functionality associated with various signal processing functions. Layer 1 (which includes the physical (PHY) layer) may include error detection on the transport channel, forward error correction (FEC) decoding / decoding of the transport channel, interleaving, rate matching, mapping to the physical channel, modulation / demodulation of the physical channel, and MIMO antenna processing. TX processor 316 processes the mapping to the signal constellation based on various modulation schemes such as binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), M-phase shift keying (M-PSK), and M-quadrature amplitude modulation (M-QAM). Decoded and modulated symbols can be split into parallel streams. Each stream can be mapped to OFDM subcarriers, multiplexed with a reference signal (such as a pilot) in the time or frequency domain, and combined using inverse fast Fourier transform (IFFT) to generate a physical channel carrying a stream of time-domain OFDM symbols. The OFDM streams are spatially pre-decoded to generate multiple spatial streams. The channel estimate from channel estimator 374 can be used to determine the decoding and modulation scheme, as well as for spatial processing. The channel estimate can be derived from a reference signal or channel condition feedback transmitted by UE 350. Each spatial stream can be provided to a different antenna 320 via a separate transmitter 318TX. Each transmitter 318TX can modulate an RF carrier with the corresponding spatial stream for transmission.

[0061] At UE 350, each receiver 354RX receives signals via its corresponding antenna 352. Each receiver 354RX recovers the information modulated onto the RF carrier and provides that information to the receive (RX) processor 356. The TX processor 368 and RX processor 356 implement Layer 1 functionality associated with various signal processing functions. The RX processor 356 can perform spatial processing on the information to recover any spatial stream destined for UE 350. If multiple spatial streams are destined for UE 350, the RX processor 356 can combine them into a single OFDM symbol stream. The RX processor 356 uses a Fast Fourier Transform (FFT) to transform this OFDM symbol stream from the time domain to the frequency domain. The frequency domain signal consists of a separate OFDM symbol stream for each subcarrier of the OFDM signal. The symbols on each subcarrier, along with the reference signal, are recovered and demodulated by determining the most probable signal constellation point transmitted by base station 310. These soft decisions can be based on a channel estimate calculated by channel estimator 358. These soft decisions are decoded and deinterleaved to recover the data and control signals originally transmitted by base station 310 on the physical channel. These data and control signals are then provided to controller / processor 359, which implements layer 3 and layer 2 functionality.

[0062] The controller / processor 359 may be associated with a memory 360 that stores program code and data. The memory 360 may be referred to as a computer-readable medium. In the UL, the controller / processor 359 provides demultiplexing, packet reassembly, decryption, header decompression, and control signal processing between transport and logical channels to recover IP packets from the EPC 160. The controller / processor 359 is also responsible for error detection using ACK or NACK protocols to support HARQ operation.

[0063] Similar to the functionality described in conjunction with DL transmission performed by base station 310, controller / processor 359 provides RRC layer functionality associated with system information (such as MIB, SIB) acquisition, RRC connectivity, and measurement reporting; PDCP layer functionality associated with header compression / decompression and security (encryption, decryption, integrity protection, integrity verification); RLC layer functionality associated with the transmission of upper-layer PDUs, error correction via ARQ, concatenation, segmentation, and reassembly of RLC SDUs, resegmentation of RLC data PDUs, and reordering of RLC data PDUs; and MAC layer functionality associated with mapping between logical channels and transport channels, multiplexing of MAC SDUs to TBs, demultiplexing of MAC SDUs from TBs, scheduling information reporting, error correction via HARQ, priority handling, and logical channel priority ordering.

[0064] The TX processor 368 can use the reference signal transmitted from the base station 310 or the channel estimate derived from feedback by the channel estimator 358 to select an appropriate decoding and modulation scheme and facilitate spatial processing. The spatial stream generated by the TX processor 368 can be provided to different antennas 352 via individual transmitters 354TX. Each transmitter 354TX can modulate an RF carrier with the corresponding spatial stream for transmission.

[0065] UL transmission is processed at base station 310 in a manner similar to that described in conjunction with the receiver function at UE 350. Each receiver 318RX receives signals via its corresponding antenna 320. Each receiver 318RX recovers the information modulated onto the RF carrier and provides that information to RX processor 370.

[0066] The controller / processor 375 may be associated with a memory 376 that stores program code and data. The memory 376 may be referred to as a computer-readable medium. In the UL, the controller / processor 375 provides demultiplexing, packet reassembly, decryption, header decompression, and control signal processing between the transport and logical channels to recover IP packets from the UE 350. IP packets from the controller / processor 375 may be provided to the EPC 160. The controller / processor 375 is also responsible for error detection using ACK or NACK protocols to support HARQ operation.

[0067] At least one of the TX processor 368, RX processor 356, and controller / processor 359 can be configured to combine Figure 1 The preamble receiving component 140 performs various functions. For example, memory 360 may include executable instructions that define the preamble receiving component 140. TX processor 368, RX processor 356, and / or controller / processor 359 may be configured to execute the preamble receiving component 140.

[0068] In some specific implementations, the UE 350 can operate as an intermediary device between the base station 310 and the A-IoT device 380. At least one of the TX processor 368, RX processor 356, and controller / processor 359 can be configured to combine Figure 1 The precode transmission component 120 performs various aspects. For example, memory 360 may include executable instructions that define the precode transmission component 120. TX processor 368, RX processor 356, and / or controller / processor 359 may be configured to execute the precode transmission component 120.

[0069] At least one of the TX processor 316, RX processor 370, and controller / processor 375 can be configured to combine Figure 1 The precode transmission component 120 performs various functions. For example, memory 376 may include executable instructions that define the precode transmission component 120. TX processor 316, RX processor 370, and / or controller / processor 375 may be configured to execute the precode transmission component 120.

[0070] A-IoT device 380 may be a wireless device configured for low-power transmission. For example, A-IoT device 380 may be referred to as a Type 1 device with a peak power of approximately 1 μW or a Type 2 (2a or 2b) device with a peak power of less than several hundred μW. A-IoT device 380 may include an antenna 382, ​​a transceiver 384, a processor 386, and a memory 388. The memory 388 may store instructions for the preamble transmission component 120 and / or the preamble reception component 140, and the processor 386 may execute the instructions.

[0071] In some implementations, the A-IoT device 380 is configured for ambient backscatter communication. The A-IoT device 380 can use simple energy harvester circuitry to derive its operating power from received ambient RF signals. The A-IoT device 380 communicates via the absorption and reflection of RF signals. Instead of generating its own RF signal, the A-IoT device 380 transmits by modulating the reflection of the incident RF signal. For example, to transmit, a transceiver 384 can (e.g., from a processor 386) receive streams of one and zero and switch between a non-reflective or absorption state and a reflection state. To receive, the transceiver 384 can compare the received signal to a threshold to determine whether the received signal is in a high-voltage or low-voltage state.

[0072] Figure 4 This is an illustration of an example decomposed base station 400 architecture. The decomposed base station 400 architecture may include one or more central units (CUs) 410, which may communicate directly with the core network 420 via a backhaul link, or indirectly with the core network 420 via one or more decomposed base station units, such as a near real-time (near-RT) RAN Intelligent Controller (RIC) 425 via an E2 link, or a non-real-time (non-RT) RIC 415 associated with a Service Management and Orchestration (SMO) framework 405, or both. CUs 410 may communicate with one or more distributed units (DUs) 430 via appropriate midhaul links (such as F1 interfaces). DUs 430 may communicate with one or more radio units (RUs) 440 via appropriate fronthaul links. RUs 440 may communicate with a corresponding UE 104 via one or more radio frequency (RF) access links. In some implementations, UE 104 may be served simultaneously by multiple RUs 440.

[0073] Each of these units (i.e., CU 410, DU 430, RU 440, and near-RT RIC 425, non-RT RIC 415, and SMO frame 405) may include or be coupled to one or more interfaces configured to receive or transmit signals, data, or information (collectively, signals) via wired or wireless transmission media. Each of these units, or an associated processor or controller providing instructions to the communication interfaces of these units, may be configured to communicate with one or more other units via transmission media. For example, these units may include wired interfaces configured to receive signals or transmit signals to one or more other units via wired transmission media. Additionally, these units may include wireless interfaces that may include receivers, transmitters, or transceivers (such as radio frequency (RF) transceivers) configured to receive signals or transmit signals to one or more other units via wireless transmission media, or both.

[0074] In some aspects, the CU 410 can host one or more higher-level control functions. Such control functions may include Radio Resource Control (RRC), Packet Data Convergence Protocol (PDCP), Serving Data Adaptation Protocol (SDAP), etc. Each control function can be implemented using an interface configured to signal to other control functions hosted by the CU 410. The CU 410 can be configured to handle user plane functionality (i.e., Central Unit-User Plane (CU-UP)), control plane functionality (i.e., Central Unit-Control Plane (CU-CP)), or a combination thereof. In some implementations, the CU 410 can be logically divided into one or more CU-UP units and one or more CU-CP units. When implemented in an O-RAN configuration, the CU-UP units can communicate bidirectionally with the CU-CP units via an interface such as an E1 interface. The CU 410 can be implemented to communicate with the DU 430 for network control and signaling, as needed.

[0075] DU 430 may correspond to a logical unit that includes one or more base station functions for controlling the operation of one or more RU 440s. In some aspects, DU 430 may at least partially host one or more of the Radio Link Control (RLC) layer, Medium Access Control (MAC) layer, and one or more high physical (PHY) layers (such as modules for forward error correction (FEC) encoding and decoding, scrambling, modulation and demodulation, etc.) according to functional splits (such as those defined by the 3rd Generation Partnership Project (3GPP). In some aspects, DU 430 may further host one or more low PHY layers. Each layer (or module) may be implemented using an interface configured to communicate signals with other layers (and modules) hosted by DU 430 or with control functions hosted by CU 410.

[0076] Lower-layer functionality can be implemented by one or more RU 440s. In some deployments, an RU440 controlled by a DU 430 may correspond to a logical node that hosts RF processing functions or low-PHY layer functions (such as performing Fast Fourier Transform (FFT), Inverse FFT (iFFT), digital beamforming, Physical Random Access Channel (PRACH) extraction and filtering, or both, based at least in part on functional decomposition (such as lower-layer functional decomposition). In such architectures, the RU 440 may be implemented to handle over-the-air (OTA) communications with one or more UE 104s. In some specific implementations, the real-time and non-real-time aspects of control plane and user plane communications with the RU 440 may be controlled by the corresponding DU 430. In some scenarios, this configuration allows the DU 430 and CU 410 to be implemented in a cloud-based RAN architecture (such as a vRAN architecture).

[0077] SMO framework 405 can be configured to support RAN deployment and provisioning of both non-virtualized and virtualized network elements. For non-virtualized network elements, SMO framework 405 can be configured to support the deployment of dedicated physical resources for RAN coverage requirements, which can be managed via operation and maintenance interfaces such as the O1 interface. For virtualized network elements, SMO framework 405 can be configured to interact with cloud computing platforms such as Open Cloud (O-Cloud) 490 to perform network element lifecycle management (such as instantiating virtualized network elements) via cloud computing platform interfaces such as the O2 interface. Such virtualized network elements may include, but are not limited to, CU 410, DU 430, RU 440, and near-RT RIC 425. In some implementations, SMO framework 405 can communicate with hardware aspects of the 4G RAN, such as Open eNB (O-eNB) 411, via the O1 interface. Additionally, in some implementations, SMO framework 405 can communicate directly with one or more RU 440s via the O1 interface. SMO framework 405 may also include a non-RT RIC 415 configured to support the functionality of SMO framework 405.

[0078] The non-RT RIC 415 can be configured to include logical functions that enable non-real-time control and optimization of RAN elements and resources, including artificial intelligence / machine learning (AI / ML) workflows for model training and updates, or policy-based guidance for applications / features in the near-RT RIC 425. The non-RT RIC 415 can be coupled to or communicate with the near-RT RIC 425, such as via an A1 interface. The near-RT RIC 425 can be configured to include logical functions that enable near real-time control and optimization of RAN elements and resources via an interface, such as via an E2 interface, through data collection and action, connecting one or more CU 410s, one or more DU 430s, or both, and O-eNBs to the near-RT RIC 425.

[0079] In some implementations, to generate AI / ML models to be deployed in the near-RT RIC 425, the non-RT RIC 415 may receive parameters or external enrichment information from an external server. This information can be utilized by the near-RT RIC 425 and can be received from non-network data sources or network functions at the SMO framework 405 or the non-RT RIC 415. In some examples, the non-RT RIC 415 or the near-RT RIC 425 may be configured to tune RAN behavior or performance. For example, the non-RT RIC 415 may monitor long-term trends and patterns in performance and use AI / ML models to perform corrective actions via the SMO framework 405 (such as reconfiguration via O1) or by creating RAN management policies (such as A1 policies).

[0080] Figure 5 This is a diagram illustrating an example of transmission using a preamble that includes one or more designated symbols used to indicate the preamble.

[0081] The first example transmission 500 includes a designated symbol 502, a first designated data mode 504, a second designated data mode 506, and data transmission 508. The designated symbol 502 can refer to a symbol with a duration much longer than the symbol or chip of code data. For example, the duration of the designated symbol 502 can be defined as a number of microseconds (μs) or a number of data chips. The designated symbol 502 may not have a transition. That is, the designated symbol 502 can be transmitted with a single output voltage, which can be a high output voltage. The designated symbol 502 can indicate the presence of a preamble 510, which can be a preamble.

[0082] The first specified data mode 504 can be used for frequency synchronization. The first specified data mode 504 has a fixed chip duration. Thus, the frequency of the first specified data mode 504 can be measured. The second specified data mode 506 can be used as a chip duration indicator. The chip duration of the second specified data mode 506 varies based on the chip duration of the data transmission 508. For example, the chip duration of the second specified data mode 506 can be a multiple of the chip duration of the data transmission 508.

[0083] The second example transmission 520 includes a designation symbol 502, a single designated data pattern 524, and a data transmission 528. The designation symbol 502 may indicate the start of a preamble 530. The single designated data pattern 524 may be used for both frequency synchronization and chip duration indication. The chip duration of the single designated data pattern 524 may be fixed to allow for frequency synchronization. The single designated data pattern 524 may have a sequence indicating the chip duration. For example, the sequence may indicate two bits mapped to different multiples or fractions of the chip duration of the single designated data pattern 524. In an example mapping, the value "00" indicates the same duration, the value "01" indicates half the duration, the value "10" indicates a quarter of the duration, and the value "11" indicates an eighth of the duration.

[0084] The third example transmission 540 includes a first designated symbol 522, a second designated symbol 544, and a designated data pattern 524. The first designated symbol 522 has a predefined minimum duration, but not necessarily a predefined duration. The first designated symbol 522 has a single output voltage (low or high). The second designated symbol 544 has a fixed duration and a single output voltage opposite to that of the first designated symbol 522. The presence of the two designated symbols with different output voltages improves the detectability of the preamble 550, which is exemplified as a preamble. The designated data pattern 546 may be similar to the single designated data pattern 524 and can be used for both frequency synchronization and indication of the chip duration for data transmission 548.

[0085] In some specific implementations, the prefix codes 510, 530, or 550 may be repeated once or multiple times.

[0086] Figure 6 This diagram illustrates an example of transmission using a line code violation of Manchester code, which is used to indicate the guide code. The line code can indicate a pattern representing digital data transmitted over a communication channel. For example, symbols representing 0 or 1 can be represented by one or more voltage levels or by transitions over chip duration. A line code violation is a symbol that does not conform to the rules for a particular line code. In one aspect, a line code violation can indicate a guide code. For example, in some implementations, specifying data patterns 504, 506, 524, or 546 may include a line code violation. In some implementations where a line code violation exists to indicate a guide code, the guide code may not include the specified symbols 502, 522, 542, or 544.

[0087] Transmission 600 illustrates a sequence transmitted in Manchester code, where no line code violation exists. In Manchester code, 1 represents a high voltage level transitioning to a low voltage level within a symbol, and 0 represents a low voltage level transitioning to a high voltage level within a symbol. Transmission 600 has the sequence "100110". Line code violations for Manchester code can include symbols that do not have a transition. Such symbols may be referred to as violation symbols. Furthermore, line code violations can be defined by whether the transition occurs at a symbol edge between a violation symbol and a normal symbol or another violation symbol.

[0088] Transmission 620 shows the same sequence as transmission 600, with violation symbols in the second, third, and fifth symbols. There is no transition at the leading edge of the violation symbol following either a normal symbol or another violation symbol. For example, the second bit is represented by a low voltage without transition, and the third bit is represented by another low voltage without transition. Similarly, the violation symbol for the fifth bit is represented by a low voltage without transition.

[0089] Transmission 640 shows the same sequence as transmission 600, with violation symbols in the second, third, and fifth symbols. A transition occurs at the leading edge of the violation symbol following either a normal symbol or another violation symbol. The second symbol transitions to high voltage at the leading edge, and the third symbol transitions to low voltage at the leading edge. Similarly, the fifth symbol has a transition to high voltage.

[0090] Transmitter 640 shows the same sequence as Transmitter 600, with violation symbols in the second, third, and fifth symbols. The output voltage for a symbol with a line code violation is predefined based on the value for the symbol. For example, 0 is represented by a low voltage with no transition, and 1 is represented by a high voltage with no transition. Therefore, the second and third symbols have low voltages, and the fifth symbol has a high voltage.

[0091] Figure 7 This diagram illustrates an example of a transmission using Pulse Interval Encoded (PIE) codes to indicate a line code violation. The PIE code uses the length of a high-voltage pulse preceding a transition in the middle of a symbol to indicate the value. A transition occurs at the leading edge of each symbol. Transmission 700 has the sequence "100110" decoded using PIE codes, where no line code violation occurs. Line code violations for PIE codes can include no transition in the middle of the violation symbol, an inversion of the high and low output levels for the violation symbol, or a configured output level for the violation symbol.

[0092] The 720 transmission includes a line code violation where there is no transition in the middle of the violation symbol and no transition between two violation symbols. The line code violation occurs in the second, third, and fifth symbols. The second symbol has a transition to high voltage at the leading edge but no transition in the middle. The third symbol does not transition at the leading edge after the violation symbol and remains at high voltage. The fifth symbol has a transition at the leading edge and remains at high voltage.

[0093] Transmitting 740 includes a line code violation, where there is no transition at the symbol edge between the normal and violation symbols, but a transition exists between the two violation symbols. Therefore, the second symbol remains low voltage after the first symbol, but the third symbol transitions to high voltage. The fifth symbol has a transition at the leading edge and remains low voltage.

[0094] Sending 760 includes a line code violation, where the high and low levels are reversed. That is, in the second, third, and fifth symbols, the voltage starts low and then transitions to high.

[0095] The 780 transmission includes line code violations, where the output voltage of the violation symbol is configured based on a value that has not changed. For example, the second and third symbols with a value of 0 have a low voltage, and the fifth symbol with a value of 1 has a high voltage.

[0096] Figure 8 This is a diagram illustrating an example of a line code violation in a frequency modulation (FM) code used to indicate the lead. In FM codes such as FM0, there is a transition at the leading edge of each symbol, and symbols with a value of 0 have a transition in the middle. Transmission 800 has the sequence "100110" decoded using FM0 code, where no line code violation exists. A line code violation in FM codes can include the absence of a transition at the leading edge of the violating symbol. Transmission 820 includes line code violations in the second, third, and fifth symbols. For example, the second symbol does not transition from the high voltage of the first symbol and then transitions to low voltage in the middle of the symbol. The third symbol remains low at the leading edge but transitions to high in the middle of the symbol. The fifth symbol, with a value of 1, remains low after the fourth symbol.

[0097] Figure 9This diagram illustrates an example of a transmission using Miller codes to indicate line code violations. In Miller codes, a binary 1 is represented by a transition in the middle of a bit, and a binary 0 is represented by no transition after a binary 1, or by a transition between bits representing consecutive 0s. Baseband Miller codes may include a value M indicating the number of subcarrier cycles per bit. For example, the illustrated transmission has M=2, where a phase inversion occurs in the middle of a symbol for a binary 1. Transmission 900 has the sequence "100110" decoded using Miller codes of M=2, and where no line code violation occurs. For Miller codes, symbol rule violations may include a missing transition at the symbol edge of a violation symbol or no transition in the middle of a violation symbol. When a symbol rule violation includes no transition at the symbol edge, a violation symbol with a value of 0 may not follow a normal symbol with a value of 0.

[0098] Sending 920 includes line code violations, where there is no transition at the symbol edge between the normal and violation symbols, but a transition exists between two violation symbols. In the second symbol, the signal is not inverted at the symbol edge. In the third symbol, for a value of 0, the signal is inverted because the third symbol is a violation symbol. The fifth symbol has no transition at the leading edge.

[0099] Sending 940 includes line code violations where there is no transition in the middle of the violation symbol, and a transition at the symbol edge between the normal and violation symbols, but no transition between two violation symbols. The second, third, and fifth symbols are violation symbols. The second symbol transitions to low voltage at the leading edge. The third symbol does not transition at the leading edge and does not transition in the middle. The fifth symbol has a transition at the leading edge.

[0100] Sending 960 includes a line code violation, where there is no transition in the middle of the violation symbol, a transition occurs at the symbol edge between the normal and violation symbols, and a transition exists between the two violation symbols. The second symbol transitions to low voltage at the leading edge. The third symbol transitions to high voltage at the leading edge. The fifth symbol does not transition at the leading edge and remains at high voltage.

[0101] Sending 980 includes a line code violation, wherein there is no transition in the middle of the violation symbol, no transition at the symbol edge between the normal symbol and the violation symbol rule, and no transition between the two violation symbols. The second symbol does not include a transition at the leading edge and remains at high voltage. Similarly, the third and fifth symbols do not include a transition at the leading edge and remain at high voltage.

[0102] Figure 10This is a diagram illustrating a preamble and an example of data transmission with different line codes. Furthermore, the line codes can differ for the first and second specified data modes of the preamble. For example, the use of different line codes may be limited due to the potential ambiguity between the preamble symbol of one line code and the data symbol of another.

[0103] For example, if data is to be transmitted using PIE code, the first specified data pattern can use Manchester code, FM0, or Miller code, and includes symbols with values ​​of both 0 and 1. However, due to different chip durations, the second specified data pattern includes at least one symbol with a value of 1 in the PIE code. Transmission 1000 includes a first specified data pattern having a sequence "101" using Manchester code, a second specified data pattern having a sequence "10" using PIE code, and data with PIE code. Transmission 1020 includes a first specified data pattern having a sequence "101" using Manchester code, a second specified data pattern having a sequence "1" using PIE code, and data with PIE code. In the illustrated example, the chip duration of the data can be indicated by the second specified data pattern.

[0104] In some specific implementations, when data is encoded using FM0, the preamble cannot be Manchester code. Conversely, when data is encoded using Manchester code, if the preamble uses FM0 as the line code, the preamble sequence should include at least one 1 and one 0. When data is encoded using Manchester code, the preamble cannot be Miller code. When data is encoded using Miller code, if the preamble uses FM0 as the line code, the preamble sequence should include at least one 1 and one 0. When data is encoded using Miller code, the preamble cannot be Manchester code.

[0105] Figure 11 This diagram illustrates an example of a preamble with a chip duration that is a multiple of the chip duration of data transmission (1100). For example, the chip duration of preamble 1120 is twice the bit / chip duration of the data. The chip duration of preamble 1140 is three times the bit / chip duration of the data. The chip duration of preamble 1160 is four times the bit / chip duration of the data. A longer chip duration for the preamble improves coverage and decoding success rate for the preamble. In specific implementations where the chip duration of the first specified data mode of the preamble is fixed to allow frequency synchronization, the preamble may include a second specified data mode with a variable duration to indicate the chip duration of data transmission.

[0106] Figure 12 Figure 1200 illustrates the transmission of a preamble at a single frequency and data at multiple frequencies. A single frequency for the preamble simplifies detection and improves coverage. Multiple frequencies (e.g., multiple carriers) for the data can increase bandwidth or data rate.

[0107] Figure 13 This is a conceptual data flow diagram 1300 illustrating the data flow between different parts / components in example UE 104, which may be UE 104 ( Figure 1 Examples include a preamble receiving component 140. The preamble receiving component 140 may be implemented by a memory 360 and a TX processor 368, an RX processor 356, and / or a controller / processor 359. For example, the memory 360 may store executable instructions defining the preamble receiving component 140, and the TX processor 368, RX processor 356, and / or controller / processor 359 may execute these instructions.

[0108] UE 104 may include receiver component 1370, which may include, for example, an RF receiver for receiving the signals described herein. UE 104 may include transmitter component 1372, which may include, for example, an RF transmitter for transmitting the signals described herein. In one aspect, receiver component 1370 and transmitter component 1372 may be co-located at a transceiver (such as...) Figure 3 In TX / RX 352). In some specific implementations, where UE 104 is an A-IoT device 106 or 380, the transceiver can be a backscatter transceiver, such as Figure 3 The transceiver in the 384.

[0109] For example, for Figure 1 The preamble receiving component 140 discussed includes a preamble detection component 142, a pattern recognition component 144, a rule violation component 146, a frequency synchronization component 148, and a time-lapse component 149.

[0110] Receiver component 1370 can receive the DL signals described herein, including any one of the following transmit signals: 500, 520, 540, 600, 620, 640, 660, 700, 720, 740, 760, 780, 800, 820, 900, 920, 940, 960, 980, 1000, or 1020. Receiver component 1370 can output the received signal to one or both of preamble detection component 142 and rule violation component 146. For example, the received signal can be a binary signal represented as high and low voltage.

[0111] The preamble detection component 142 is configured to detect a preamble indicated by a designated symbol (such as designated symbols 502, 522, or a first designated symbol 542 and a second designated symbol 544). The preamble detection component 142 may detect the designated symbol based on the duration for which the received signal sustains a minimum or fixed voltage. For example, when the preamble detection component detects a high voltage at designated symbol 502, the preamble detection component 142 indicates the presence of a preamble and the start of a designated data pattern following the designated symbol.

[0112] Rule violation component 146 is configured to detect a preamble indicated by a line code rule violation. Rule violation component 146 can be configured to analyze the received signal to determine whether the received signal conforms to a configured line code. For example, the configured line code may be specified in a standard. When rule violation component 146 detects a line code rule violation, rule violation component 146 can indicate the presence of a preamble and a specified data pattern in the event of a line code rule violation.

[0113] Pattern recognition component 144 may receive indications of preambles from preamble detection component 142 or rule violation component 146. Pattern recognition component 144 is configured to receive at least a first specified data pattern, such as specified data pattern 504, 524, or 546. Pattern recognition component 144 may apply a configured line code of the first specified data pattern to detect symbols of the specified data pattern. In some embodiments, where the specified data pattern has a fixed length, pattern recognition component 144 may output the specified data pattern to a frequency synchronization component. In some embodiments, the received signal may include a second specified data pattern 506 indicating the chip duration of data transmission. Pattern recognition component 144 may output the second specified data pattern 506 to duration component 149.

[0114] Frequency synchronization component 148 can receive a specified data pattern of fixed length from pattern recognition component 144. Frequency synchronization component 144 is configured to perform frequency synchronization based on a first specified data pattern.

[0115] The timing component 149 is configured to receive a specified data pattern indicating the chip duration of data transmission. In some embodiments, the specified data pattern has a sequence indicating the chip duration of data transmission. In some embodiments, the specified data pattern has a chip duration indicating the chip duration of data transmission. The timing component 149 can be configured using tables or formulas to calculate the chip duration of data transmission based on the specified data pattern. The timing component 149 can output the chip duration of data transmission.

[0116] In some implementations, UE 104 includes a decoder 1310 configured to decode data transmissions. Decoder 1310 may receive a frequency synchronization signal from frequency synchronization component 148. Decoder 1310 may receive chip duration from duration component 149. Decoder 1310 may apply line codes to received data transmissions (e.g., after a preamble) based on chip duration to decode each symbol of the data transmission.

[0117] In some implementations, UE 104 includes a data source 1320. Data source 1320 may store or generate data for transmission by UE 104. For example, data source 1320 may generate data for transmission in response to a command or information received at decoder 1310. Data source 1320 may transmit control signals to precode transmission component 120 to generate one or more precodes conforming to a configured format, which may be selected from the transmission formats described herein. Precode transmission component 120 may be configured to generate precodes based on the configured format and output the precodes to transmitter component 1372 for transmission via an antenna. Data source 1320 may then output data to transmitter component 1372 for transmission, for example, by encoding with a configured line code for data transmission.

[0118] Figure 14 This is a flowchart of an example method 1400 for a receiving device to receive transmitted preambles (e.g., preambles, intermembs, or postcodes). Method 1400 may be performed by a UE (such as UE 104, which may include memory 360 and may be the entire UE 104 or components of UE 104, such as preamble receiving component 140, TX processor 368, RX processor 356, or controller / processor 359). Method 1400 may be performed by preamble receiving component 140 communicating with preamble transmitting components of one or more base stations 102, other UEs, or A-IoT devices 106. Optional boxes are shown in dashed lines.

[0119] At block 1410, method 1400 includes receiving a designation symbol indicating the start of a preamble, introductory code, or postcode. In some embodiments, for example, UE 104, RX processor 356, or controller / processor 359 may execute preamble receiving component 140 or preamble detection component 142 to receive designation symbols 502, 522, 542, 544 indicating the start of a preamble, introductory code, or postcode. In some embodiments, the designation symbol includes a first designation symbol having a minimum length with a single output voltage and a second designation symbol having a fixed length with a single output voltage. Therefore, UE 104, RX processor 356, or controller / processor 359 executing preamble receiving component 140 or preamble detection component 142 may provide components for receiving designation symbols indicating the start of a preamble, introductory code, or postcode.

[0120] At block 1420, method 1400 includes receiving a first specified data pattern after a specified symbol, wherein the duration of the specified symbol is greater than the duration of the first specified data pattern. In some specific implementations, for example, UE 104, RX processor 356, or controller / processor 359 may execute preamble receiving component 140 or pattern recognition component 144 to receive the first specified data pattern 504, 524 after a specified symbol. The duration of specified symbols 502, 522, 542, 544 is greater than the duration of the first specified data pattern 504, 524. Therefore, UE 104, RX processor 356, or controller / processor 359 executing preamble receiving component 140 or pattern recognition component 144 may provide components for receiving the first specified data pattern after a specified symbol, wherein the duration of the specified symbol is greater than the duration of the first specified data pattern.

[0121] At block 1430, method 1400 includes performing frequency synchronization based on a first specified data pattern. In some specific implementations, for example, UE 104, TX processor 368, or controller / processor 359 may execute preamble receiving component 140 or frequency synchronization component 148 to perform frequency synchronization based on the first specified data pattern. Therefore, UE 104, TX processor 368, or controller / processor 359 executing preamble receiving component 140 or frequency synchronization component 148 may provide components for performing frequency synchronization based on the first specified data pattern.

[0122] At block 1440, method 1400 includes identifying the chip duration of data transmission based on a first specified data pattern or a second specified data pattern following the first specified data pattern. In some embodiments, for example, UE 104, RX processor 356, or controller / processor 359 may execute preamble receiving component 140 or timing component 149 to identify the chip duration of data transmission based on the first specified data pattern or a second specified data pattern following the first specified data pattern. In some embodiments, the first specified data pattern is fixed, and the second specified data pattern varies based on the chip duration of data transmission, thus identifying the chip duration of data transmission is based on the second specified data pattern. In some embodiments, the first specified data pattern is a unique data pattern for a preamble, introductory code, or postamble, and identifying the chip duration of data transmission is based on a sequence of the first specified data pattern. For example, a sequence of the first specified data pattern may indicate the relationship between the chip duration of the first specified data pattern or the data rate and the chip duration of data transmission. Therefore, the UE 104, RX processor 356, or controller / processor 359 performing the preamble receiving component 140 or the timing component 149 may provide components for identifying the chip timing of data transmission based on a first specified data mode or a second specified data mode following the first specified data mode.

[0123] Figure 15 This is a flowchart of an example method 1500 for a receiving device to receive transmitted preambles (e.g., preambles, intermembs, or postcodes). Method 1400 may be performed by a UE (such as UE 104, which may include memory 360 and may be the entire UE 104 or components of UE 104, such as preamble receiving component 140, TX processor 368, RX processor 356, or controller / processor 359). Method 15 may be performed by preamble receiving component 140 communicating with preamble transmitting components of one or more base stations 102, other UEs, or A-IoT devices 106. Optional boxes are shown in dashed lines.

[0124] At block 1510, method 1500 includes: receiving a first designated data pattern comprising a plurality of symbols encoded with line codes, wherein the first designated data pattern has a symbol rule violation of line codes in violation symbols indicating preambles, introductory codes, or postcodes. In some embodiments, for example, UE 104, RX processor 356, or controller / processor 359 may execute preamble receiving component 140 or rule violation component 146 to receive the first designated data pattern comprising a plurality of symbols encoded with line codes, wherein the first designated data pattern has a symbol rule violation of line codes in violation symbols indicating preambles, introductory codes, or postcodes. In some embodiments, the designated symbols include a first designated symbol of minimum length having a single output voltage and a second designated symbol of fixed length having a single output voltage. Therefore, the UE 104, RX processor 356, or controller / processor 359 performing the preamble receiving component 140 or the preamble detection component 142 may provide components for receiving a first specified data pattern comprising a plurality of symbols encoded with line codes, wherein the first specified data pattern has a symbol rule violation of the line code in a violation symbol indicating a preamble, intro, or postamble.

[0125] At block 1520, method 1400 includes performing frequency synchronization based on a first specified data pattern. In some specific implementations, for example, UE 104, TX processor 368, or controller / processor 359 may execute preamble receiving component 140 or frequency synchronization component 148 to perform frequency synchronization based on the first specified data pattern. Therefore, UE 104, TX processor 368, or controller / processor 359 executing preamble receiving component 140 or frequency synchronization component 148 may provide components for performing frequency synchronization based on the first specified data pattern.

[0126] At block 1530, method 1500 includes identifying the chip duration of data transmission based on a first specified data pattern or a second specified data pattern following the first specified data pattern. In some embodiments, for example, UE 104, RX processor 356, or controller / processor 359 may execute preamble receiving component 140 or timing component 149 to identify the chip duration of data transmission based on the first specified data pattern or a second specified data pattern following the first specified data pattern. In some embodiments, the first specified data pattern is fixed, and the second specified data pattern varies based on the chip duration of data transmission, thus identifying the chip duration of data transmission is based on the second specified data pattern. In some embodiments, the first specified data pattern is a unique data pattern for a preamble, introductory code, or postamble, and identifying the chip duration of data transmission is based on a sequence of the first specified data pattern. For example, a sequence of the first specified data pattern may indicate the relationship between the chip duration of the first specified data pattern or the data rate and the chip duration of data transmission. Therefore, the UE 104, RX processor 356, or controller / processor 359 performing the preamble receiving component 140 or the timing component 149 may provide components for identifying the chip timing of data transmission based on a first specified data mode or a second specified data mode following the first specified data mode.

[0127] The following numbered clauses provide an overview of the various aspects of this disclosure:

[0128] Clause 1. An apparatus for receiving a preamble, introductory code, or postcode for data transmission, the apparatus comprising: one or more memories storing executable instructions; and one or more processors coupled to the one or more memories and configured to execute the instructions to: receive a designated symbol indicating the start of the preamble, introductory code, or postcode; receive a first designated data pattern after the designated symbol, wherein the duration of the designated symbol is greater than the duration of the first designated data pattern; perform frequency synchronization based on the first designated data pattern; and identify the chip duration of the data transmission based on the first designated data pattern or a second designated data pattern following the first designated data pattern.

[0129] Clause 2. The apparatus according to Clause 1, wherein the first specified data pattern is fixed, and the second specified data pattern varies based on the chip duration of the data transmission, and the chip duration of the data transmission is identified as being based on the second specified data pattern.

[0130] Clause 3. The apparatus according to Clause 1 or 2, wherein the first designated data pattern is a unique data pattern of the preamble, introductory code, or postcode, and wherein the chip duration identifying the transmission of the data is based on a sequence of the first designated data pattern.

[0131] Clause 4. The apparatus according to Clause 3, wherein the sequence of the first specified data pattern indicates the relationship between the chip duration or data rate of the first specified data pattern and the chip duration of the data transmission.

[0132] Clause 5. The apparatus according to any one of Clauses 1 to 4, wherein the preamble, introductory code, or postcode is repeated once or more for the transmission of the data.

[0133] Clause 6. The apparatus according to any one of Clauses 1 to 4, wherein the designation symbol comprises a first designation symbol having a minimum length having a single output voltage and a second designation symbol having a fixed length having a single output voltage.

[0134] Clause 7. An apparatus for receiving a preamble, introductory code, or postamble for data transmission, the apparatus comprising: one or more memories storing executable instructions; and one or more processors coupled to the one or more memories and configured to execute the instructions to: receive a first designated data pattern comprising a plurality of symbols encoded with line codes, wherein the first designated data pattern has a symbol rule violation of the line code in a violation symbol indicating the preamble, introductory code, or postamble; perform frequency synchronization based on the first designated data pattern; and identify the chip duration of the data transmission based on the first designated data pattern or a second designated data pattern following the first designated data pattern.

[0135] Clause 8. The apparatus according to Clause 7, wherein the line code is Manchester code, and the symbol rule violation includes the absence of a transition in the middle of the violation symbol, and the rule defines whether the transition occurs at the symbol edge between the violation symbol and a normal symbol or another violation symbol.

[0136] Clause 9. The apparatus according to Clause 7 or 8, wherein the line code is a PIE code, and the symbol rule violation includes a missing transition in the middle of the violating symbol, an inversion of the high and low output levels for the violating symbol, or a configured output level for the violating symbol.

[0137] Clause 10. The apparatus according to Clause 7 or 8, wherein the line code is Miller code, and the symbol rule violation includes the absence of a transition at the edge of the violating symbol or the absence of a transition in the middle of the violating symbol.

[0138] Clause 11. The apparatus according to Clause 7 or 8, wherein the data transmission is encoded with a line code different from the preamble.

[0139] Clause 12. The apparatus according to any one of the preceding clauses, wherein the chip duration of the preamble, introductory code, or postamble is a multiple of the chip duration of the data transmission.

[0140] Clause 13. The apparatus according to any one of the preceding clauses, wherein the preamble, intermezzo, or postamble is received at a designated single frequency, and the data transmission is received at multiple frequencies.

[0141] Clause 14. A method for receiving a preamble, introductory code, or postamble for data transmission, the method comprising: receiving a designated symbol indicating the start of the preamble, introductory code, or postamble; receiving a first designated data pattern after the designated symbol, wherein the duration of the designated symbol is greater than the duration of the first designated data pattern; performing frequency synchronization based on the first designated data pattern; and identifying the chip duration of the data transmission based on the first designated data pattern or a second designated data pattern following the first designated data pattern.

[0142] Clause 15. The method according to Clause 14, wherein the first specified data pattern is fixed, and the second specified data pattern varies based on the chip duration of the data transmission, and the chip duration of the data transmission is identified as being based on the second specified data pattern.

[0143] Clause 16. The method according to Clause 14, wherein the first specified data pattern is a unique data pattern of the preamble, intermolecular, or postamble, and wherein the chip duration identifying the transmission of the data is based on a sequence of the first specified data pattern.

[0144] Clause 17. The method according to any one of Clauses 14 to 16, wherein the preamble, intermolecular, or postamble is repeated once or more for the transmission of the data.

[0145] Clause 18. The method according to any one of Clauses 14 to 17, wherein the preamble, introductory code, or postamble comprises a plurality of symbols encoded with line codes, and the preamble, introductory code, or postamble has a symbol rule violation of the line code in a violation symbol indicating the preamble, introductory code, or postamble.

[0146] Clause 19. The method according to Clause 18, wherein the data transmission is encoded with a line code different from the preamble.

[0147] Clause 20. The method according to any one of Clauses 14 to 19, wherein the chip duration of the preamble, introductory code, or postamble is a multiple of the chip duration of the data transmission.

[0148] Clause 21. An apparatus comprising components for performing the method according to any one of Clauses 14 to 20.

[0149] Clause 22. A non-transitory computer-readable medium storing computer-executable instructions that, when executed by a processor, cause the processor to perform a method according to any one of Clauses 14 to 20.

[0150] As used in this article, the phrase “at least one of” in a list of items refers to any combination of those items, including a single member. As an example, “at least one of a, b, or c” is intended to cover: a, b, c, ab, ac, bc, and abc.

[0151] The various exemplary logics, logic blocks, modules, circuits, and algorithmic processes described in conjunction with the specific implementations disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. The interchangeability of hardware and software has been broadly described in terms of functionality and illustrated in the aforementioned exemplary components, blocks, modules, circuits, and processes. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0152] Hardware and data processing means for implementing the various exemplary logic, logic blocks, modules, and circuits described herein can be implemented or executed using general-purpose single-chip or multi-chip processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. In some specific implementations, specific processes and methods can be performed by circuitry specific to a given function.

[0153] In one or more aspects, the described functionality may be implemented in hardware, digital electronic circuits, computer software, firmware, including the structures disclosed in this specification and their structural equivalents or any combination thereof. Specific implementations of the subject matter described in this specification may also be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a computer storage medium for execution by a data processing apparatus or for controlling the operation of the data processing apparatus.

[0154] If implemented in software, the functionality can be stored as one or more instructions or code on or transmitted through a computer-readable medium. The processes of the methods or algorithms disclosed herein can be implemented in a processor-executable software module that can reside on a computer-readable medium. Computer-readable media include both computer storage media and communication media, with communication media including any medium capable of transferring a computer program from one place to another. Storage media can be any available medium accessible to a computer. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and is accessible to a computer. Furthermore, any connection may be properly referred to as a computer-readable medium. As used herein, disks and optical discs include compact optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, where disks typically magnetically reproduce data, while optical discs optically reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operation of a method or algorithm may reside as a set of code and instructions or any combination of code and instructions on a machine-readable medium and a computer-readable medium that may be incorporated into a computer program product.

[0155] Various modifications to the specific embodiments described in this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other specific embodiments without departing from the spirit or scope of this disclosure. Therefore, the claims are not intended to be limited to the specific embodiments shown herein, but are to be accorded the broadest scope consistent with this disclosure, the principles disclosed herein, and the novel features.

[0156] Additionally, those skilled in the art will readily recognize that the terms “upper” and “lower” are sometimes used to facilitate the description of the drawings and to indicate relative positioning on a correctly oriented page corresponding to the orientation of the drawings, and may not reflect the correct orientation of any device as implemented.

[0157] Some features described in this specification in the context of a single embodiment may also be implemented in combination in that single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as operating in certain combinations and even originally claimed in this way, in some cases, one or more features from the claimed combination may be removed from that combination, and the claimed combination may involve sub-combinations or variations thereof.

[0158] Similarly, although operations are depicted in a specific order in the figures, this should not be construed as requiring such operations to be performed in the specific order shown or in sequential order, or to perform all illustrated operations to achieve the desired result. Furthermore, the figures may schematically depict one or more example processes in the form of flowcharts. However, other operations not depicted may be incorporated into the schematically illustrated example processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any of the illustrated operations. In some contexts, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be construed as requiring such separation in all embodiments, but rather should be understood as meaning that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired result.

Claims

1. An apparatus for receiving a preamble, intermezzo, or postamble for data transmission, the apparatus comprising: One or more memories, wherein the one or more memories store executable instructions; and One or more processors, said one or more processors coupled to said one or more memories and configured to execute said instructions to: Receive a designated symbol indicating the start of the preamble, intermezzo, or posttermezzo; A first specified data pattern is received after the specified symbol, wherein the duration of the specified symbol is greater than the duration of the first specified data pattern; Frequency synchronization is performed based on the first specified data pattern; as well as The chip duration of the data transmission is identified based on the first specified data pattern or a second specified data pattern following the first specified data pattern.

2. The apparatus of claim 1, wherein the first specified data pattern is fixed, and the second specified data pattern varies based on the chip duration of the data transmission, and the chip duration of the data transmission is identified as being based on the second specified data pattern.

3. The apparatus of claim 1, wherein the first specified data pattern is a unique data pattern of the preamble, intermezzo, or postamble, and wherein the chip duration identifying the data transmission is a sequence based on the first specified data pattern.

4. The apparatus of claim 3, wherein the sequence of the first specified data pattern indicates the relationship between the chip duration or data rate of the first specified data pattern and the chip duration of the data transmission.

5. The apparatus of claim 1, wherein the preamble, intermezzo, or postamble is repeated once or multiple times for the data transmission.

6. The apparatus of claim 1, wherein the designation symbol comprises a first designation symbol having a minimum length having a single output voltage and a second designation symbol having a fixed length having a single output voltage.

7. An apparatus for receiving a preamble, intermezzo, or postamble for data transmission, the apparatus comprising: One or more memories, wherein the one or more memories store executable instructions; and One or more processors, said one or more processors coupled to said one or more memories and configured to execute said instructions to: Receive a first specified data pattern comprising a plurality of symbols encoded with line codes, wherein the first specified data pattern has a symbol rule violation of the line code in a violation symbol indicating the preamble, introductory code, or postamble; Frequency synchronization is performed based on the first specified data pattern; as well as The chip duration of the data transmission is identified based on the first specified data pattern or a second specified data pattern following the first specified data pattern.

8. The apparatus of claim 7, wherein the line code is Manchester code, and the symbol rule violation includes the absence of a transition in the middle of the violation symbol, and the rule defines whether the transition occurs at a symbol edge between the violation symbol and a normal symbol or another violation symbol.

9. The apparatus of claim 7, wherein the line code is a PIE code, and the symbol rule violation includes a missing transition in the middle of the violation symbol, an inversion of the high and low output levels for the violation symbol, or a configured output level for the violation symbol.

10. The apparatus of claim 7, wherein the line code is Miller code, and the symbol rule violation includes a lack of transition at the edge of the violation symbol or a lack of transition in the middle of the violation symbol.

11. The apparatus of claim 7, wherein the data transmission is encoded with a line code different from the preamble.

12. The apparatus of claim 7, wherein the chip duration of the preamble, intermezcode, or postamble is a multiple of the chip duration of the data transmission.

13. The apparatus of claim 7, wherein the preamble, intermezzo, or postamble is received at a specified single frequency, and the data transmission is received at multiple frequencies.

14. A method for receiving a preamble, intermezzo, or postamble for data transmission, the method comprising: Receive a designated symbol indicating the start of the preamble, intermezzo, or posttermezzo; A first specified data pattern is received after the specified symbol, wherein the duration of the specified symbol is greater than the duration of the first specified data pattern; Frequency synchronization is performed based on the first specified data pattern; as well as The chip duration of the data transmission is identified based on the first specified data pattern or a second specified data pattern following the first specified data pattern.

15. The method of claim 14, wherein the first specified data pattern is fixed, and the second specified data pattern varies based on the chip duration of the data transmission, and the chip duration of the data transmission is identified as being based on the second specified data pattern.

16. The method of claim 14, wherein the first specified data pattern is a unique data pattern of the preamble, intermezzo, or postamble, and wherein the chip duration identifying the data transmission is a sequence based on the first specified data pattern.

17. The method of claim 14, wherein the preamble, intermezzo, or postamble is repeated once or more for the data transmission.

18. The method of claim 14, wherein the preamble, indicative, or postamble comprises a plurality of symbols encoded with line codes, and the preamble, indicative, or postamble has a symbol rule violation of the line code in a violation symbol indicating the preamble, indicative, or postamble.

19. The method of claim 18, wherein the data transmission is encoded with a line code different from the preamble.

20. The method of claim 14, wherein the chip duration of the preamble, intermezcode, or postamble is a multiple of the chip duration of the data transmission.

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