Package structure

Abstract

The utility model provides a packaging structure. The packaging structure comprises an adapter plate; the blocking structure is arranged on the adapter plate and defines a chip filling area, and the adapter plate is provided with an extension part extending out of the chip filling area in the direction parallel to the main surface of the adapter plate; the chip structure is arranged in the chip filling area and is electrically connected with the adapter plate; the bottom filling layer is limited in the chip filling area by the blocking structure and fills the space between the chip structure and the adapter plate; the packaging layer is arranged on the adapter plate and packages the blocking structure, the chip structure and the bottom filling layer, and the orthographic projection of the bottom filling edge of the bottom filling layer and the orthographic projection of the packaging edge of the packaging layer on the main surface of the adapter plate are staggered from each other. According to the utility model, layering among the bottom filling layer, the encapsulation layer and the adapter plate can be avoided, and the pore occurrence rate of the bottom filling layer can be reduced, so that the reliability of the encapsulation structure and the performance of the device are improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor packaging technology, and in particular to a packaging structure. Background Art

[0002] In semiconductor packaging technology, chips can be packaged to achieve chip protection, physical and / or electrical connection, etc. For example, multiple chips can be integrated together through packaging technology, and high-performance computing can be achieved. For example, in chip on wafer packaging, the chip structure is mounted on an adapter board through connectors such as solder balls, and a bottom fill layer can be set to fill the space between the chip structure and the adapter board. How to apply and control the formation area of ​​the bottom fill layer will affect the performance and reliability of the packaging structure to a certain extent, and is therefore an important research topic in the field of semiconductor packaging. Utility Model Content

[0003] According to at least one embodiment of the present disclosure, a packaging structure is provided, comprising: an adapter board; a blocking structure, which is arranged on the adapter board and defines a chip filling area, wherein the adapter board has an extension portion extending beyond the chip filling area in a direction parallel to the main surface of the adapter board; a chip structure, which is arranged in the chip filling area and electrically connected to the adapter board; a bottom filling layer, which is surrounded by the blocking structure and defined in the chip filling area, and fills the space between the chip structure and the adapter board; and an encapsulation layer, which is arranged on the adapter board and encapsulates the blocking structure, the chip structure and the bottom filling layer, wherein the bottom filling layer has a bottom filling edge, the encapsulation layer has an encapsulation edge, and the orthographic projections of the bottom filling edge and the encapsulation edge on the main surface of the adapter board are staggered from each other.

[0004] In the packaging structure provided according to at least one embodiment of the present disclosure, in a direction parallel to the main surface of the adapter board, a first distance between an edge of the chip structure and the blocking structure is smaller than a second distance between the edge of the chip structure and an edge of the encapsulation.

[0005] In the package structure provided according to at least one embodiment of the present disclosure, the bottom filling edge contacts the inner sidewall of the barrier structure.

[0006] In the packaging structure provided according to at least one embodiment of the present disclosure, the encapsulation layer has an encapsulation end close to the encapsulation edge, the blocking structure and the encapsulation end are located on the extension portion of the adapter board, and the outer wall of the blocking structure away from the bottom filling layer and the surface of the blocking structure away from the adapter board are covered by the encapsulation end.

[0007] In the packaging structure provided according to at least one embodiment of the present disclosure, the encapsulation edge is aligned with the side wall of the transfer board in a direction perpendicular to the main surface of the transfer board.

[0008] In the packaging structure provided according to at least one embodiment of the present disclosure, the bottom filling layer includes a main body portion and an overflow portion, the main body portion fills the space between the chip structure and the adapter board, the overflow portion extends beyond the edge of the chip structure in a direction parallel to the main surface of the adapter board and has a surface covered by the encapsulation layer, wherein the bottom filling edge is the surface of the overflow portion farthest from the chip structure in a direction parallel to the main surface of the adapter board.

[0009] In the packaging structure provided according to at least one embodiment of the present disclosure, a portion of the surface of the bottom filling layer contacts the encapsulation layer, and the orthographic projection of the contact interface between the bottom filling layer and the encapsulation layer on the main surface of the adapter board and the orthographic projection of the encapsulation edge on the main surface of the adapter board are staggered with each other.

[0010] In the packaging structure provided according to at least one embodiment of the present disclosure, the chip structure is electrically connected to the adapter board via a conductive connector, and at least a portion of the blocking structure is disposed in the same layer as a portion of the conductive connector and comprises the same material.

[0011] In the packaging structure provided according to at least one embodiment of the present disclosure, the barrier structure includes one or more barrier rings, and the chip filling area is defined by an inner sidewall of the barrier ring farthest from the chip structure among the one or more barrier rings.

[0012] In the packaging structure provided according to at least one embodiment of the present disclosure, each of the one or more barrier rings is a single-layer structure or a multi-layer stacked structure.

[0013] In the packaging structure provided according to at least one embodiment of the present disclosure, one or more blocking rings in the blocking structure each include a first blocking member and a second blocking member, the second blocking member is stacked on a side of the first blocking member away from the adapter plate, and the first blocking member and the second blocking member include the same or different materials.

[0014] In the packaging structure provided according to at least one embodiment of the present disclosure, one of the first barrier and the second barrier includes an insulating material, and the other of the first barrier and the second barrier includes a metal material; or both the first barrier and the second barrier include an insulating material; or both the first barrier and the second barrier include a metal material.

[0015] In the packaging structure provided according to at least one embodiment of the present disclosure, in a direction parallel to the main surface of the adapter board, the first blocking member has a first blocking width, and the second blocking member has a second blocking width, wherein the first blocking width is greater than the second blocking width; or the first blocking width is equal to the second blocking width, and the first blocking member and the blocking member have side walls aligned in a direction perpendicular to the main surface of the adapter board; or the first blocking width is smaller than the second blocking width, and the second blocking member covers the side walls of the first blocking member.

[0016] In the packaging structure provided according to at least one embodiment of the present disclosure, the blocking structure includes a plurality of blocking rings, and the chip filling area includes: a main body area, which is defined by the inner side wall of the blocking ring closest to the chip structure among the plurality of blocking rings, and the chip structure is arranged in the main body area; and a buffer area, which is defined by the side walls of adjacent blocking rings among the plurality of blocking rings facing each other.

[0017] In the packaging structure provided according to at least one embodiment of the present disclosure, the bottom filling layer is entirely located in the main body region; or the bottom filling layer includes a portion located in the main body region and also includes an extending portion extending into the buffer region.

[0018] The packaging structure provided according to at least one embodiment of the present disclosure further includes: a packaging substrate, which is arranged on a side of the adapter board away from the chip structure and is electrically connected to the adapter board.

[0019] The packaging structure provided according to at least one embodiment of the present disclosure further includes: a circuit board, which is arranged on a side of the packaging substrate away from the packaging substrate and is electrically connected to the packaging substrate.

[0020] In the packaging structure according to the embodiment of the present disclosure, by setting a blocking structure, the bottom filling layer is confined within the chip filling area defined by the blocking structure, which can prevent the bottom filling layer from spreading to the edge of the packaging structure. In this way, in the process of cutting the wafer-level structure to form the packaging structure in the packaging process, the cutting process will cut the encapsulation layer but will not cut the bottom filling layer, so that in the formed packaging structure, the encapsulation edge is aligned with the side wall of the adapter plate, while the bottom filling edge and the encapsulation edge are staggered from each other. Since the bottom filling layer will not be cut, the problem of delamination between the encapsulation layer and the bottom filling layer and between the bottom filling layer and the adapter plate caused by the cutting process can be avoided, and the incidence of pores in the bottom filling layer can be reduced, thereby improving the reliability of the packaging structure and the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0022] Figure 1A A schematic cross-sectional view showing a wafer structure; Figure 1B A schematic cross-sectional view of a packaging structure is shown.

[0023] Figure 2 A schematic cross-sectional view showing a package structure according to some embodiments of the present disclosure is shown.

[0024] Figure 3 A schematic top view of a packaging structure according to some embodiments of the present disclosure is shown.

[0025] Figure 4A and Figure 4B A schematic top view showing a packaging structure according to some other embodiments of the present disclosure; Figure 4C Schematic top views of interposers and blocking structures in packaging structures according to other embodiments of the present disclosure are shown.

[0026] FIG. 5A to FIG. 5D A schematic cross-sectional view showing an interposer and a barrier ring in a package structure according to some embodiments of the present disclosure.

[0027] FIG. 6A to FIG. 6D A schematic cross-sectional view showing an interposer and a barrier ring in a package structure according to some embodiments of the present disclosure.

[0028] Figures 7 to 13 Schematic cross-sectional views showing structures of various steps in a method for manufacturing a package structure according to some embodiments of the present disclosure.

[0029] Fig.14 and Fig.15 Schematic cross-sectional views of package structures according to still other embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0031] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0032] Unless otherwise defined, the features such as "parallel", "perpendicular" and "same" used in the embodiments of the present disclosure include the situations of "parallel", "perpendicular", "same" in a strict sense, as well as the situations of "approximately parallel", "approximately perpendicular", "approximately the same", etc., which contain certain errors. For example, the above-mentioned "approximately" may mean that the difference of the compared objects is within 10% or 5% of the average value of the compared objects. When the number of a component or element is not specifically indicated in the following of the embodiments of the present disclosure, it means that the component or element may be one or more, or may be understood as at least one. "At least one" refers to one or more, and "plurality" refers to at least two.

[0033] Figure 1A A schematic cross-sectional view showing a wafer structure, Figure 1B Shows a Figure 1A The schematic cross-sectional view of the package structure formed by cutting the wafer structure is shown.

[0034] refer to Figure 1A In some embodiments, the wafer structure 10 has a plurality of packaging regions R1 and a cutting region R2. For example, the plurality of packaging regions R1 may be arranged in an array and spaced apart from each other by the cutting region R2. A plurality of packaging structures 10a are respectively formed in the plurality of packaging regions R1. For example, the packaging structure 10a may include a plurality of chips 1, an adapter plate 2, a bottom filling layer 3, an encapsulation layer 4, and a conductive bump 5. A plurality of chips 1 are arranged side by side on one side of the adapter plate 2 and are electrically connected to the adapter plate 2. The bottom filling layer 3 fills the space between the chip 1 and the adapter plate 2 and extends beyond the edge of the chip in a direction parallel to the main surface of the adapter plate. For example, the bottom filling layer 3 may also cover part or all of the sidewalls of the chip 1. The encapsulation layer 4 is arranged on the adapter plate 2 and encapsulates the plurality of chips 1 and the bottom filling layer 3. There is a contact interface between the bottom filling layer 3 and the encapsulation layer 4. The conductive bump 5 is located on the side of the adapter plate 2 away from the chip 1 and is electrically connected to the adapter plate 2.

[0035] The adapter plate 2 extends continuously in multiple packaging areas R1 and cutting areas R2. The encapsulation layer 4 is located in multiple packaging areas R1 and cutting areas R2, and can also extend continuously in these areas. In some examples, the bottom filling layer 3 is located in each packaging area R1 and may also extend into the cutting area R2.

[0036] For example, there is an edge spacing Es between the edge of the chip 1 and the cutting area R2. When the edge spacing is insufficient, the bottom filling layer 3 may extend beyond the packaging area R1 and extend to the cutting area R2. Figure 1A As shown, in the cutting region R2, the underfill layer 3 and the encapsulation layer 4 overlap each other in a direction perpendicular to the main surface of the interposer.

[0037] refer to Figure 1A to Figure 1B In the packaging process, after the wafer structure 10 is formed, the wafer structure 10 is subjected to a cutting process to cut the plurality of packaging structures 10a apart and form a plurality of packaging structures 10a that are independent of each other. Figure 1B For example, the cutting process may be performed along the cutting area R2 using a cutting blade 9, wherein the material located in the cutting area R2 will be cut.

[0038] In this example, since the bottom filling layer 3 spreads to the cutting area R2 and overlaps with the encapsulation layer 4 in the cutting area R2, the cutting process will cut both the encapsulation layer 4 and the bottom filling layer 3. Figure 1B As shown, after the cutting process, the edge of the bottom filling layer 3 and the edge of the encapsulation layer 4 are roughly aligned in the direction perpendicular to the main surface of the adapter board, and are roughly aligned with the side wall of the adapter board 2. For example, the orthographic projections of the edge of the bottom filling layer 3 and the edge of the encapsulation layer 4 on the plane where the main surface of the adapter board is located overlap each other.

[0039] In some examples, the material of the bottom filling layer 3 and the material of the encapsulation layer 4 have different moduli (e.g., Young's modulus) and widely different thermal expansion coefficients. However, due to the difference in modulus and thermal expansion coefficient between the materials of the bottom filling layer 3 and the encapsulation layer 4, the cutting process easily leads to delamination between different materials, such as delamination at the contact interface between the bottom filling layer and the encapsulation layer and / or between the bottom filling layer and the adapter. For example, since the bottom filling layer and the encapsulation layer have different Young's moduli and widely different thermal expansion coefficients, large internal stress remains between the bottom filling layer, the encapsulation layer, and the adapter before cutting, and the internal stress is easily released during the cutting process, which may lead to delamination, cracking, and other problems between the bottom filling layer and the encapsulation layer and / or between the bottom filling layer and the adapter, thereby reducing the reliability of the packaging structure.

[0040] In some examples, the risk of material delamination caused by the bottom filling layer overflowing to the edge of the packaging area or into the cutting area can be reduced by widening the edge spacing Es between the chip and the cutting area; for example, the edge spacing Es needs to be greater than 1 millimeter (mm) to reduce the above manufacturing risks. However, increasing the edge spacing will also increase the overall size of the packaging structure. On the other hand, the bottom filling layer can be formed by applying the bottom filling material through a dispensing process and then curing the bottom filling material; the bottom filling material has fluidity, and the higher its fluidity, the farther the bottom filling material may spread (i.e., the overflow distance). In order to reduce the overflow distance of the bottom filling layer and prevent it from extending into the cutting area, it may not be possible to use a high-fluidity bottom filling material, and it may be necessary to use a bottom filling material with lower fluidity (e.g., higher viscosity), but this may easily lead to the formation of air gaps in the bottom filling layer formed.

[0041] In response to the above-mentioned problems, an embodiment of the present disclosure provides a packaging structure, which can avoid delamination between the bottom filling layer and the encapsulation layer and between the bottom filling layer and the adapter board, and can help reduce the incidence of pores in the bottom filling layer, thereby improving the reliability of the packaging structure and device performance; moreover, it can also help reduce the edge spacing between the chip structure and the edge of the package, thereby reducing the overall size of the packaging structure.

[0042] For example, the packaging structure of the embodiment of the present disclosure includes: an adapter board; a blocking structure, which is arranged on the adapter board and defines a chip filling area, wherein the adapter board has an extension portion extending beyond the chip filling area in a direction parallel to the main surface of the adapter board; a chip structure, which is arranged in the chip filling area and electrically connected to the adapter board; a bottom filling layer, which is surrounded by the blocking structure and defined in the chip filling area, and fills the space between the chip structure and the adapter board; and an encapsulation layer, which is arranged on the adapter board and encapsulates the blocking structure, the chip structure and the bottom filling layer, wherein the bottom filling layer has a bottom filling edge, the encapsulation layer has an encapsulation edge, and the orthographic projections of the bottom filling edge and the encapsulation edge on the main surface of the adapter board are staggered from each other.

[0043] In the embodiment of the present disclosure, by providing a blocking structure on the adapter plate and limiting the bottom filling layer within the chip filling area defined by the blocking structure, the bottom filling layer can be prevented from spreading to the edge of the packaging structure, so that the bottom filling edge and the encapsulation edge are staggered. In this way, in the process of cutting the wafer-level structure to form the packaging structure in the packaging process, the cutting process will cut the encapsulation layer, but the bottom filling layer will not be cut, so that in the formed packaging structure, the encapsulation edge is aligned with the side wall of the adapter plate, and the bottom filling edge and the encapsulation edge are staggered. Since the bottom filling layer will not be cut, there will be no delamination problem between the encapsulation layer and the bottom filling layer and between the bottom filling layer and the adapter plate due to the cutting process, thereby improving the reliability of the packaging structure and the device performance. Moreover, since the blocking structure is provided to limit the extension area of ​​the bottom filling layer, a bottom filling material with high fluidity (for example, lower viscosity) can also be selected in the packaging process to form the bottom filling layer, so that the pore incidence rate of the bottom filling layer can be improved, and then it can also be beneficial to improve the reliability of the packaging structure and the device performance. On the other hand, since a blocking structure is provided to prevent the bottom filling layer from spreading to the edge of the package, the edge spacing between the chip structure and the edge of the package does not need to be set too large to prevent the spreading of the bottom filling layer. For example, the chip structure and the edge of the package can be set to have a smaller edge spacing, which is beneficial to reducing the overall size of the package structure.

[0044] Figure 2 A schematic cross-sectional view showing a package structure according to some embodiments of the present disclosure; Figure 3 A schematic top view of a packaging structure according to some embodiments of the present disclosure is shown, and Figure 2 For example, along Figure 3 A cross-sectional view taken along line II' in FIG.

[0045] refer to Figure 2 and Figure 3 In some embodiments, the package structure 500 includes an interposer 100, a barrier structure 101, a chip structure 80, a bottom filling layer 105, and an encapsulation layer 106. The barrier structure 101 is disposed on the interposer 100 and defines a chip filling region CR. For example, the barrier structure 101 has an inner sidewall S1 and an outer sidewall S2 that are opposite to each other in a direction parallel to a main surface of the interposer (for example, a horizontal direction including the first direction D1), and the chip filling region CR is defined by the inner sidewall S1 of the barrier structure 101.

[0046] In some embodiments, the adapter board 100 has an extension portion 100e, and the extension portion 100e extends beyond the chip filling area in a direction parallel to the main surface of the adapter board 100. In other words, the area of ​​the chip filling area CR is smaller than the area of ​​the adapter board 100, and the area of ​​each component mentioned above refers to its area in a direction parallel to the main surface of the adapter board. In some embodiments, the extension portion 100e of the adapter board 100 is an edge portion of the adapter board 100 close to its side wall.

[0047] In some embodiments, the chip structure 80 is disposed on the adapter board 100 in the chip filling region CR and is electrically connected to the adapter board 100. For example, the chip structure 80 can be electrically connected to the adapter board 100 through the conductive connector 104. The chip structure 80 may include one or more chips 80a. The bottom filling layer 105 is disposed on the adapter board 100, surrounded by the blocking structure 101 and confined in the chip filling region CR. The bottom filling layer 105 fills the space between the chip structure 80 and the adapter board 100, and surrounds and protects the conductive connector 104 in a direction parallel to the main surface of the adapter board 100.

[0048] Continue to refer Figure 2 and Figure 3 , the encapsulation layer 106 is disposed on the transfer board 100, and encapsulates the barrier structure 101, the chip structure 80, and the bottom filling layer 105. In some embodiments, the bottom filling layer 105 has a bottom filling edge E1, the encapsulation layer 106 has an encapsulation edge E2, and the orthographic projections of the bottom filling edge E1 and the encapsulation edge E2 on the main surface of the transfer board 100 or on a reference plane parallel to the main surface of the transfer board are staggered from each other, that is, spaced apart. In other words, the bottom filling edge E1 and the encapsulation edge E2 are not aligned in a direction perpendicular to the main surface of the transfer board (e.g., the second direction D2), but are spaced apart from each other in a direction parallel to the main surface of the transfer board (e.g., a horizontal direction including the first direction D1).

[0049] In some embodiments, in a direction parallel to the main surface of the transfer board, the chip filling region CR exceeds the edge of the chip structure 80; the bottom filling layer 105 is in the chip filling region CR and can extend beyond the edge of the chip structure 80. The edge of the chip filling region CR is roughly the position of the inner sidewall S1 of the barrier structure 101; that is, the bottom filling layer 105 can extend as far as the inner sidewall S1 of the barrier structure 101 in the horizontal direction and in the direction away from the chip structure.

[0050] In some embodiments, the bottom filling layer 105 may cover part or all of the sidewalls of the chip structure 80. The encapsulation layer 106 may cover the sidewalls of the barrier structure 101 and the surface thereof away from the interposer 100, part of the surface of the bottom filling layer 105, and the sidewalls of the chip structure 80. In some embodiments, the surface of the encapsulation layer 106 away from the interposer 100 may be substantially flush with the surface of the chip structure 80 away from the interposer 100 in a direction parallel to the main surface of the interposer. In other embodiments, the encapsulation layer 106 may also cover the surface of the chip structure 80 away from the interposer 100.

[0051] In some embodiments, in a direction parallel to the main surface of the transfer board (for example, the first direction D1), there is a first distance d1 between the edge of the chip structure 80 and the blocking structure 101, and there is a second distance d2 between the edge of the chip structure 80 and the encapsulation edge E2 of the encapsulation layer 106, and the first distance d1 is less than the second distance d2. It should be understood that the first distance between the edge of the chip structure and the blocking structure is the distance between the edge of the chip structure and the inner sidewall of the blocking structure.

[0052] In some embodiments, the bottom filling layer 105 is located in the chip filling region CR, and may or may not extend to the edge of the chip filling region. That is, in a direction parallel to the main surface of the interposer, the distance between the edge of the chip structure 80 and the bottom filling edge E1 may be less than or substantially equal to the first distance d1 between the edge of the chip structure 80 and the inner sidewall of the barrier structure 101, and less than the second distance d2 between the edge of the chip structure 80 and the encapsulation edge E2. That is, the bottom filling layer 105 is confined within the chip filling region CR surrounded by the barrier structure 101, and does not spread to areas outside the chip filling region CR.

[0053] In a direction parallel to the main surface of the interposer 100 (e.g., a horizontal direction including the first direction D1), the bottom filling edge E1 is located on a side of the blocking structure 101 close to the chip structure 80, and the encapsulation edge E2 is located on a side of the blocking structure 101 away from the chip structure 80. The bottom filling edge E1 refers to the end point of the bottom filling layer 105 away from the chip structure 80 in the direction parallel to the main surface of the interposer.

[0054] In some embodiments, the underfill layer 105 may extend to the edge of the chip filling region CR, and the underfill edge E1 thereof may contact the inner sidewall S1 of the barrier structure 101 defining the chip filling region CR.

[0055] In some embodiments, the encapsulation layer has an encapsulation end portion close to the encapsulation edge, the blocking structure and the encapsulation end portion are located on the extension portion of the adapter plate, and the outer wall of the blocking structure away from the bottom filling layer and the surface of the blocking structure away from the adapter plate are covered by the encapsulation end portion.

[0056] For example, the encapsulation layer 106 has an encapsulation end 106e, the encapsulation end 106e and the blocking structure 101 are located on the extension 100e of the interposer 100, and the encapsulation end 106e may cover the outer sidewall S2 of the blocking structure 101 and the surface thereof on the side away from the interposer 100. The blocking structure 101 is located between the bottom filling layer 105 and the encapsulation end 106e in a direction parallel to the main surface of the interposer 100 (for example, a horizontal direction including the first direction D1), and may be located between the interposer 100 and the encapsulation end 106e in a direction perpendicular to the main surface of the interposer 100 (for example, the second direction D2).

[0057] The sidewall of the encapsulation end 106e is the encapsulation edge E2 of the encapsulation layer 106. In some embodiments, the encapsulation edge E2 may be aligned with the sidewall of the transfer board 100, for example, approximately aligned in a direction perpendicular to the main surface of the transfer board. For example, the edge of the package structure 500 includes the encapsulation edge E2 and the sidewall of the transfer board 100.

[0058] In some embodiments, the bottom filling layer includes a main portion and an overflow portion, the main portion filling the space between the chip structure and the adapter board, the overflow portion extending beyond the edge of the chip structure in a direction parallel to the main surface of the adapter board and having a surface covered by the encapsulation layer, wherein the bottom filling edge is the surface of the overflow portion farthest from the chip structure in a direction parallel to the main surface of the adapter board.

[0059] Continue to refer Figure 2 and Figure 3 For example, the bottom filling layer 105 includes a main body 105a and an overflow portion 105b. The main body 105a is located in the area where the chip structure 80 is located, fills the space between the chip structure 80 and the adapter board 100, and can be filled in the gap between adjacent chips 80a in the chip structure 80, covering the side walls of the adjacent chips facing each other. The overflow portion 105b extends beyond the edge of the chip structure 80 in a direction parallel to the main surface of the adapter board, and can cover the side wall surface of the chip structure 80 located at the edge. The bottom filling edge E1 includes the edge of the overflow portion 105b that is farthest from the chip structure 80 in each direction parallel to the main surface of the adapter board, for example, it can be the surface of the overflow portion 105b that contacts the blocking structure 101.

[0060] In some embodiments, a portion of the surface of the bottom filling layer contacts the encapsulation layer, and the orthographic projection of the contact interface between the bottom filling layer and the encapsulation layer on the main surface of the adapter plate is offset from the orthographic projection of the encapsulation edge on the main surface of the adapter plate.

[0061] For example, a portion of the surface of the overflow portion 105b may be covered by the encapsulation layer 106 and contact the encapsulation layer 106. In some embodiments, the bottom filling edge E1 of the overflow portion 105b may contact the barrier structure 101, but not contact the encapsulation layer 106. The contact interface between the bottom filling layer 105 and the encapsulation layer 106 may be or include the contact interface between the portion of the surface of the overflow portion 105b and the encapsulation layer 106. For example, the orthographic projection of the contact interface between the bottom filling layer 105 and the encapsulation layer 106 on the main surface of the transfer board 100 and the orthographic projection of the encapsulation edge E2 on the main surface of the transfer board 100 are staggered from each other, that is, spaced apart. For example, the orthographic projection of the contact interface between the bottom filling layer 105 and the encapsulation layer 106 on the main surface of the transfer board 100 may be located within the orthographic projection of the chip filling region CR on the main surface of the transfer board 100. That is, the contact interface between the bottom filling layer and the encapsulation layer does not extend to the edge of the packaging structure.

[0062] In some embodiments, in a direction perpendicular to the main surface of the adapter board, the height of the bottom filling edge E1 of the bottom filling layer 105 is less than or equal to the height of the blocking structure 101, so that the bottom filling layer 105 can be blocked and confined in the chip filling area CR by the blocking structure 101, and will not spread across the blocking structure 101 to the area outside the chip filling area, that is, it will not spread to the edge of the adapter board.

[0063] For example, the height of the overflow portion 105 b gradually decreases as the overflow portion 105 b moves away from the chip structure 80 in the horizontal direction, and has a minimum height value at the bottom filling edge E1 , and the minimum height value is less than or equal to the height of the blocking structure 101 .

[0064] In some embodiments, the blocking structure 101 may include insulating materials and / or conductive materials such as metals; for example, the blocking structure 101 may include at least one of insulating materials such as photosensitive polyimide (PSPI) and polybenzoxazole (PBO), and metal materials such as copper. When the blocking structure 101 includes a metal material, the blocking structure 101 is electrically floating, that is, it is not electrically connected to the conductive components in the adapter board.

[0065] In some embodiments, the chip structure is electrically connected to the adapter plate via a conductive connector, and at least a portion of the blocking structure is disposed in the same layer as a portion of the conductive connector and comprises the same material.

[0066] refer to Figure 2 In some embodiments, the chip structure 80 is electrically connected to the adapter board 100 via a conductive connector 104, and the conductive connector 104 may be or include a conductive bump such as a micro-bump. Figure 2 As shown in the enlarged view of , the conductive connector 104 may include a first conductive connector 102, a second conductive connector 103 and a third conductive connector 81 electrically connected to each other. The first conductive connector 102 is disposed on the adapter board 100 and is electrically connected to the conductive circuit in the adapter board 100. The third conductive connector 81 is disposed on the chip structure 80, and may be, for example, an input and output contact of each chip. The second conductive connector 103 is located between the first conductive connector 102 and the third conductive connector 81. In some embodiments, the first conductive connector 102 and the third conductive connector 81 may each include a conductive material such as metal (e.g., copper), and the second conductive connector 103 may include a conductive material such as solder.

[0067] In some embodiments, at least a portion (ie, part or all) of the blocking structure 101 may be disposed at the same layer as the first conductive connection 102 and include the same material, for example, the same metal material (eg, copper).

[0068] In some embodiments, the package structure 500 further includes a conductive terminal 120, which is disposed on a side of the interposer 100 away from the chip structure 80, is electrically connected to the interposer 100, and can be electrically connected to the chip structure 80 through the interposer 100. For example, the conductive terminal 120 may include a solder ball, such as a controlled collapsed chip connection (C4) bump. The conductive terminal 120 can be used to further electrically connect the package structure 500 to other package components, such as a package substrate.

[0069] In some embodiments, from a plan view, the blocking structure is annular, for example, a closed ring, and encloses and defines the chip filling area. That is, the blocking structure surrounds the chip filling area, and the chip structure and the bottom filling layer are located in the area surrounded by the blocking structure. In this article, the ring shape can be any type of ring shape such as a square ring, a circular ring, etc. In some embodiments, the outline of the blocking structure can have a similar shape to the outline of the adapter plate. For example, if the adapter plate is square, the blocking structure can have a square ring shape, but the present disclosure is not limited to this.

[0070] In some embodiments, the blocking structure includes one or more blocking rings, and the chip filling area is defined by the inner sidewall of the blocking ring farthest from the chip structure among the one or more blocking rings. In embodiments where the blocking structure includes multiple blocking rings, the multiple blocking rings are arranged side by side in a direction parallel to the main surface of the adapter plate (e.g., horizontal direction), and each blocking ring may be annular, such as a closed ring.

[0071] For example, Figure 3 As shown, the blocking structure 101 includes a blocking ring, which may be in the shape of a closed ring to surround the chip filling area. Figure 4A As shown, the blocking structure 101 includes a plurality of blocking rings, for example, a first blocking ring 101a and a second blocking ring 101b arranged side by side and spaced apart in a horizontal direction. Figure 4B As shown, the blocking structure 101 includes a plurality of blocking rings, for example, a first blocking ring 101a, a second blocking ring 101b and a third blocking ring 101c arranged side by side and spaced apart in a horizontal direction. It should be understood that Figure 4A and Figure 4B The number of the plurality of barrier rings shown is for illustration only and the present disclosure is not limited thereto.

[0072] FIG. 5A to FIG. 5D Schematic cross-sectional views showing a blocking ring located on an adapter plate according to some embodiments of the present disclosure, the cross-sectional views are, for example, taken along a line parallel to a major surface of the adapter plate. Figure 3 , Figure 4A and Figure 4B A cross-sectional view of any of the barrier rings shown.

[0073] In some embodiments, each of the one or more blocking rings is a single-layer structure or a multi-layer stacked structure. In some embodiments, each of the one or more blocking rings in the blocking structure includes a first blocking member and a second blocking member, the second blocking member is stacked and arranged on a side of the first blocking member away from the adapter plate, and the first blocking member and the second blocking member include the same or different materials. For example, the first blocking member and the second blocking member may both be ring-shaped.

[0074] For example, Figure 5A As shown, the blocking ring (eg, Figure 3 The barrier ring shown or Figure 4A and Figure 4B The blocking ring 101a, 101b or 101c shown in the figure may be a single-layer structure and include a first blocking member L1. FIG. 5B to FIG. 5DAs shown, the blocking ring of the blocking structure 101 may be a multi-layer stacked structure, for example, it may include a first blocking member L1 and a second blocking member L2, and the second blocking member L2 is stacked and arranged on a side of the first blocking member L1 away from the adapter plate 100. For example, the first blocking member L1 and the second blocking member L2 may include the same or different materials.

[0075] In some embodiments, the first barrier and the second barrier may each include an insulating material or a conductive material. The insulating material may include, for example, an organic insulating material such as PSPI and PBO, and the conductive material may include, for example, a metal material such as copper.

[0076] In some embodiments, one of the first barrier and the second barrier comprises an insulating material, and the other of the first barrier and the second barrier comprises a metal material; or both the first barrier and the second barrier comprise an insulating material; or both the first barrier and the second barrier comprise a metal material.

[0077] For example, the first blocking member L1 includes a metal material, and the second blocking member L2 includes an insulating material or a metal material; in this example, at least a portion of the blocking structure (eg, the first blocking member L1) may be Figure 2 The conductive connection 104 shown as a part (eg, the first conductive connection 102) is disposed in the same layer and includes the same material. For example, in other examples, the first barrier L1 includes an insulating material, and the second barrier L2 includes an insulating material or a metal material.

[0078] In some embodiments, in a direction parallel to the main surface of the adapter plate, the first blocking member has a first blocking width and the second blocking member has a second blocking width, wherein the first blocking width is greater than the second blocking width; or the first blocking width is equal to the second blocking width, and the first blocking member and the blocking member have side walls aligned in a direction perpendicular to the main surface of the adapter plate; or the first blocking width is smaller than the second blocking width, and the second blocking member covers the side walls of the first blocking member.

[0079] For example, refer to Figure 5A When the blocking ring of the blocking structure 101 is a single-layer structure, the first blocking member L1 of the blocking structure 101 can be set to have a suitable width according to product design and requirements. FIG. 5B to FIG. 5DAs shown, when the blocking ring of the blocking structure 101 includes a multi-layer stacked structure, different blocking members may have the same or different blocking widths; for example, the first blocking member L1 has a first blocking width w1, and the second blocking member L2 has a second blocking width w2, and the first blocking width w1 and the second blocking width w2 may be the same or different. In this article, the blocking width of a blocking member refers to the width of its blocking material in a direction parallel to the main surface of the adapter plate.

[0080] For example, Figure 5B As shown, the first blocking width w1 of the first blocking member L1 is greater than the second blocking width w2 of the second blocking member L2. Figure 4C Schematic illustration Figure 5B Schematic plan view of the first blocking member and the second blocking member shown. Figure 4C and Figure 5B As shown, the orthographic projection of the second blocking member L2 on the adapter plate 100 may be located within the orthographic projection of the first blocking member L1 on the adapter plate 100. The first blocking member L1 extends beyond the edge of the second blocking member L2 in a direction parallel to the main surface of the adapter plate.

[0081] For example, Figure 5C As shown, the first blocking width w1 of the first blocking member L1 may be substantially equal to the second blocking width w2 of the second blocking member L2. For example, the sidewall of the first blocking member L1 may be substantially aligned with the sidewall of the second blocking member L2 in a direction perpendicular to the main surface of the adapter plate 100.

[0082] For example, Figure 5D As shown, the first blocking width w1 of the first blocking member L1 may be smaller than the second blocking width w2 of the second blocking member L2. For example, the second blocking member L2 extends beyond the edge of the first blocking member L1 in a direction parallel to the main surface of the adapter plate, and may extend to cover the side wall of the first blocking member L1. For example, the orthographic projection of the first blocking member L1 on the main surface of the adapter plate may be located within the orthographic projection of the second blocking member L2 on the main surface of the adapter plate.

[0083] FIG. 5B to FIG. 5D The blocking structure is schematically shown to include a two-layer stacked structure. In other examples, the blocking structure may include a stacked structure formed by stacking more layers (e.g., 3 layers, 4 layers, etc.) of blocking members. The number of layers of blocking members included in the blocking structure may be determined according to relevant process parameters and the required overall height of the blocking structure, and may be set and adjusted based on product design and requirements.

[0084] In some embodiments, along Figure 3 A cross-sectional view of the barrier structure taken along line II-II' may have FIG. 5A to FIG. 5DIt should be understood that in the example where the blocking structure includes a single blocking ring, the chip structure and the bottom filling layer are both located in the area surrounded by the single blocking ring, and the bottom filling layer is confined within the chip filling area defined by the single blocking ring, and does not extend to the side of the single blocking ring away from the chip structure.

[0085] Fig. 6A and Figure 6B Schematically showing the Figure 4A Schematic cross-sectional view of the adapter plate and the blocking structure taken along line II-II'. Figure 6C and Fig.6D Schematically showing the Figure 4B Schematic cross-sectional view of the adapter plate and the blocking structure taken along line II-II'.

[0086] Fig. 6A and Figure 6C Schematically showing an example in which a plurality of barrier rings in the barrier structure are each a single-layer structure; Figure 6B and Fig.6D The schematic diagram shows an example in which each of the plurality of barrier rings in the barrier structure is a multi-layer stacked structure. Figure 6B and Fig.6D The blocking ring is Figure 5B The stacked structure shown is an example of a first blocking member and a second blocking member; it should be understood that in other examples, Figure 6B and Fig.6D Each barrier ring in may also have Figure 5C or Figure 5D The stacking structure shown.

[0087] In some embodiments, the blocking structure includes a plurality of blocking rings, and the chip filling area includes a main area and a buffer area; the main area is defined by an inner side wall of a blocking ring among the plurality of blocking rings that is closest to the chip structure, and the chip structure is disposed in the main area; the buffer area is defined by side walls of adjacent blocking rings among the plurality of blocking rings that face each other.

[0088] refer to Figure 4A , Figure 4B and FIG. 6A to FIG. 6D For example, the blocking structure 101 includes a plurality of blocking rings. The chip filling region CR may include a main region CR1 and one or more buffer regions CR2. The main region CR1 is defined by the inner sidewall of the blocking ring (e.g., the first blocking ring 101a) closest to the chip structure 80 among the plurality of blocking rings, and the chip structure 80 is disposed in the main region CR1. The outermost edge of the chip filling region CR is defined by the inner sidewall of the blocking ring (e.g., the first blocking ring 101a) farthest from the chip structure 80 among the plurality of blocking rings. Fig. 6A and Figure 6B The second blocking ring 101b shown, Figure 6C and Fig.6DThe third barrier ring 101c is shown as defining.

[0089] The buffer zone CR2 is defined by the side walls of adjacent barrier rings facing each other in the plurality of barrier rings. The number of buffer zones in the barrier structure is one less than the number of barrier rings. Figure 4A , Fig. 6A and Figure 6B In the example shown, the blocking structure 101 includes a first blocking ring 101a and a second blocking ring 101b, and the chip filling region CR includes a main region CR1 and a buffer region CR2; the buffer region CR2 is defined by the side walls of the first blocking ring 101a and the second blocking ring 101b facing each other. Figure 4B , Figure 6C and Fig.6D In the example shown, the blocking structure 101 includes a first blocking ring 101a, a second blocking ring 101b and a third blocking ring 101c, and the chip filling region CR includes a main region CR1 and two buffer regions CR2, one of the two buffer regions CR2 being defined by side walls of the first blocking ring 101a and the second blocking ring 101b facing each other, and the other of the two buffer regions CR2 being defined by side walls of the second blocking ring 101b and the third blocking ring 101c facing each other.

[0090] In some embodiments, the bottom filling layer is entirely located in the main area of ​​the chip filling area; or, the bottom filling layer includes a portion located in the main area of ​​the chip filling area and also includes an extending portion extending into the buffer area.

[0091] refer to Figure 4A , Fig. 6A and Figure 6B In some examples, the bottom filling layer may be located in the main body region CR1 of the chip filling region CR without extending into the buffer region CR2. In other examples, the main body of the bottom filling layer is located in the main body region CR1, and the bottom filling layer may also cross the first barrier ring 101a and extend into the buffer region CR2.

[0092] refer to Figure 4B , Figure 6C and Fig.6DIn some examples, the bottom filling layer may be located in the main body region CR1 of the chip filling region CR without extending into the buffer region CR2. In other examples, the main body of the bottom filling layer is located in the main body region CR1, and the bottom filling layer may also span the first barrier ring 101a and extend into the buffer region CR2 between the first barrier ring 101a and the second barrier ring 101b; or, the bottom filling layer may also span the second barrier ring 101b and extend into the buffer region CR2 between the second barrier ring 101b and the third barrier ring 101c. In the example where the chip filling region includes a plurality of buffer regions, there may be no bottom filling layer in any of the plurality of buffer regions, or there may be a bottom filling layer in one or more of the plurality of buffer regions.

[0093] It should be understood that in various examples, the bottom filling layer will not cross the barrier ring farthest from the chip structure and extend to the side of the barrier structure farthest from the chip structure. That is, the bottom filling layer is limited by the barrier structure within the chip filling area and will not extend to the area outside the chip filling area.

[0094] In some embodiments, the blocking ring is configured to include a stacked structure of a first blocking member and a second blocking member to increase the overall height of the blocking ring, thereby increasing the vertical limit height of the end of the bottom filling layer, that is, increasing the amount of the bottom filling layer that can be accommodated in the chip filling area, thereby being more conducive to limiting the bottom filling layer in the chip filling area and preventing the bottom filling layer from spreading to areas outside the chip filling area. The limit height of the end of the bottom filling layer refers to the maximum height that the end will not cross the blocking ring.

[0095] In some embodiments, Figure 6B and Fig.6D As shown, by setting the blocking width of the first blocking member to be larger than the blocking width of the second blocking member, the height of the blocking ring can be increased to increase the restricted height of the end of the bottom filling layer in the vertical direction, while increasing the area where the bottom filling layer can extend in the horizontal direction, thereby further increasing the amount of the bottom filling layer that can be accommodated in the chip filling area. This is conducive to limiting the bottom filling layer in the chip filling area and preventing it from spreading to areas outside the chip filling area.

[0096] In some embodiments, the blocking structure is configured to have a plurality of blocking rings, which can ensure that the bottom filling layer does not extend to the side of the blocking structure away from the chip structure. For example, even if the bottom filling layer crosses a blocking ring closest to the chip structure among the plurality of blocking rings, it can be blocked in the buffer zone by the other blocking rings and will not spread to the area outside the chip filling area.

[0097] Figures 7 to 13 A schematic cross-sectional view showing the structure of each step in the method for manufacturing a package structure according to some embodiments of the present disclosure, wherein Figures 7 to 12The process is a wafer level process, and the structure in these steps can be called a wafer level structure. For example, the wafer level structure can include multiple packaging areas R1 and cutting areas R2. Multiple packaging areas R1 are arranged side by side, for example, can be arranged in an array, and are separated from each other by the cutting area R2.

[0098] refer to Figure 7 In some embodiments, a carrier 20 is provided. The carrier 20 may be a glass carrier or the like that can provide support for a structure subsequently placed thereon and will be removed in a subsequent process, so it may also be referred to as a temporary carrier.

[0099] An interposer 100 is provided and attached to a carrier 20. For example, the interposer 100 may be mounted on the carrier 60 via an attachment layer 21. The attachment layer 21 may be or include a temporary bonding and debonding (TBDB) layer, and may be used to bond the interposer 100 to the carrier 20 in this step, and may be used to detach the interposer 100 and the structure thereon from the carrier 20 in a subsequent step.

[0100] In some embodiments, the adapter board 100 may be a silicon-based adapter board, and may include a substrate, a substrate through-hole and an interconnection structure; the substrate may be a semiconductor substrate, for example, a silicon substrate; the interconnection structure is located on one side of the substrate (for example, a side away from the carrier 20), and may include an inorganic dielectric structure and a conductive structure embedded in the inorganic dielectric structure (for example, including conductive traces and / or conductive through-holes, etc.); the substrate through-hole is embedded in the substrate and electrically connected to the interconnection structure; the interconnection structure is used to provide electrical connection between multiple chips, and the substrate through-hole is used to provide electrical connection between multiple chips and the interconnection structure and the conductive terminal.

[0101] In some embodiments, the adapter board 100 may be or include a redistribution structure, and may include an organic dielectric structure and a redistribution layer (RDL) embedded in the organic dielectric structure, and the redistribution layer is used to provide electrical connections between multiple chips and between multiple chips and conductive terminals. In some embodiments, the adapter board 100 may include a redistribution structure and a bridge chip, and the bridge chip may be embedded in the organic dielectric structure of the redistribution structure and is used to provide electrical connections between multiple chips in the chip structure; the redistribution layer is used to provide electrical connections between multiple chips and conductive terminals, or it can also be used to provide electrical connections between multiple chips.

[0102] refer to Figure 7 and Fig. 8AIn some embodiments, a barrier material layer 101' is formed on the transfer board 100, and then a patterning process is performed on the barrier material layer 101' to form a barrier structure 101 in each packaging area R1. For example, the barrier structure 101 may be disposed at a position close to the edge of each packaging area and at a non-zero distance from the cutting area R2 in the horizontal direction. That is, the barrier structure 101 is not disposed in the cutting area, and there may be a gap between the barrier structure 101 and the cutting area in the horizontal direction.

[0103] In some embodiments, the barrier material layer 101' may include an insulating material, for example, an organic insulating material such as PSPI, PBO, etc., and may be formed by a coating process; or, the barrier material layer 101' may include a conductive material, for example, a metal material such as copper, and may be formed by a plating process such as electroplating.

[0104] In some embodiments, the patterning process performed on the blocking material layer 101' may include a photolithography process. For example, the blocking material layer 101' includes PSPI, and the PSPI may be patterned by a photolithography process including exposure and development, and the PSPI may be cured by a baking process. In some embodiments, the patterning process performed on the blocking material layer 101' may include a photolithography and an etching process, for example, a patterned mask layer is formed on the blocking material layer 101' by a photolithography process, and then an etching process is performed on the blocking material layer 101' using the patterned mask layer as an etching mask to form a patterned blocking structure 101.

[0105] The blocking structure 101 may include one or more blocking rings, and a single blocking ring is used as an example. Figure 5A The blocking structure 101 may be a single-layer structure as shown, and may be formed by a single patterning process; in other embodiments, the blocking structure 101 may be a multi-layer stacked structure (eg, FIG. 5B to FIG. 5D The stacked structure shown in FIG. 1 may be repeated through multiple patterning processes, for example Figure 7 and Fig. 8A The process shown is used to form the desired stacking structure.

[0106] refer to Figure 8B In some embodiments, in each packaging region R1, a plurality of first conductive connectors 102 are formed on the transfer board 100; the plurality of first conductive connectors 102 include conductive materials, such as metal materials such as copper. For example, a conductive material layer may be formed by a plating process such as electroplating, and then the conductive material layer may be patterned by a patterning process including etching to form the plurality of first conductive connectors 102.

[0107] In some embodiments, at least a portion of the plurality of first conductive connectors 102 and the blocking structure 101 include the same material, for example, they may all include metal materials such as copper, and may be formed simultaneously by the same patterning process. For example, the conductive material layer is patterned to simultaneously form at least a portion of the first conductive connector 102 and the blocking structure 101. In some examples, the blocking structure 101 is a single-layer structure, and the blocking structure 101 (for example, its first blocking member) and the first conductive connector 102 are formed by the same patterning process; in a direction perpendicular to the main surface of the transfer board, the height of the blocking structure 101 may be substantially the same as the height of the first conductive connector 102. In other examples, the blocking structure 101 is a multi-layer stacked structure (for example, including a first blocking member and a second blocking member stacked), then one of the plurality of blocking members in the blocking structure 101 may be formed by the same patterning process as the first conductive connector 102; in this example, the overall height of the blocking structure 101 may be greater than the height of the first conductive connector 102.

[0108] In some embodiments, the first conductive connection 102 and the blocking structure 101 may also be formed separately, and the blocking structure 101 may be formed before or after the first conductive connection 102 is formed, which is not limited in the present disclosure. The blocking structure 101 defines a chip filling area, and the first conductive connection 102 is formed in the chip filling area.

[0109] refer to Fig. 9 , the chip structure 80 is connected to the transfer board 100, and the chip structure 80 is disposed in the chip filling area of ​​each packaging area R1. For example, the chip structure 80 can be connected to the transfer board 100 through a conductive connector 104, and the conductive connector 104 includes Figure 8B The first conductive connector 102 shown may also include a second conductive connector (eg, solder) and a third conductive connector (eg, metal such as copper). The specific structure of the conductive connector 104 can be referred to in Figure 2 , and for the sake of simplicity in the diagram Fig. 9 The bonding process of the chip structure 80 and the interposer 100 may include a welding process.

[0110] In some embodiments, the chip structure 80 includes one or more chips 80a, and the one or more chips 80a can select appropriate chip types according to product requirements, and can be system on chip (SoC), digital signal processor (DSP) chip, graphic processing unit (GPU), application specific integrated circuit (ASIC) chip, memory chip, central processing unit (CPU), tensor processing unit (TPU), neural network processor (NPU), deep learning processor (DPU), accelerated processing unit (APU), general-purpose computing on graphics processing unit (GPGPU), etc. For example, in each packaging area R1, multiple chips 80a are arranged side by side on the transfer board 100, and are arranged in the chip filling area defined by the blocking structure 101, and the multiple chips 80a may include chips of the same type or different types. For example, one of the chips 80a may be a system chip, and another of the chips 80a may be a memory chip, such as a high bandwidth memory (HBM) chip. It should be understood that the number of chips shown in the figure is only for illustration, and the present disclosure is not limited thereto.

[0111] refer to Fig.10 , a bottom filling process is performed to form a bottom filling layer 105 in each packaging region R1. The bottom filling process may include a dispensing process, for example, a bottom filling material 51 may be applied to the chip filling region defined by the barrier structure 101 by a dispensing device 50, and the bottom filling material 51 has fluidity, extends in the chip filling region, and fills the space between the chip structure 80 and the transfer board 100 by capillary action. Afterwards, a curing process is performed on the bottom filling material 51 to form a bottom filling layer 105.

[0112] In some embodiments, a bottom filling material with high fluidity (e.g., low viscosity) may be selected to form the bottom filling layer 105, thereby facilitating the avoidance or reduction of the probability of generating pores in the bottom filling layer 105, thereby improving the reliability and device performance of the bottom filling layer and the package structure formed. In some examples, the larger the size of the transfer board and the denser the conductive connectors 104, the more a bottom filling layer with high fluidity (e.g., low viscosity) is required for gap filling, thereby improving the reliability and device performance of the package structure.

[0113] Moreover, since a blocking structure 101 is formed on the adapter board 100, the blocking structure 101 can prevent the bottom filling material from spreading to areas outside the chip filling area. Therefore, even if a high-fluidity bottom filling material is used, the bottom filling layer can be confined within the chip filling area, and will not spread to a larger area due to the high fluidity of the bottom filling material.

[0114] Therefore, by setting the blocking structure 101, the bottom filling layer 105 can be confined within the chip filling area to prevent the bottom filling layer 105 from extending to the edge of the packaging area R1 or the cutting area R2. In addition, due to the setting of the blocking structure, the selection of the bottom filling material can be more flexible. For example, a high-flow bottom filling material can be used, thereby improving the incidence of pores in the bottom filling layer. For example, the bottom filling layer can be made substantially free of pores, or the number of pores can be very small.

[0115] refer to Fig.11 , an encapsulation layer 106 is formed on the transfer board 100. The encapsulation layer 106 may include a molding compound, such as an epoxy molding compound (EMC), and may be formed by a molding process. The encapsulation layer 106 is formed in the entire area on the transfer board 100; for example, the encapsulation layer 106 may be formed in a plurality of packaging regions R1 to encapsulate the barrier structure, the chip structure, and the bottom filling layer of each packaging region R1, and is also formed in the cutting region R2. In some embodiments, an encapsulation material layer may be formed on the transfer board by a molding process to encapsulate the chip structure, the barrier structure, and the bottom filling layer, and then the encapsulation material layer is subjected to a planarization process (for example, a grinding process such as chemical mechanical polishing) to form the encapsulation layer 106. For example, the planarization process may remove the encapsulation material located on the side of the chip structure 80 away from the transfer board, thereby exposing the surface of the chip structure 80 away from the transfer board, and making the formed encapsulation layer 106 have a surface flush with the chip structure 80. In some other embodiments, the planarization process may be omitted, or the planarization process does not completely remove the encapsulation material on the side of the chip structure away from the adapter, so that the surface of the chip structure 80 away from the adapter is covered by the formed encapsulation layer.

[0116] For example, the encapsulation layer 106 includes a first portion P1 located in each packaging region R1 and a second portion P2 located in the cutting region R2. The bottom filling layer 105 and the first portion P1 of the encapsulation layer 106 overlap in a direction perpendicular to the main surface of the transfer board 100, and the bottom filling layer 105 and the second portion P2 of the encapsulation layer 106 do not overlap in a direction perpendicular to the main surface of the transfer board 100. That is, the orthographic projection of the bottom filling layer 105 on the main surface of the transfer board 100 is staggered from the orthographic projection of the second portion of the encapsulation layer 106 on the main surface of the transfer board 100, and for example, they are not adjacent to each other.

[0117] refer to Fig.11 and Fig.12 , remove the carrier 20 and the attachment layer 21, and expose the side of the adapter board 100 away from the chip structure. For example, the attachment layer 21 may be irradiated with laser or ultraviolet (UV) light, so that the attachment layer 21 loses its stickiness under the light, so that the attachment layer 21 and the carrier 20 can be separated from the overlying structure such as the adapter board 100, and the surface of the adapter board 100 away from the chip structure is exposed.

[0118] refer to Fig.12 , a conductive terminal 120 is formed on a side of the transfer board 100 away from the chip structure, thereby forming a wafer-level structure 150. The wafer-level structure 150 includes a plurality of package structures 500 formed in a plurality of package regions R1, and the cutting region R2 is located between the plurality of package structures 500, so that the plurality of package structures 500 are spaced apart from each other. In some embodiments, the conductive terminal 120 may include a conductive column and / or a solder ball, for example, a conductive column disposed on a side of the transfer board 100 away from the chip structure, and a solder ball disposed on a side of the conductive column away from the transfer board.

[0119] refer to Fig.12 and Fig.13 , performing a cutting process on the wafer-level structure 150 to cut the plurality of package structures 500 apart and form a plurality of package structures 500 that are independent of each other, Fig.13 FIG. 5 shows the package structure 500 formed after the cutting process. Figures 2 to 6D The description is roughly the same and will not be repeated here.

[0120] The cutting process may include a mechanical cutting process, a laser cutting process, or a combination thereof. For example, the cutting process may include cutting the wafer-level structure 150 along the cutting region R2 using a cutting blade 130. For example, the cutting process cuts through the encapsulation layer 106 and the adapter plate 100 located in the cutting region R2. Fig.12As shown, in the wafer-level structure 150, the bottom filling layer 105 of the plurality of package structures 500 is confined within the chip filling area defined by the barrier structure 101 within the package area R1, and does not extend to the cutting area R2; therefore, the cutting process does not cut the bottom filling layer, nor does it cut the interface between the different materials of the encapsulation layer 106 and the bottom filling layer 105, and the interface between the bottom filling layer and the transfer board. In this way, delamination between the encapsulation layer and the bottom filling layer and between the bottom filling layer and the transfer board can be avoided, thereby improving the reliability and device performance of the formed package structure.

[0121] In some embodiments, the packaging structure further includes: a packaging substrate, which is disposed on a side of the adapter plate away from the chip structure and is electrically connected to the adapter plate. In some embodiments, the packaging structure further includes: a circuit board, which is disposed on a side of the packaging substrate away from the packaging substrate and is electrically connected to the packaging substrate.

[0122] Fig.14 and Fig.15 Schematic cross-sectional views of package structures according to other embodiments of the present disclosure are shown.

[0123] refer to Fig.14 In some embodiments, the above reference Figures 2 to 13 The package structure described is a CoW package, and the CoW package can be further connected to a package substrate to form a chip-on-wafer-on-substrate (CoWoS) package. For example, the CoW package can be electrically connected to the package substrate 300 through a conductive terminal 120, wherein the chip structure 80 is electrically connected to the package substrate 300 through an adapter plate 100. In some embodiments, the package structure may also include a bottom fill layer 302 to fill the space between the CoW package and the package substrate 300; the bottom fill layer 302 may also extend to cover the sidewalls of the CoW package. A reinforcement ring 301 may be provided on the package substrate 300 to facilitate controlling the warping of the package structure. A conductive terminal 303 is also provided on the side of the package substrate 300 away from the adapter plate 100 for further connecting the CoWoS package to other package components, such as a circuit board. The conductive terminal 303 may be or include a ball grid array (BGA). In the embodiment of the present disclosure, the encapsulation layer is formed on the transfer board and included in the CoW package before the CoW package is connected to the package substrate. Therefore, the encapsulation layer can provide protection for the chip during the process of mounting the CoW package on the package substrate.

[0124] For example, Fig.15 As shown, the CoWoS package can be further connected to the circuit board 400 via the conductive terminals 303 .

[0125] In various embodiments of the present disclosure, by providing a blocking structure on the adapter plate, the bottom filling layer is confined within the chip filling area defined by the blocking structure, thereby preventing the bottom filling layer from being cut during the cutting process, thereby preventing the bottom filling layer and the encapsulation layer and the bottom filling layer and the adapter plate from being delaminated due to the cutting process; moreover, a high-fluidity material can be used to form the bottom filling layer, thereby reducing the incidence of pores in the bottom filling layer; therefore, the reliability of the packaging structure and the device performance can be improved. On the other hand, since a blocking structure is provided to block the bottom filling layer, the edge spacing between the edge of the chip structure and the edge of the package can also be set to be smaller, for example, the edge spacing can be controlled within 1 mm, which is conducive to reducing the overall size of the packaging structure and realizing the miniaturization of the packaging structure.

[0126] There are a few points to note:

[0127] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0128] (2) Unless there is a conflict, the features of the same embodiment or different embodiments of the present disclosure may be combined with each other.

[0129] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A packaging structure, characterized in that: include: Adapter plate; a blocking structure disposed on the interposer and defining a chip filling region, wherein the interposer has an extension extending beyond the chip filling region in a direction parallel to a major surface of the interposer; A chip structure, disposed in the chip filling area and electrically connected to the adapter board; A bottom filling layer, surrounded by the barrier structure and confined within the chip filling area, and filling the space between the chip structure and the adapter plate; as well as an encapsulation layer, disposed on the adapter plate and encapsulating the blocking structure, the chip structure and the bottom filling layer, The bottom filling layer has a bottom filling edge, the encapsulation layer has an encapsulation edge, the encapsulation edge is aligned with the side wall of the adapter plate in a direction perpendicular to the main surface of the adapter plate, and the orthographic projections of the bottom filling edge and the encapsulation edge on the main surface of the adapter plate are staggered with each other.

2. The packaging structure according to claim 1, characterized in that: In a direction parallel to the main surface of the interposer, a first distance between an edge of the chip structure and the blocking structure is smaller than a second distance between the edge of the chip structure and an edge of the encapsulation.

3. The packaging structure according to claim 1, characterized in that: The underfill edge contacts an inner sidewall of the barrier structure.

4. The packaging structure according to claim 1, characterized in that: The encapsulation layer has an encapsulation end portion close to the encapsulation edge, the blocking structure and the encapsulation end portion are located on the extension portion of the adapter plate, and the outer wall of the blocking structure away from the bottom filling layer and the surface of the blocking structure away from the adapter plate are covered by the encapsulation end portion.

5. The packaging structure according to claim 1, characterized in that: The bottom filling layer includes a main body portion and an overflow portion, the main body portion filling the space between the chip structure and the adapter board, the overflow portion extending beyond the edge of the chip structure in a direction parallel to the main surface of the adapter board and having a surface covered by the encapsulation layer, wherein the bottom filling edge is the surface of the overflow portion farthest from the chip structure in a direction parallel to the main surface of the adapter board.

6. The packaging structure according to claim 1 or 5, characterized in that: Part of the surface of the bottom filling layer contacts the encapsulation layer, and the orthographic projection of the contact interface between the bottom filling layer and the encapsulation layer on the main surface of the adapter plate is offset from the orthographic projection of the encapsulation edge on the main surface of the adapter plate.

7. The packaging structure according to claim 1, characterized in that: The chip structure is electrically connected to the adapter plate via a conductive connector, and at least a portion of the blocking structure is disposed in the same layer as a portion of the conductive connector and comprises the same material.

8. The packaging structure according to any one of claims 1 to 5 and 7, characterized in that: The blocking structure includes one or more blocking rings, and the chip filling area is defined by an inner sidewall of a blocking ring among the one or more blocking rings that is farthest from the chip structure.

9. The packaging structure according to claim 8, characterized in that: Each of the one or more barrier rings is a single-layer structure or a multi-layer stacked structure.

10. The packaging structure according to claim 8, characterized in that: The one or more blocking rings in the blocking structure each include a first blocking member and a second blocking member, the second blocking member is stacked and arranged on a side of the first blocking member away from the adapter plate, and the first blocking member and the second blocking member include the same or different materials.

11. The packaging structure according to claim 10, characterized in that: One of the first blocking member and the second blocking member comprises an insulating material, and the other of the first blocking member and the second blocking member comprises a metal material; or The first blocking member and the second blocking member both include insulating material; or The first blocking member and the second blocking member both include a metal material.

12. The packaging structure according to claim 10, characterized in that: In a direction parallel to the main surface of the adapter plate, the first blocking member has a first blocking width, and the second blocking member has a second blocking width, wherein The first blocking width is greater than the second blocking width; or The first blocking width is equal to the second blocking width, and the first blocking member and the blocking member have side walls that are aligned in a direction perpendicular to a major surface of the adapter plate; or The first blocking width is smaller than the second blocking width, and the second blocking member covers a side wall of the first blocking member.

13. The packaging structure according to any one of claims 1 to 5 and 7, characterized in that: The blocking structure includes a plurality of blocking rings, and the chip filling area includes: a main body region defined by an inner sidewall of a barrier ring among the plurality of barrier rings that is closest to the chip structure, and the chip structure is disposed in the main body region; and A buffer zone is defined by side walls of adjacent barrier rings among the plurality of barrier rings facing each other.

14. The packaging structure according to claim 13, characterized in that: The bottom filling layer is entirely located within the main body region; or The bottom filling layer includes a portion located in the main region and further includes an extending portion extending into the buffer region.

15. The packaging structure according to any one of claims 1 to 5 and 7, characterized in that: The packaging structure further includes: The packaging substrate is arranged on a side of the adapter board away from the chip structure and is electrically connected to the adapter board.

16. The packaging structure according to claim 15, characterized in that: The packaging structure further includes: The circuit board is arranged on a side of the packaging substrate away from the packaging substrate and is electrically connected to the packaging substrate.

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