Interface expansion circuit, interface expansion device, mainboard and electronic equipment
By designing an interface expansion circuit that includes uplink interface conversion, downlink interface driving and switching circuits, the complexity and high cost of existing interface expansion devices are solved, and the number and type of interfaces are expanded, while reducing area and power consumption.
Patent Information
- Application Number
- CN202323669606.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2033-12-29
AI Technical Summary
The circuit design of existing interface expansion devices is complex and uses many devices, which leads to problems such as large area, high power consumption and high cost.
An interface expansion circuit including an uplink interface conversion circuit, a downlink interface driver circuit and a switching circuit is designed. A multiple first adapter interface is formed through uplink interface conversion, and the interface type expansion is realized using the switching circuit and the downlink interface driver circuit. Supports multiple transmission protocols.
The number and type of interfaces are expanded, the circuit construction is simplified, and the area, power consumption and cost are reduced.
Smart Images
Figure CN222145505U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of interface expansion, in particular to an interface expansion circuit, an interface expansion device, a mainboard and electronic equipment. Background Art
[0002] In the electronics industry, when the number of peripheral interfaces of main control devices such as computers is limited and the supported transmission protocols are limited, it is often necessary to use interface expansion devices such as PCIE expansion cards or LPC expansion cards to enrich and expand the peripheral interfaces to connect peripheral devices with different transmission protocols.
[0003] However, the expansion circuit design of this interface expansion device is relatively complex and uses many components, resulting in a large area of the interface expansion device and high power consumption and cost. Utility Model Content
[0004] In view of the above problems, an interface expansion circuit, an interface expansion device, a mainboard and an electronic device are proposed to overcome the above problems or at least partially solve the above problems, so as to solve the problem that the circuit design of the current interface expansion device is relatively complex and uses more components, resulting in a large area of the interface expansion device and high power consumption and cost.
[0005] In order to solve the above problems, in a first aspect, the utility model discloses an interface expansion circuit, which includes an uplink interface conversion circuit, a downlink interface driving circuit and a switching circuit;
[0006] The uplink interface conversion circuit has an uplink interface and a plurality of first transfer interfaces, wherein the uplink interface is used to be electrically connected to an uplink main control device;
[0007] The downstream interface driving circuit has a second adapter interface and a downstream interface, wherein the downstream interface is used to be electrically connected to a downstream peripheral device;
[0008] The switching circuit has a signal input pin and a signal output pin, wherein the signal input pin of the switching circuit is used to be electrically connected to an uplink master control device;
[0009] Each of the first adapter interfaces is electrically connected to a second adapter interface of the downstream interface driving circuit, the signal output pin of the switching circuit is electrically connected to the upstream interface conversion circuit and the downstream interface driving circuit, and the switching circuit controls the downstream interface driving circuit to transmit data in a plurality of different interface modes, wherein the downstream interface and the upstream interface support different transmission protocols.
[0010] Optionally, the downlink interface driving circuit is a half-duplex asynchronous serial communication transceiver, and the half-duplex asynchronous serial communication transceiver has a first mode configuration pin and a second mode configuration pin;
[0011] Some signal output pins of the switching circuit are electrically connected to the first mode configuration pin and the second mode configuration pin.
[0012] Optionally, the switching circuit includes a first switching circuit;
[0013] The signal output pin of the first switching circuit is electrically connected to the first mode configuration pin and the second mode configuration pin, and is used to control the downstream interface driving circuit to switch to a target interface mode.
[0014] Optionally, the first switching circuit includes a first transistor, a first pull-up resistor, a first pull-down resistor, a second transistor, a second pull-up resistor, and a second pull-down resistor;
[0015] The input pin of the first transistor is electrically connected to the first pull-up resistor, and the node between the input pin of the first transistor and the first pull-up resistor forms a first signal output pin, and the first signal output pin is electrically connected to the first mode configuration pin; the output pin of the first transistor is grounded; the control pin of the first transistor is electrically connected to the first pull-down resistor, and the node between the control pin of the first transistor and the first pull-down resistor forms a first signal input pin, and the first signal input pin is used to be electrically connected to an upstream master control device;
[0016] The input pin of the second transistor is electrically connected to the second pull-up resistor, and the node between the input pin of the second transistor and the second pull-up resistor forms a second signal output pin, and the second signal output pin is electrically connected to the second mode configuration pin; the output pin of the second transistor is grounded; the control pin of the second transistor is electrically connected to the second pull-down resistor, and the node between the control pin of the second transistor and the second pull-down resistor forms a second signal input pin, and the second signal input pin is used to be electrically connected to an upstream master control device.
[0017] Optionally, the uplink interface conversion circuit is a conversion chip, and the conversion chip has an interface configuration pin and a reset pin;
[0018] Some signal output pins of the switching circuit are electrically connected to the interface configuration pin and the reset pin, and are used to control the uplink interface conversion circuit to switch to a mode consistent with the downlink interface driving circuit.
[0019] Optionally, the switching circuit further includes a second switching circuit;
[0020] The signal output pin of the second switching circuit is electrically connected to the interface configuration pin and the reset pin, and is used to control the uplink interface conversion circuit to switch to a mode consistent with the downlink interface driving circuit.
[0021] Optionally, the second switching circuit includes a third transistor, a third pull-up resistor, a fourth pull-up resistor and a fourth transistor;
[0022] The input pin of the third transistor is electrically connected to the third pull-up resistor, and the node between the input pin of the third transistor and the third pull-up resistor forms a third signal output pin, and the third signal output pin is electrically connected to the interface configuration pin; the output pin of the third transistor is grounded; the control pin of the third transistor is electrically connected to the fourth pull-up resistor, and the node between the control pin of the third transistor and the fourth pull-up resistor forms a third signal input pin, and the third signal input pin is used to be electrically connected to an upstream master control device;
[0023] The input pin of the fourth transistor forms a fourth signal output pin, and the fourth signal output pin is electrically connected to the reset pin; the output pin of the fourth transistor is grounded; the control pin of the fourth transistor forms a fourth signal input pin, and the fourth signal input pin is used to be electrically connected to the upstream master control device.
[0024] Optionally, the interface expansion circuit further includes a connector and an electrostatic protection device;
[0025] The connector is electrically connected to the downstream interface, and the electrostatic protection device is arranged between the connector and the downstream interface.
[0026] In a second aspect, the utility model further discloses an interface expansion device, which includes the interface expansion circuit described in the first aspect of the utility model.
[0027] In a third aspect, the utility model further discloses a mainboard, which includes the interface expansion circuit described in the first aspect of the utility model.
[0028] In a fourth aspect, the utility model further discloses an electronic device, which includes the interface expansion circuit described in the first aspect of the utility model.
[0029] The utility model embodiment includes the following advantages:
[0030] The embodiment of the utility model can expand the uplink interface to form more first adapter interfaces by using the uplink interface conversion circuit, thereby increasing the number of interfaces. In addition, the switching circuit and the downlink interface driving circuit can be used to convert the multiple first adapter interfaces formed by the expansion to form downlink interfaces that match the peripheral devices, thus achieving the expansion of the interface types. It can be seen that the interface expansion circuit of the embodiment of the utility model can achieve the expansion of the number of interfaces and the expansion of the interface types through a relatively simple circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 It is a schematic diagram of the architecture of an interface expansion circuit of the utility model;
[0032] Figure 2 This is a schematic diagram of the circuit principle of a first switching circuit of the utility model;
[0033] Figure 3 It is a circuit principle schematic diagram of a second switching circuit of the utility model;
[0034] Figure 4 It is a schematic diagram of the architecture of another interface expansion circuit of the utility model. DETAILED DESCRIPTION
[0035] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0036] Reference Figure 1 , the embodiment of the utility model provides an interface expansion circuit, the interface expansion circuit includes an uplink interface conversion circuit 10, a downlink interface driving circuit 11 and a switching circuit 12;
[0037] The uplink interface conversion circuit 10 has an uplink interface 101 and a multi-channel first adapter interface 102, wherein the uplink interface 101 is used to be electrically connected to the uplink main control device 20;
[0038] The downstream interface driving circuit 11 has a second adapter interface 111 and a downstream interface 112, wherein the downstream interface 112 is used to be electrically connected to the downstream peripheral device 30;
[0039] The switching circuit 12 has a signal input pin 12a and a signal output pin 12b, wherein the signal input pin 12a of the switching circuit 12 is used to be electrically connected to the uplink master control device 20;
[0040] Each of the first adapter interfaces 102 is electrically connected to a second adapter interface 111 of the downstream interface driving circuit 11, and the signal output pin 12b of the switching circuit 12 is electrically connected to the upstream interface conversion circuit 10 and the downstream interface driving circuit 11. The switching circuit 12 controls the downstream interface driving circuit 11 to transmit data in a plurality of different interface modes, wherein the downstream interface 112 and the upstream interface 101 support different transmission protocols.
[0041] Specifically, the interface expansion circuit of the embodiment of the utility model can be used in the field of industrial communication and industrial control to expand the peripheral interface of the main control device in the uplink line of industrial control communication to increase the number and type of interfaces, thereby improving the expansion connection performance of the main control device.
[0042] like Figure 1 In one implementation of the present utility model, the interface expansion circuit includes an uplink interface conversion circuit 10, a downlink interface driving circuit 11 and a switching circuit 12. The uplink interface conversion circuit 10 is electrically connected to the main control device 20 via the uplink interface 101, and expands the corresponding interface of the main control device 20 into a multi-channel first transfer interface 102. In addition, each uplink interface conversion circuit 10 is connected to a downlink interface driving circuit 11, specifically, as shown in FIG. Figure 1 As shown in the figure, the uplink interface conversion circuit 10 and the downlink interface driving circuit 11 are electrically connected through the first adapter interface 102 and the second adapter interface 112. Then, a peripheral device 30 can be connected to the downlink interface 112 of the corresponding downlink interface driving circuit 11 according to the needs of the control task.
[0043] In addition, in the embodiment of the utility model, the uplink interface 101 and the interface on the main control device 20 are interfaces supporting the same protocol, and the uplink interface 101 and the downlink interface 112 respectively support different transmission protocols. When data needs to be transmitted between the main control device 20 and the peripheral device 30, the main control device 20 can transmit a control signal to the switching circuit 12, and use the switching circuit 12 to switch the uplink interface conversion circuit 10 and the downlink interface driving circuit 11 to the same transmission mode. Thus, the uplink interface 101 can be converted into a downlink interface 112 compatible with the peripheral device 30.
[0044] In practical applications, the interface on the main control device 20 connected to the uplink interface 101 may be a USB (Universal Serial Bus), an I 2The first adapter interface 102 and the second adapter interface 112 may be UART (Universal Asynchronous Receiver / Transmitter) interfaces. It is understood that, depending on the type of interface connected between the main control device 20 and the uplink interface 101, the uplink interface conversion circuit 10 may be a USB to UART circuit, an I2C to I2C circuit, or a SPI to I2C circuit. 2 C to UART circuit or SPI to UART circuit and other conversion circuits.
[0045] Therefore, the embodiment of the utility model can expand the uplink interface 101 to form more first adapter interfaces 102 by using the uplink interface conversion circuit 10, thereby increasing the number of interfaces. In addition, the switching circuit 12 and the downlink interface driving circuit 11 can be used to convert the expanded multiple first adapter interfaces 102 to form downlink interfaces 112 that match the peripheral device 30, thereby achieving the expansion of interface types. It can be seen that the interface expansion circuit of the embodiment of the utility model can achieve the expansion of interface types while achieving the expansion of interface number through a relatively simple circuit structure.
[0046] Optionally, refer to Figure 2 , the downlink interface driving circuit 11 is a half-duplex asynchronous serial communication transceiver, and the half-duplex asynchronous serial communication transceiver has a first mode configuration pin MODE0 and a second mode configuration pin MODE1;
[0047] Some signal output pins of the switching circuit 12 are electrically connected to the first mode configuration pin MODE0 and the second mode configuration pin MODE1 .
[0048] Specifically, if Figure 2 As shown, in one implementation of the utility model, the downstream interface driving circuit 11 can be a half-duplex asynchronous serial communication transceiver. Specifically, the downstream interface driving circuit 11 can use a transceiver that is compatible with RS232, RS422 and RS485 transmission protocols. In this transceiver, two mode configuration pins are included, namely, a first mode configuration pin MODE0 and a second mode configuration pin MODE1. Figure 1 and Figure 2As shown in FIG. 1 , the first mode configuration pin MODE0, the second mode configuration pin MODE1, the second adapter interface 111, and the downstream interface 112 all correspond to pins with different functions in the downstream interface driving circuit 11, wherein the second adapter interface 111 is used to connect with the upstream interface conversion circuit 10, and can receive data transmitted from the upstream interface conversion circuit 10, and the data transmitted to the downstream interface driving circuit 11 can be sent to the corresponding peripheral device 30 through the downstream interface 112. Some signal output pins of the switching circuit 12 are electrically connected to the first mode configuration pin MODE0 and the second mode configuration pin MODE1, and the switching circuit 12 can control the level of the first mode configuration pin MODE0 to be 0 or 1, and control the level of the second mode configuration pin MODE1 to be 0 or 1, respectively, and correspond the combination of the high and low levels of the two mode configuration pins to different transmission modes, so that the transmission mode of the downstream interface driving circuit 11 can be adjusted by controlling the high and low levels of the two mode configuration pins. When the transmission mode of the downstream interface driving circuit 11 is switched, that is, the transmission protocol of the data transmission line between the second adapter interface 111 and the downstream interface 112 changes accordingly.
[0049] For example, when MODE0:MODE1=[1:1], the downstream interface driving circuit 11 works in RS422 mode, and the data transmission protocol between the second adapter interface 111 and the downstream interface 112 is the RS422 protocol; when MODE0:MODE1=[0:1], the downstream interface driving circuit 11 works in RS485 mode, and the data transmission protocol between the second adapter interface 111 and the downstream interface 112 is the RS485 protocol; when MODE0:MODE1=[1:0], the downstream interface driving circuit 11 works in RS232 mode, and the data transmission protocol between the second adapter interface 111 and the downstream interface 112 is the RS232 protocol.
[0050] Optionally, refer to Figure 2 , the switching circuit 12 includes a first switching circuit 121;
[0051] The signal output pin of the first switching circuit 121 is electrically connected to the first mode configuration pin MODE0 and the second mode configuration pin MODE1, and is used to control the downstream interface driving circuit 11 to switch to the target interface mode.
[0052] Specifically, if Figure 2As shown, in one implementation of the embodiment of the utility model, the switching circuit 12 may include a first switching circuit 121, and the first switching circuit 121 has two signal output pins, one of which is electrically connected to the first mode configuration pin MODE0, and is used to control the level of the first mode configuration pin MODE0 to be 0 or 1, and the other signal output pin is electrically connected to the second mode configuration pin MODE1, and is used to control the level of the second mode configuration pin MODE1 to be 0 or 1. The first switching circuit 121 is a switching circuit dedicated to controlling the working mode of the downstream interface driving circuit 11, and can switch the working mode of the downstream interface driving circuit 11 to one of the RS422 mode, RS485 mode or RS232 mode as the target interface mode.
[0053] Optionally, refer to Figure 2 , the first switching circuit 121 includes a first transistor Q1, a first pull-up resistor R1, a first pull-down resistor R2, a second transistor Q2, a second pull-up resistor R3 and a second pull-down resistor R4;
[0054] The input pin of the first transistor Q1 is electrically connected to the first pull-up resistor R1, and the node between the input pin of the first transistor Q1 and the first pull-up resistor R1 forms a first signal output pin OUT_1, and the first signal output pin OUT_1 is electrically connected to the first mode configuration pin MODE0; the output pin of the first transistor Q1 is grounded; the control pin of the first transistor Q1 is electrically connected to the first pull-down resistor R2, and the node between the control pin of the first transistor Q1 and the first pull-down resistor R4 forms a first signal input pin IN_1, and the first signal input pin IN_1 is used to be electrically connected to the uplink master control device 20;
[0055] The input pin of the second transistor Q2 is electrically connected to the second pull-up resistor R3, and the node between the input pin of the second transistor Q2 and the second pull-up resistor R3 forms a second signal output pin OUT_2, and the second signal output pin OUT_2 is electrically connected to the second mode configuration pin MODE1; the output pin of the second transistor Q2 is grounded; the control pin of the second transistor Q2 is electrically connected to the second pull-down resistor R4, and the node between the control pin of the second transistor Q2 and the second pull-down resistor R4 forms a second signal input pin IN_2, and the second signal input pin IN_2 is used to be electrically connected to the upstream master control device 20.
[0056] Specifically, if Figure 2As shown, in one implementation of the embodiment of the utility model, the first switching circuit 121 may include a first transistor Q1, a first pull-up resistor R1, a first pull-down resistor R2, a second transistor Q2, a second pull-up resistor R3, and a second pull-down resistor R4. The first transistor Q1 and the second transistor Q2 may be triodes or MOS transistors with three pins, and these transistors may be switched between an on or off state under the action of a control signal, thereby realizing the control of the level signal of the first mode configuration pin MODE0 and the second mode configuration pin MODE1.
[0057] To clearly describe the working principle of the first switching circuit 121 , the level control process of the first mode configuration pin MODE0 and the second mode configuration pin MODE1 is described below by taking the first transistor Q1 and the second transistor Q2 using NPN transistors as an example.
[0058] Combination Figure 2 As shown in the figure, the collector C of the first transistor Q1 is electrically connected to one end of the first pull-up resistor R1, and the other end of the first pull-up resistor R1 can be connected to a 3.3V power supply, which can be provided by the main control device 20 or an independent power supply module. The node between the collector C of the first transistor Q1 and the first pull-up resistor R1 forms a first signal output pin OUT_1, and the first signal output pin OUT_1 is electrically connected to the first mode configuration pin MODE0 of the downstream interface driving circuit 11. The emitter E of the first transistor Q1 is grounded. The base B of the first transistor Q1 is connected to one end of the first pull-down resistor R2, and the other end of the first pull-down resistor R2 is grounded. At the same time, a first signal input pin IN_1 is formed between the base B of the first transistor Q1 and the first pull-down resistor R4 and is connected to the main control device 20. For example, the first signal input pin IN_1 can be connected to the general input and output pin GPIO2 of the processor in the main control device 20.
[0059] The collector C of the second transistor Q2 is electrically connected to one end of the second pull-up resistor R3, and the other end of the second pull-up resistor R3 can be connected to a 3.3V power supply, and the 3.3V power supply and the 3.3V power supply connected to the first pull-up resistor R1 can be the same power supply. The node between the collector C of the second transistor Q2 and the second pull-up resistor R3 forms a second signal output pin OUT_2, and the second signal output pin OUT_2 is electrically connected to the second mode configuration pin MODE1 of the downstream interface driving circuit 11. The emitter E of the second transistor Q2 is grounded. The base B of the second transistor Q2 is connected to one end of the second pull-down resistor R4, and the other end of the second pull-down resistor R4 is grounded. At the same time, a second signal input pin IN_2 is formed between the base B of the second transistor Q2 and the second pull-down resistor R4 and is connected to the main control device 20. For example, the second signal input pin IN_2 can be connected to another general input and output pin GPIO3 of the processor in the main control device 20.
[0060] Combination Figure 1 and Figure 2 As shown in FIG. 1 , the first signal input pin IN_1 and the second signal input pin IN_2 are two input pins of the signal input pins 12 a , and the first signal output pin OUT_1 and the second signal output pin OUT_2 are two output pins of the signal output pins 12 b .
[0061] When the general input and output pin GPIO2 of the processor of the main control device 20 does not output a control signal, the base B of the first transistor Q1 is at a low level under the action of the first pull-down resistor R2, and the collector C and the emitter E of the first transistor Q1 are in a disconnected state. At this time, under the action of the first pull-up resistor R1, the first signal output pin OUT_1 transmits a high-level signal 1 to the first mode configuration pin MODE0. When the general input and output pin GPIO2 of the processor of the main control device 20 outputs a high-level control signal, under the control of GPIO2, the base B of the first transistor Q1 is at a high level, and the collector C and the emitter E of the first transistor Q1 are in a conductive state. At this time, the signal of the first signal output pin OUT_1 is pulled down to a low-level signal 0, and the first signal output pin OUT_1 transmits a low-level signal 0 to the first mode configuration pin MODE0.
[0062] Similar to the above process, when the general input and output pin GPIO3 of the processor of the main control device 20 does not output a control signal, the second signal output pin OUT_2 transmits a high level signal 1 to the second mode configuration pin MODE1. When the general input and output pin GPIO3 of the processor of the main control device 20 outputs a high level control signal, the second signal output pin OUT_2 transmits a low level signal 0 to the second mode configuration pin MODE1.
[0063] In addition, it should be noted that Figure 2 Based on the first switching circuit 121 shown in the figure, those skilled in the art may also replace the first transistor Q1 and the second transistor Q2 with NMOS transistors, or use a PMOS transistor or a PNP transistor as the first transistor Q1 and the second transistor Q2, and make adaptive adjustments to the connection positions of the pull-up resistor and the pull-down resistor in the circuit. The embodiments of the utility model are for these Figure 2 The basic transformation alternatives will not be described in detail one by one.
[0064] Therefore, the first switching circuit 121 is electrically connected to the main control device 20. After receiving the control signal transmitted from the main control device 20, the first switching circuit 121 can control the levels of the two mode configuration pins in the downstream interface driving circuit 11 by utilizing the cooperation of the first transistor Q1, the second transistor Q2 and the corresponding pull-up resistor and the pull-down resistor, thereby completing the switching adjustment of the transmission mode of the downstream interface driving circuit 11.
[0065] Optionally, refer to Figure 3 , the uplink interface conversion circuit 10 is a conversion chip, and the conversion chip has an interface configuration pin CFG and a reset pin RESET;
[0066] Some signal output pins of the switching circuit 12 are electrically connected to the interface configuration pin CFG and the reset pin RESET, and are used to control the uplink interface conversion circuit 10 to switch to a mode consistent with the downlink interface driving circuit 11 .
[0067] Specifically, if Figure 3 As shown, in one implementation of the utility model embodiment, the uplink interface conversion circuit 10 can be a conversion chip, for example, the uplink interface conversion circuit 10 can be a USB conversion chip, which can convert a single-channel USB interface into an eight-channel UART interface. The conversion chip has an interface configuration pin CFG and a reset pin RESET.
[0068] Combination Figure 1 and Figure 3, the interface configuration pin CFG, the reset pin RESET, the first adapter interface 102, and the uplink interface 101 all correspond to the pins with different functions in the uplink interface conversion circuit 10, wherein the uplink interface 101 is used to connect with the main control device 20, and can receive the data transmitted from the main control device 20 to the uplink interface conversion circuit 10, and the data transmitted to the uplink interface conversion circuit 10 can be sent to the corresponding downlink interface driving circuit 11 through the first adapter interface 102. Some signal output pins of the switching circuit 12 are electrically connected to the interface configuration pin CFG and the reset pin RESET, and the switching circuit 12 can control the level of the interface configuration pin CFG to 0 or 1, and control the level of the reset pin RESET to 0 or 1, respectively, and correspond the combination of the high and low levels of the two pins to different transmission modes, so that the transmission mode of the uplink interface conversion circuit 10 can be adjusted by controlling the high and low levels of the two pins. When the transmission mode of the uplink interface conversion circuit 10 is switched, that is, the transmission protocol of the data transmission line between the uplink interface 101 and the first adapter interface 102 changes accordingly.
[0069] For example, when the uplink interface conversion circuit 10 needs to work in RS232 or RS422 mode, the interface configuration pin CFG can be configured to a low level, and the reset pin RESET can be configured to a high level. At this time, the data transmission protocol between the uplink interface 101 and the first transfer interface 102 is the RS232 or RS422 protocol. When the uplink interface conversion circuit 10 needs to work in RS485 mode, the working mode of the uplink interface conversion circuit 10 can be switched to RS485 mode by controlling the flipping change of the interface configuration pin CFG and the reset pin RESET level. At this time, the data transmission protocol between the uplink interface 101 and the first transfer interface 102 is the RS485 protocol.
[0070] Optionally, the switching circuit 12 further includes a second switching circuit 122;
[0071] The signal output pin of the second switching circuit 122 is electrically connected to the interface configuration pin CFG and the reset pin RESET, and is used to control the uplink interface conversion circuit 10 to switch to a mode consistent with the downlink interface driving circuit 11 .
[0072] Specifically, if Figure 3 As shown, in one implementation of an embodiment of the utility model, the switching circuit 12 may further include a second switching circuit 122, the second switching circuit 122 having two signal output pins, one of which is electrically connected to the interface configuration pin CFG for controlling the level of the interface configuration pin CFG to be 0 or 1, and the other is electrically connected to the reset pin RESET for controlling the level of the reset pin RESET to be 0 or 1.
[0073] The second switching circuit 122 is a switching circuit dedicated to controlling the working mode of the uplink interface conversion circuit 10 , and can switch the working mode of the uplink interface conversion circuit 10 to one of the RS422 mode, RS485 mode or RS232 mode to make it consistent with the working mode of the downlink interface driving circuit 11 .
[0074] Combination Figures 1 to 3 As can be seen from the schematic diagram, the second switching circuit 122 and the first switching circuit 121 are two independent circuits in the switching circuit 12, which are respectively used to switch and control the transmission modes of different controlled objects. The first switching circuit 121 is used to switch and control the downstream interface driving circuit 11, and the second switching circuit 122 is used to switch and control the upstream interface conversion circuit 10. Although there is no signal transmission control relationship between the first switching circuit 121 and the second switching circuit 122, since both are electrically connected to the upstream main control device 20, in actual applications, when the switching circuit 12 uses a chip with a mode switching control function, the first switching circuit 121 and the second switching circuit 122 can be packaged together in the chip, and the first switching circuit 121 and the second switching circuit 121 each form a signal input pin and a signal output pin corresponding to their own switching control function outside the chip. Optionally, refer to Figure 3 , the second switching circuit 122 includes a third transistor Q3, a third pull-up resistor R5, a fourth pull-up resistor R6 and a fourth transistor Q4;
[0075] The input pin of the third transistor Q3 is electrically connected to the third pull-up resistor R5, and the node between the input pin of the third transistor Q3 and the third pull-up resistor R5 forms a third signal output pin OUT_3, and the third signal output pin OUT_3 is electrically connected to the interface configuration pin CFG; the output pin of the third transistor Q3 is grounded; the control pin of the third transistor Q3 is electrically connected to the fourth pull-up resistor R6, and the node between the control pin of the third transistor Q3 and the fourth pull-up resistor R6 forms a third signal input pin IN_3, and the third signal input pin IN_3 is used to be electrically connected to the uplink master control device 20;
[0076] The input pin of the fourth transistor Q4 forms a fourth signal output pin OUT_4, and the fourth signal output pin OUT_4 is electrically connected to the reset pin RESET; the output pin of the fourth transistor Q4 is grounded; the control pin of the fourth transistor Q4 forms a fourth signal input pin IN_4, and the fourth signal input pin IN_4 is used to be electrically connected to the upstream master control device 20.
[0077] Specifically, if Figure 3As shown, in one implementation of the embodiment of the utility model, the second switching circuit 122 may include a third transistor Q3, a third pull-up resistor R5, a fourth pull-up resistor R6 and a fourth transistor Q4. The third transistor Q3 and the fourth transistor Q4 may be triodes or MOS transistors with three pins, and these transistors may be switched between an on or off state under the action of a control signal, thereby realizing the control of the level signals of the interface configuration pin CFG and the reset pin RESET.
[0078] To clearly describe the working principle of the second switching circuit 122, the level control process of the interface configuration pin CFG and the reset pin RESET is described below by taking the third transistor Q3 and the fourth transistor Q4 as NPN transistors as an example.
[0079] Combination Figure 3 As shown in the figure, the collector C of the third transistor Q3 is electrically connected to one end of the third pull-up resistor R5, and the other end of the third pull-up resistor R5 can be connected to a 3.3V power supply, which can be provided by the main control device 20 or an independent power supply module. The node between the collector C of the third transistor Q3 and the third pull-up resistor R5 forms a third signal output pin OUT_3, and the third signal output pin OUT_3 is electrically connected to the interface configuration pin CFG of the uplink interface conversion circuit 10. The emitter E of the third transistor Q3 is grounded. The base B of the third transistor Q3 is connected to one end of the fourth pull-up resistor R6, and the other end of the fourth pull-up resistor R6 can be connected to a 1.8V power supply, which can be provided by the main control device 20 or an independent power supply module. At the same time, a third signal input pin IN_3 is formed between the base B of the third transistor Q3 and the fourth pull-up resistor R6 and is connected to the main control device 20 . For example, the third signal input pin IN_3 can be connected to the general input and output pin GPIO11 of the processor in the main control device 20 .
[0080] The collector C of the fourth transistor Q4 forms a fourth signal output pin OUT_4, and the fourth signal output pin OUT_4 is electrically connected to the reset pin RESET of the uplink interface conversion circuit 10. The emitter E of the fourth transistor Q4 is grounded. The base of the fourth transistor Q4 forms a fourth signal input pin IN_4 connected to the main control device 20. For example, the fourth signal input pin IN_4 can be connected to another general input and output pin GPIO12 of the processor in the main control device 20.
[0081] Combination Figure 1 and Figure 3As shown in FIG. 1 , the third signal input pin IN_3 and the fourth signal input pin IN_4 are the other two input pins of the signal input pins 12 a , and the third signal output pin OUT_3 and the fourth signal output pin OUT_4 are the other two output pins of the signal output pins 12 b .
[0082] When the general input and output pin GPIO11 of the processor of the main control device 20 does not output a control signal, the base B of the third transistor Q3 is at a high level under the action of the fourth pull-up resistor R6, and the collector C and the emitter E of the third transistor Q3 are in an on state. At this time, the signal of the third signal output pin OUT_3 is pulled down to a low level signal 0, and the third signal output pin OUT_3 transmits a low level signal 0 to the interface configuration pin CFG.
[0083] When the general input and output pin GPIO2 of the processor of the main control device 20 outputs a low-level control signal, under the control of GPIO11, the base B of the third transistor Q3 is at a low level, and the collector C and the emitter E of the first transistor Q1 are in a disconnected state. At this time, under the action of the third pull-up resistor R5, the third signal output pin OUT_3 transmits a low-level signal 0 to the first mode configuration pin MODE0.
[0084] Similar to the above process, when the general purpose input and output pin GPIO3 of the processor of the main control device 20 controls the collector C and the emitter E of the first transistor Q1 to be turned on, the reset pin RESET of the uplink interface conversion circuit 10 is grounded and reset.
[0085] Combined with the above Figure 3 The second switching circuit 122 shown in the figure, when the uplink interface conversion circuit 10 needs to work in RS232 or RS422 mode, GPIO11 can be configured to be high level and GPIO12 can be configured to be low level. At this time, the interface configuration pin CFG is low level and the reset pin RESET is high level. When the uplink interface conversion circuit 10 needs to work in RS485 mode, GPIO12 can be configured to be high level first, so that the reset pin RESET is grounded and the level is flipped and reset, and GPIO11 is configured to be low level at the same time, so that the interface configuration pin CFG becomes high level, and then GPIO12 is restored to be configured to be low level, so that the reset pin RESET ends the reset.
[0086] In addition, it should be noted that Figure 3Based on the second switching circuit 122 shown in the figure, those skilled in the art may also replace the third transistor Q3 and the fourth transistor Q4 with NMOS transistors, or use a PMOS transistor or a PNP transistor as the third transistor Q3 and the fourth transistor Q4, and make adaptive adjustments to the connection positions of the pull-up resistor and the pull-down resistor in the circuit. The embodiments of the present utility model are suitable for these Figure 3 The basic transformation alternatives will not be described in detail one by one.
[0087] Therefore, the second switching circuit 122 is electrically connected to the main control device 20. After receiving the control signal transmitted from the main control device 20, the second switching circuit 122 can use the cooperation of the third transistor Q3, the fourth transistor Q4 and the corresponding pull-up resistor and pull-down resistor to control the level of the interface configuration pin CFG and the reset pin RESET in the upstream interface conversion circuit 10, and complete the switching adjustment of the transmission mode of the second switching circuit 122.
[0088] Optionally, refer to Figure 4 , the interface expansion circuit also includes a connector 13 and an electrostatic protection device 14;
[0089] The connector 13 is electrically connected to the downstream interface 112 , and the electrostatic protection device 14 is disposed between the connector 13 and the downstream interface 112 .
[0090] Specifically, if Figure 4 As shown in the figure, in one implementation of the embodiment of the utility model, a DB9 nine-pin connector can be used as a connector 13 connected to the downstream interface 112 to achieve plugging with the peripheral device 30, and an electrostatic protection device 14 can be set on the signal transmission line between the connector 13 and the downstream interface 112 to prevent the interface expansion circuit or the electrostatic current of the peripheral device 30 from damaging the interface expansion circuit, thereby reducing the risk of data transmission failure. The electrostatic protection device 14 used in the embodiment of the utility model can be one or more combinations of TVS diodes, overvoltage protectors, gas discharge tubes, etc. The embodiment of the utility model does not limit the specific type of the electrostatic protection device 14.
[0091] In addition, based on the interface expansion circuit disclosed in any of the above embodiments, it can be processed and designed on a circuit board to present an interface expansion device in the form of a board structure. This interface expansion device can be connected to the computer motherboard interface to expand the interface of the computer motherboard. Due to the simplification of the interface expansion circuit, the structure size of this interface expansion device can be reduced, and its power consumption and cost can be reduced.
[0092] In addition, the interface expansion circuit disclosed in any of the above embodiments can also be directly designed and processed on the mainboard and integrated with the mainboard circuit, so that the mainboard itself can expand more peripheral interfaces with lower power consumption and material cost.
[0093] The utility model also discloses an electronic device, which includes the interface expansion circuit disclosed in any of the above embodiments of the utility model. When the above interface expansion circuit is applied to electronic devices such as home computers, industrial computers or various embedded devices, it helps to reduce the power consumption and cost of the electronic device interface expansion.
[0094] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0095] It should be understood by those skilled in the art that, although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.
[0096] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.
[0097] The above is a detailed introduction to an interface expansion circuit, an interface expansion device, a mainboard and an electronic device provided by the utility model. Specific examples are used in this article to illustrate the principle and implementation mode of the utility model. The description of the above embodiments is only used to help understand the method and core idea of the utility model. At the same time, for general technical personnel in this field, according to the idea of the utility model, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as a limitation on the utility model.
Claims
1. An interface expansion circuit, characterized in that: The interface expansion circuit includes an uplink interface conversion circuit, a downlink interface driving circuit and a switching circuit; The uplink interface conversion circuit has an uplink interface and a plurality of first transfer interfaces, wherein the uplink interface is used to be electrically connected to an uplink main control device; The downstream interface driving circuit has a second adapter interface and a downstream interface, wherein the downstream interface is used to be electrically connected to a downstream peripheral device; The switching circuit has a signal input pin and a signal output pin, wherein the signal input pin of the switching circuit is used to be electrically connected to an uplink master control device; Each of the first adapter interfaces is electrically connected to a second adapter interface of the downstream interface driving circuit, the signal output pin of the switching circuit is electrically connected to the upstream interface conversion circuit and the downstream interface driving circuit, and the switching circuit controls the downstream interface driving circuit to transmit data in a plurality of different interface modes, wherein the downstream interface and the upstream interface support different transmission protocols.
2. The interface expansion circuit according to claim 1, characterized in that: The downlink interface driving circuit is a half-duplex asynchronous serial communication transceiver, and the half-duplex asynchronous serial communication transceiver has a first mode configuration pin and a second mode configuration pin; Some signal output pins of the switching circuit are electrically connected to the first mode configuration pin and the second mode configuration pin.
3. The interface expansion circuit according to claim 2, characterized in that: The switching circuit includes a first switching circuit; The signal output pin of the first switching circuit is electrically connected to the first mode configuration pin and the second mode configuration pin, and is used to control the downstream interface driving circuit to switch to a target interface mode.
4. The interface expansion circuit according to claim 3, characterized in that: The first switching circuit includes a first transistor, a first pull-up resistor, a first pull-down resistor, a second transistor, a second pull-up resistor, and a second pull-down resistor; The input pin of the first transistor is electrically connected to the first pull-up resistor, and the node between the input pin of the first transistor and the first pull-up resistor forms a first signal output pin, and the first signal output pin is electrically connected to the first mode configuration pin; the output pin of the first transistor is grounded; the control pin of the first transistor is electrically connected to the first pull-down resistor, and the node between the control pin of the first transistor and the first pull-down resistor forms a first signal input pin, and the first signal input pin is used to be electrically connected to an upstream master control device; The input pin of the second transistor is electrically connected to the second pull-up resistor, and the node between the input pin of the second transistor and the second pull-up resistor forms a second signal output pin, and the second signal output pin is electrically connected to the second mode configuration pin; the output pin of the second transistor is grounded; the control pin of the second transistor is electrically connected to the second pull-down resistor, and the node between the control pin of the second transistor and the second pull-down resistor forms a second signal input pin, and the second signal input pin is used to be electrically connected to an upstream master control device.
5. The interface expansion circuit according to claim 3, characterized in that: The uplink interface conversion circuit is a conversion chip, and the conversion chip has an interface configuration pin and a reset pin; Some signal output pins of the switching circuit are electrically connected to the interface configuration pin and the reset pin, and are used to control the uplink interface conversion circuit to switch to a mode consistent with the downlink interface driving circuit.
6. The interface expansion circuit according to claim 5, characterized in that: The switching circuit further includes a second switching circuit; The signal output pin of the second switching circuit is electrically connected to the interface configuration pin and the reset pin, and is used to control the uplink interface conversion circuit to switch to a mode consistent with the downlink interface driving circuit.
7. The interface expansion circuit according to claim 6, characterized in that: The second switching circuit includes a third transistor, a third pull-up resistor, a fourth pull-up resistor and a fourth transistor; The input pin of the third transistor is electrically connected to the third pull-up resistor, and the node between the input pin of the third transistor and the third pull-up resistor forms a third signal output pin, and the third signal output pin is electrically connected to the interface configuration pin; the output pin of the third transistor is grounded; the control pin of the third transistor is electrically connected to the fourth pull-up resistor, and the node between the control pin of the third transistor and the fourth pull-up resistor forms a third signal input pin, and the third signal input pin is used to be electrically connected to an upstream master control device; The input pin of the fourth transistor forms a fourth signal output pin, and the fourth signal output pin is electrically connected to the reset pin; the output pin of the fourth transistor is grounded; the control pin of the fourth transistor forms a fourth signal input pin, and the fourth signal input pin is used to be electrically connected to the upstream master control device.
8. The interface expansion circuit according to any one of claims 1 to 7, characterized in that: The interface expansion circuit also includes a connector and an electrostatic protection device; The connector is electrically connected to the downstream interface, and the electrostatic protection device is arranged between the connector and the downstream interface.
9. An interface expansion device, characterized in that: The interface expansion device comprises the interface expansion circuit according to any one of claims 1 to 8.
10. A motherboard, characterized in that: The main board includes the interface expansion circuit according to any one of claims 1 to 8.
11. An electronic device, characterized in that: The electronic device comprises the interface expansion circuit according to any one of claims 1 to 8.