Semiconductor device structure

Abstract

A semiconductor device structure includes a substrate; and the isolation structures are positioned on the substrate and between two adjacent transistors. The isolation structure comprises a dielectric structure; and an insulating material under the dielectric structure. The insulating material includes an upper side portion including a first sidewall and an upper surface contact dielectric structure; and a bottom having a second sidewall wherein the substrate surrounds and contacts the second sidewall. The insulating material also includes an intermediate portion having a third sidewall between the first sidewall and the second sidewall. The semiconductor device structure also includes a dielectric material, a contact dielectric structure, a first sidewall, a third sidewall, and a substrate.

Description

Technical Field

[0001] The embodiments of the utility model relate to a semiconductor device structure, and more particularly to an isolation structure. Background Art

[0002] As the semiconductor industry progresses to nanometer technology process nodes for higher device density, higher performance, and lower cost, the development of multi-gate devices such as fin field effect transistors and all-around gate transistors faces challenges in manufacturing and design. In order to continue to reduce the size and increase the density of multi-gate devices in advanced technology nodes, the gate pitch must continue to decrease. Various solutions such as poly on diffusion edge (PODE) and continuous poly on diffusion edge (CPODE) are used to reduce the gate pitch and avoid leakage current between transistors. However, these solutions cannot provide the device density levels, unit isolation, and device performance required for significantly smaller circuits and devices.

[0003] Therefore, there is an urgent need to improve the processing and manufacturing methods of integrated circuits. Utility Model Content

[0004] The purpose of the present invention is to provide a semiconductor device structure to solve at least one of the above problems.

[0005] One embodiment is a semiconductor device structure, including: a first source / drain epitaxial structure formed on a substrate; a second source / drain epitaxial structure formed on the substrate and adjacent to the first source / drain structure; two or more first semiconductor layers located between the first source / drain epitaxial structure and the second source / drain epitaxial structure; a gate layer surrounding a portion of one of the plurality of first semiconductor layers; and an isolation structure located on the substrate and adjacent to the second source / drain epitaxial structure, and the isolation structure includes: a dielectric structure; a dielectric material contacting an exposed surface of the dielectric structure; and a shallow trench isolation located below the dielectric structure, and the shallow trench isolation includes: a first portion adjacent to the dielectric structure, and the dielectric material surrounding and contacting the first portion; and a second portion located below the first portion, and the substrate surrounding and contacting the second portion.

[0006] According to one embodiment of the utility model, it also includes: a third source / drain epitaxial structure formed on the substrate; a fourth source / drain epitaxial structure formed on the substrate and adjacent to the third source / drain epitaxial structure; and two or more second semiconductor layers located between the third source / drain structure and the fourth source / drain structure; wherein the gate layer surrounds a portion of one of the plurality of second semiconductor layers, and the third source / drain structure and the second source / drain structure are separated by the isolation structure.

[0007] According to one embodiment of the present invention, the first portion of the shallow trench isolation has a first component, and the diameter of the first component gradually increases along a direction away from the dielectric structure.

[0008] According to one embodiment of the present invention, the first portion of the shallow trench isolation has a second component located below the first component, and the diameter of the second component gradually decreases along a direction away from the dielectric structure.

[0009] According to one embodiment of the present invention, the first portion of the shallow trench isolation has a curved surface profile.

[0010] According to one embodiment of the present invention, a first radius of the first curvature of the side wall of the first component is greater than a second radius of the second curvature of the side wall of the second component.

[0011] According to one embodiment of the present invention, the first component has a first height, the shallow trench isolation has a second height, and the ratio of the first height to the second height is 1:1.5 to 1:2.5.

[0012] According to one embodiment of the present invention, the lowest point of an interface defined by the dielectric material and the substrate is lower than the lower surface of the second portion.

[0013] According to one embodiment of the present invention, the second portion has a first height, the shallow trench isolation has a second height, and a ratio of the first height to the second height is 1:10 to 1:20.

[0014] According to one embodiment of the present invention, the dielectric structure further includes: a dielectric core material; a liner surrounding and contacting at least three surfaces of the dielectric core material; and a dielectric cover located above the dielectric core material and the upper surface of the liner and contacting the dielectric core material and the upper surface of the liner. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figures 1 to 17 2 is a perspective view of various stages in the fabrication of a semiconductor device structure in some embodiments.

[0016] Fig.18A and FIG. 18B to FIG. 25A and Fig.25B In some embodiments, various stages of manufacturing a semiconductor device structure are as follows: Fig.17 Section view of section lines AA and BB. Section view of section lines AA and BB.

[0017] Fig. 21C for Fig. 21B A partial enlarged view of a semiconductor device structure showing the insulating material of the isolation region after a fin cutting process (or a wafer cutting process).

[0018] The reference numerals are as follows:

[0019] AA,BB: Section line

[0020] C: Dashed circle

[0021] D3: Transverse diameter

[0022] H1,H2,H3,H4,H5,H6: Height

[0023] W1,W2: Width

[0024] 100:Semiconductor device structure

[0025] 101:Substrate

[0026] 102a, 102b: substrate part

[0027] 104: Semiconductor layer stack

[0028] 106: first semiconductor layer

[0029] 107:Ibe

[0030] 108: Second semiconductor layer

[0031] 110,1108,1702:Mask structure

[0032] 112,1110: oxygen layer

[0033] 114,1112,1606: Nitrogen-containing layer

[0034] 202a,202b: Fins

[0035] 204,502,806: Groove

[0036] 302,304,702: Gasket

[0037] 402: Insulation material

[0038] 402a: upper part

[0039] 402b: Middle part

[0040] 402c,908,2104:Bottom

[0041] 504,802,804,2103: Upper surface

[0042] 602: Coating

[0043] 704: Dielectric core material

[0044] 904: Dielectric cover

[0045] 906: Dielectric structure

[0046] 1102: Sacrificial gate stack

[0047] 1104: Sacrificial gate dielectric layer

[0048] 1106: Sacrificial gate layer

[0049] 1202: Spacer

[0050] 1204: Part 1

[0051] 1206: Part 2

[0052] 1302: Gap

[0053] 1402: Dielectric spacer

[0054] 1502: Source / drain epitaxial structure

[0055] 1602: Contact Etch Stop Layer

[0056] 1604: Interlayer dielectric layer

[0057] 1704: Mask layer

[0058] 1704'; Patterned mask layer

[0059] 1706: Photoresist layer

[0060] 1708: Bottom

[0061] 1710: Middle layer

[0062] 1712: Photosensitive top layer

[0063] 1802, 2002, 2102, 2302: Open

[0064] 1804: Quarantine

[0065] 1806: Active area

[0066] 2101: Depletion Zone

[0067] 2105: Accumulation Zone

[0068] 2106: Lower surface

[0069] 2108,2110,2112: Side wall

[0070] 2114: Lowest point

[0071] 2148,2180: highest point

[0072] 2150: point

[0073] 2201: Dielectric Materials

[0074] 2202: Isolation Structure

[0075] 2203: Interface

[0076] 2401: Replacement gate structure

[0077] 2402: Interface layer

[0078] 2404: Gate dielectric layer

[0079] 2406: Gate layer

[0080] 2502: Silicide layer

[0081] 2504: Self-aligned contact layer

[0082] 2506:Contact DETAILED DESCRIPTION

[0083] The following detailed description may be accompanied by the accompanying drawings to facilitate understanding of various aspects of the present invention. It is worth noting that the various structures are only for illustrative purposes and are not drawn to scale, as is common in the industry. In fact, the dimensions of the various structures may be increased or decreased arbitrarily for the sake of clarity.

[0084] The following disclosure provides many different embodiments or examples to implement different structures of the present invention. The following specific components and arrangement embodiments are used to simplify the present invention but are not intended to limit the present invention. For example, the description of forming a first component on a second component includes direct contact between the two, or there are other additional components between the two instead of direct contact. In addition, multiple examples of the present invention may use repeated numbers and / or symbols to simplify and clarify the description, but these repetitions do not mean that the same corresponding relationship exists between the components with the same number in multiple embodiments.

[0085] In addition, spatially relative terms such as "below," "beneath," "below," "above," "above," or similar terms may be used to simplify the description of the relative relationship of one element to another element in a diagram. Spatially relative terms may be extended to elements used in other orientations, not limited to the orientation shown in the diagram. Elements may also be rotated 90 degrees or other angles, so directional terms are only used to describe the orientation shown in the diagram.

[0086] Although the embodiments of the present invention are described with nanosheet field effect transistors, some embodiments of the present invention can be used in other processes and / or other devices, such as planar field effect transistors, fin field effect transistors, horizontal fully wrapped gate field effect transistors, vertical fully wrapped gate field effect transistors, or other suitable devices. Those skilled in the art should understand that other adjustments also fall within the scope of the embodiments of the present invention.

[0087] Figures 1 to 25B is an exemplary process for manufacturing the semiconductor device structure 100 in some embodiments. Figures 1 to 25B Additional steps may be provided before, during, and after the processes shown, and additional embodiments of the method may replace or omit some of the steps described below. In addition, the order of the steps / processes may be reversed.

[0088] Figures 1 to 17 FIG. 1 is a cross-sectional view of various stages of manufacturing a semiconductor device structure 100 in some embodiments. Figure 1 As shown, semiconductor layer stack 104 is formed on substrate 101. Substrate 101 may be a semiconductor substrate. In some embodiments, substrate 101 includes a single crystal semiconductor layer at least on the surface of substrate 101. Substrate 101 may include a single crystal semiconductor material, such as but not limited to silicon, germanium, silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide, or indium phosphide. In one embodiment, substrate 101 is composed of silicon. In some embodiments, substrate 101 is a silicon-on-insulator substrate having an insulating layer (not shown) between two silicon layers to improve performance. In one embodiment, the insulating layer is an oxygen-containing layer.

[0089] The substrate 101 may include various regions doped with impurities, such as dopants with p-type or n-type impurities. For example, the dopant may be boron for a p-type field effect transistor or phosphorus for an n-type field effect transistor, depending on the circuit design.

[0090] The semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are composed of semiconductor materials with different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 is composed of silicon, and the second semiconductor layer 108 is composed of silicon germanium. In some embodiments, the first semiconductor layer 106 may be composed of silicon germanium with a first germanium concentration range, and the second semiconductor layer 108 may be composed of silicon germanium with a second germanium concentration range, and the second germanium concentration range is less than or greater than the first germanium concentration range. In some embodiments, the semiconductor layer stack 104 includes the staggered first semiconductor layer 106 and the second semiconductor layer 108. The first semiconductor layer 106 or a portion thereof may form a nanosheet channel of the semiconductor device structure 100 in a subsequent stage. The semiconductor device structure 100 may include a nanosheet transistor. The term "nanosheet" described herein may refer to any material portion of nanometer size or even micrometer size, which has an elongated shape, regardless of the cross-sectional shape of the portion. Thus, this term may refer to elongated material portions having circular and substantially circular cross-sections, or beam-shaped or rod-shaped material portions having cylindrical or substantially rectangular cross-sections. The gate layer may surround the nanosheet channel of the semiconductor device structure 100. The nanosheet transistor may be considered a nanowire transistor, a fully wrapped gate transistor, a multi-bridge channel transistor, or any transistor having a gate layer surrounding the channel. The first semiconductor layer 106 is used to define the channel of the semiconductor device structure 100, as described below. In some embodiments, the first semiconductor layer 106 and the second semiconductor layer 108 may be replaced by a single semiconductor material connected to the substrate 101, and the device is a fin field effect transistor.

[0091] As described in detail below, the first semiconductor layer 106 can serve as channels for the semiconductor device structure 100, and the thickness of the first semiconductor layer 106 can be selected based on device performance considerations. In some embodiments, the thickness of each of the first semiconductor layers 106 is about 6 nm to about 12 nm. Finally, the second semiconductor layer 108 can be removed to define the vertical distance between adjacent channels used by the semiconductor device structure 100, and the thickness of the second semiconductor layer 108 can be selected based on device performance considerations. In some embodiments, the thickness of each of the second semiconductor layers 108 is about 2 nm to about 6 nm. Although Figure 1 Three first semiconductor layers 106 and three second semiconductor layers 108 are shown in an alternating arrangement, but it should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, depending on the predetermined number of nanosheet channels used for each field effect transistor. For example, the number of first semiconductor layers 106 (i.e., the number of channels) can be between 2 and 8.

[0092] The first semiconductor layer 106 and the second semiconductor layer 108 may be formed by any suitable deposition process such as epitaxy. For example, the epitaxial growth method of the semiconductor layer stack 104 may be molecular beam epitaxy, metal organic chemical vapor deposition and / or other suitable epitaxial growth processes.

[0093] The mask structure 110 is formed on the semiconductor layer stack 104. The mask structure 110 may include an oxygen-containing layer 112 and a nitrogen-containing layer 114. The oxygen-containing layer 112 may be a pad oxide layer such as a silicon oxide layer. The nitrogen-containing layer 114 may be a pad nitride layer such as silicon nitride. The mask structure 110 may be formed by a suitable deposition process such as a chemical vapor deposition process.

[0094] exist Figure 2 In some embodiments, the fins 202a and 202b each include a substrate portion 102a and 102b formed from the substrate 101, a portion of the semiconductor layer stack 104, and a portion of the mask structure 110. The fins 202a and 202b may also each include a well 107 (having n-type or p-type dopants) located at or near the interface between the bottom-most second semiconductor layer 108 and the substrate portions 102a and 102b. The method for making the fins 202a and 202b may adopt a suitable process, including a double patterning or a multiple patterning process. In general, the double patterning or multiple patterning process combines photolithography and self-alignment processes, and the pattern pitch produced is smaller than the pattern pitch obtained by using a single direct photolithography process. For example, one embodiment forms a sacrificial layer on the substrate and uses a photolithography process to pattern the sacrificial layer. A self-alignment process is used to form spacers along the side of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers or cores may be used to etch the semiconductor layer stack 104 and the substrate 101 to pattern the fins 202a and 202b. The etching process may include dry etching, wet etching, reactive ion etching, and / or other suitable processes. Figure 2 Two fins are shown, but the number of fins is not limited to two. In some embodiments, three or more fins are configured along the X direction, such as Fig.18A and FIG. 18B to FIG. 25A and Fig.25B shown.

[0095] In some embodiments, the method for making the fins 202a and 202b may adopt suitable processes, including photolithography and etching processes. The photolithography process may include forming a photoresist layer (not shown) on the mask structure 110, exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a patterned photoresist. In some embodiments, the method of patterning the photoresist to form a patterned photoresist may adopt an electron beam lithography process. The patterned photoresist can then be used to protect the area of ​​the substrate 101 and the layers formed thereon, and the etching process forms the groove 204 in the unprotected area and passes through the mask structure 110 and the semiconductor layer stack 104 to the substrate 101 to leave the fins 202a and 202b extending upward from the substrate 101. Dry etching such as reactive ion etching, wet etching and / or a combination of the above can be used to etch the groove 204.

[0096] exist Figure 3 In the embodiment, the liner 304 is formed on the substrate 101 and the fins 202a and 202b. In some embodiments, the liner 302 may be formed on the substrate 101 and the fins 202a and 202b as appropriate, and the liner 304 may be formed on the liner 302 as appropriate. The composition of the liner 304 may be a semiconductor material such as silicon. In some embodiments, the composition of the liner 304 and the substrate 101 is the same material. In some embodiments, the liners 302 and 304 may be formed as appropriate. In these examples, the subsequent insulating material 402 directly contacts the substrate portions 102a and 102b. The composition of the liner 302 formed as appropriate may be an oxygen-containing material such as an oxide. The liner 304 may be a compliant layer, and the method of forming it may be a compliant process such as an atomic layer deposition process. The term "compliant" described herein is used to simplify the description of layers having substantially the same thickness in different regions. The liner 302 may be a compliant layer, and its formation method may be a compliant process such as an atomic layer deposition process.

[0097] exist Figure 4 In the embodiment, an insulating material 402 is formed on the substrate 101. The insulating material 402 fills the groove 204 ( Figure 3 ). An insulating material 402 may be formed on the substrate 101 so that the fins 202a and 202b are buried in the insulating material 402. Then, a planarization step such as a chemical mechanical polishing process and / or an etch-back process is performed to expose the tops of the fins 202a and 202b (such as the liner 304) from the insulating material 402. Figure 4As shown. The composition of the insulating material 402 can be an oxygen-containing material (such as silicon oxide or fluorosilicate glass), a nitrogen-containing material (such as silicon nitride, silicon oxynitride, silicon carbonitride oxide, silicon carbonitride), a low dielectric constant dielectric material, or any suitable dielectric material. The insulating material 402 can be formed by any suitable method, such as low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, or flowable chemical vapor deposition.

[0098] exist Figure 5 , a portion of the insulating material 402 between the adjacent fins 202a and 202b is removed to recess the insulating material 402 to form a trench 502. The trench 502 may be formed by any suitable removal process such as dry etching or wet etching, which can selectively remove the insulating material 402 without removing the semiconductor material of the liner 304. The recessed insulating material 402 may be a shallow trench isolation. The upper surface 504 of the insulating material 402 may be flush with or lower than the surface of the second semiconductor layer 108 contacting the substrate portions 102a and 102b of the substrate 101.

[0099] exist Figure 6 In the embodiment, the coating 602 is formed on the liner 304 ( Figure 5 ) on the exposed surface of the semiconductor layer stack 104. The optional liner 302 may be omitted for clarity of the drawing. When the cap layer 602 is formed, the liner 304 may diffuse into the cap layer 602. Therefore, in some embodiments where the optional liner 302 is not present, the cap layer 602 contacts the semiconductor layer stack 104, such as Figure 6 As shown. In some embodiments, the capping layer 602 includes a semiconductor material. The capping layer 602 may be grown on a semiconductor material but not on a dielectric material. For example, the capping layer 602 may include silicon germanium and grow on the silicon of the liner 304 but not on the dielectric material of the insulating material 402. In some embodiments, the method of forming the capping layer 602 may be to first form a semiconductor layer on the liner 304 and the insulating material 402, and then etch back to remove the portion of the semiconductor layer on the insulating material 402. In some embodiments, the capping layer 602 and the second semiconductor layer 108 include the same material with the same etching selectivity. For example, the capping layer 602 and the second semiconductor layer 108 may both include silicon germanium. The capping layer 602 and the second semiconductor layer 108 may then be removed to create space for the gate layer.

[0100] exist Figure 7In the embodiment, the liner 702 is formed on the upper surface 504 of the cap layer 602 and the insulating material 402. The liner 702 may include a low dielectric constant dielectric material (e.g., a material with a dielectric constant less than 7), such as silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbide, or silicon oxycarbonitride. The liner 702 may be formed by a compliant process such as an atomic layer deposition process. The thickness of the liner 702 may be about 1 nm to about 6 nm. The liner 702 may serve as a shell layer to protect the flowable oxide material ( Figure 6 ).

[0101] Then, a dielectric core material 704 is formed in the trench 502 ( Figure 6 ) and on the pad 702, such as Figure 7 As shown. The liner 702 surrounds and contacts at least three surfaces of the dielectric core material 704. The dielectric core material 704 may be an oxygen-containing material such as an oxide formed by a flowable chemical vapor deposition. The dielectric constant of the oxygen-containing material may be less than about 7, such as less than about 3. The width of the dielectric core material 704 along the X direction may be defined by the width of the trench 502 and the thickness of the liner 702. In some embodiments, the width of the dielectric core material 704 is about 8nm to about 30nm. A planarization process such as a chemical mechanical polishing process may be performed to remove portions of the liner 702 and the dielectric core material 704 on the fins 202a and 202b. After the planarization process, a portion of the capping layer 602 on the nitrogen-containing layer 114 may be exposed.

[0102] exist Figure 8 In some embodiments, the liner 702 and the dielectric core material 704 are recessed to the height of the topmost first semiconductor layer 106. For example, in some embodiments, after the recessing process, the upper surface 802 of the dielectric core material 704 can be substantially flush with the upper surface 804 of the topmost first semiconductor layer 106. The upper surface 804 of the topmost first semiconductor layer 106 can contact the mask structure 110, such as contacting the oxygen-containing layer 112. The liner 702 can be recessed to the height of the dielectric core material 704. The liner 702 and the dielectric core material 704 can be recessed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a first etching process can be performed to recess the dielectric core material 704, followed by a second etching process to recess the liner 702. The etching process can be a selective etching process that does not remove the semiconductor material of the cap layer 602. The recessing process can form a trench 806 between the fins 202a and 202b.

[0103] exist Fig. 9 In the embodiment, the dielectric cap 904 is formed in the groove 806 ( Figure 8) and on the upper surface of the dielectric core material 704 and the liner 702. The dielectric cap 904 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, tantalum nitride, aluminum zirconium oxide, hafnium oxide, or other suitable dielectric materials. The dielectric cap 904 may be formed by any suitable process, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, flowable chemical vapor deposition, or atomic layer deposition. The thickness of the dielectric cap 904 may be about 5nm to about 20nm. A planarization process such as chemical mechanical polishing is then performed to expose the nitrogen-containing layer 114 of the mask structure 110. The planarization process may remove portions of the cap 602 and the dielectric cap 904 on the mask structure 110. The liner 702, the dielectric core material 704, and the dielectric cap 904 may be collectively considered as a dielectric structure (or hybrid fin) 906. The dielectric structure 906 includes a bottom 908 having a shell such as the liner 702 and a core such as the dielectric core material 704. The dielectric structure may further include a top such as a dielectric cap 904. The dielectric structure 906 may serve as a dielectric fin to separate adjacent source / drain epitaxial structures 1502 ( Fig.15 ).

[0104] exist Fig.10 602, and the mask structure 110 is removed. The capping layer 602 may be recessed by any suitable process, such as dry etching, wet etching, or a combination thereof. The recessing process may be controlled so that the remaining capping layer 602 is substantially at the same height as the upper surface 804 of the topmost first semiconductor layer 106 in the semiconductor layer stack 104. The etching process may be a selective etching process that does not remove the dielectric cap 904. The step of removing the mask structure 110 may be any suitable process, such as dry etching, wet etching, or a combination thereof. Removing the mask structure 110 may expose the upper surface 804 of the topmost first semiconductor layer 106 in the semiconductor layer stack 104.

[0105] The capping layer 602 and the mask structure 110 are removed, resulting in the top of the dielectric structure 906 (such as the dielectric cap 904) having a height H1 along the Z direction. The height H1 may be about 6 nm to about 25 nm. The dielectric cap 904 extends above the plane defined by the upper surface 804 by a height H1 to separate or cut the adjacent gate layer ( Fig.25B ).

[0106] exist Fig.11, one or more sacrificial gate stacks 1102 are formed on the semiconductor device structure 100. The sacrificial gate stack 1102 may include a sacrificial gate dielectric layer 1104, a sacrificial gate layer 1106, and a mask structure 1108. The sacrificial gate dielectric layer 1104 may include one or more layers of dielectric materials such as silicon oxide, silicon nitride, high dielectric constant dielectric materials and / or other suitable dielectric materials. In some embodiments, the material of the sacrificial gate dielectric layer 1104 is different from the material of the dielectric cap 904. In some embodiments, the deposition method of the sacrificial gate dielectric layer 1104 may be a chemical vapor deposition process, a sub-pressure chemical vapor deposition process, a flowable chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or other suitable processes. The sacrificial gate layer 1106 may include polysilicon. The mask structure 1108 may include an oxygen-containing layer 1110 and a nitrogen-containing layer 1112. In some embodiments, the sacrificial gate layer 1106 and the mask structure 1108 may be formed by a variety of layer deposition processes, such as chemical vapor deposition (including low pressure chemical vapor deposition and plasma assisted chemical vapor deposition), physical vapor deposition, thermal oxidation, electron beam evaporation, other suitable deposition techniques, or combinations thereof.

[0107] The sacrificial gate stack 1102 may be formed by first depositing a blanket layer of a sacrificial gate dielectric layer 1104, a sacrificial gate layer 1106, and a mask structure 1108, followed by patterning and etching processes. For example, the patterning process includes a photolithography process (such as photolithography or electron beam lithography), which may further include photoresist coating such as spin coating, soft baking, alignment of a photomask, exposure, post-exposure baking, developing the photoresist, rinsing, drying (such as spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (such as reactive ion etching), wet etching, other etching methods, and / or combinations thereof. By patterning the sacrificial gate stack 1102, the semiconductor layer stack 104 of the fins 202a and 202b on both sides of the sacrificial gate stack 1102 may be partially exposed. Although Fig.11 Two sacrificial gate stacks are shown, the number of sacrificial gate stacks 1102 is not limited to two. In some embodiments, more than two sacrificial gate stacks 1102 may be configured along the Y direction.

[0108] exist Fig.12, spacers 1202 are formed on the sidewalls of the sacrificial gate stack 1102. The spacers 1202 may be formed by first depositing a compliant layer and then etching back the compliant layer to form the sidewall spacers 1202. For example, the spacer material layer may be conformally located on the exposed surface of the semiconductor device structure 100. The conformal spacer material layer may be formed by an atomic layer deposition process. Reactive ion etching may then be used to anisotropically etch the spacer material layer. During the anisotropic etching process, the main spacer material layer is removed from horizontal surfaces (such as the top of the fins 202a and 202b, the cap layer 602, and the dielectric cap 904), and the spacers 1202 are retained on vertical surfaces (such as the sidewalls of the sacrificial gate stack 1102). The spacers 1202 may be composed of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride carbonitride, and / or combinations thereof. In some embodiments, the spacer 1202 includes multiple layers, such as a main spacer wall, a backing layer, and the like.

[0109] Then, one or more suitable etching processes such as dry etching, wet etching, or a combination thereof are used to selectively recess the exposed portions of the sacrificial gate stack 1102 and the fins 202a and 202b, the exposed portions of the capping layer 602, and the exposed portions of the dielectric cap 904 that are not covered by the spacer 1202. In some embodiments, the exposed portions of the semiconductor layer stack 104 of the fins 202a and 202b are removed to expose portions of the substrate portions 102a and 102b, respectively. Fig.12 As shown, the exposed portions of the fins 202a and 202b may be recessed to or below the upper surface 504 ( Figure 6 The recessing process may include an etching process that may recess the exposed portions of the fins 202 a and 202 b and the exposed portions of the capping layer 602 .

[0110] In some embodiments, the etching process may reduce the height of the exposed top portion of the dielectric structure 906 (eg, the dielectric cap 904) from a height H1 to a height H2. Fig.12 Therefore, the sacrificial gate stack 1102 and the first portion 1204 of the dielectric cap 904 below the spacer 1202 have a height H1, and the source / drain epitaxial structure 1502 ( Fig.15 ) has a second portion 1206 of the dielectric cover 904 having a height H2, and the height H2 is less than the height H1.

[0111] At this stage, the end portions of the sacrificial gate stack 1102 and the semiconductor layer stack 104 under the spacers 1202 have substantially smooth surfaces, which may be flush with the corresponding spacers 1202. In some embodiments, the end portions of the sacrificial gate stack 1102 and the semiconductor layer stack 104 under the spacers 1202 may be slightly horizontally etched.

[0112] exist Fig.13 , the edge portions of the second semiconductor layer 108 and the edge portions of the capping layer 602 are removed to form the gap 1302. In some embodiments, the method of removing the second semiconductor layer 108 and the portion of the capping layer 602 may be a selective wet etching process, which does not remove the first semiconductor layer 106. For example, in the case where the second semiconductor layer 108 is composed of silicon germanium and the first semiconductor layer 106 is composed of silicon, a selective wet etching process containing a mixture of ammonia and hydrogen peroxide may be used.

[0113] exist Fig.14 In the embodiment, dielectric spacer 1402 is formed in gap 1302 ( Fig.13 ). In some embodiments, the dielectric spacer 1402 may be composed of a dielectric material with a low dielectric constant such as silicon oxynitride, silicon carbon nitride, silicon oxycarbide, silicon carbon oxynitride, or silicon nitride. In some embodiments, the dielectric spacer 1402 may be formed by first using a compliant deposition process such as atomic layer deposition to form a compliant dielectric layer, and then removing a portion of the compliant dielectric layer outside the dielectric spacer 1402 by anisotropic etching. During the anisotropic etching process, the first semiconductor layer 106 and the spacer 1202 may protect the dielectric spacer 1402. In some embodiments, the dielectric spacer 1402 may be flush with the spacer 1202 along the Z direction.

[0114] exist Fig.15 , a source / drain epitaxial structure 1502 is formed on substrate portions 102a and 102b of fins 202a and 202b. The source / drain epitaxial structure 1502 may include one or more layers of silicon, silicon phosphide, silicon carbide, or silicon carbon phosphide for n-type field effect transistors, or one or more layers of silicon, silicon germanium, or germanium for p-type field effect transistors. The source / drain epitaxial structure 1502 may grow vertically and horizontally from substrate portions 102a and 102b to form crystal planes that may correspond to crystal planes of the material used for substrate portions 102a and 102b. The source / drain epitaxial structure 1502 may be formed by an epitaxial growth method, such as chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. Once the source / drain epitaxial structure 1502 is formed, it contacts the first semiconductor layer 106 and the dielectric spacer 1402 ( Fig.14). The source / drain epitaxial structure 1502 may represent a source / drain region. For example, one of a pair of source / drain epitaxial structures 1502 is located on one side of the sacrificial gate stack 1102 and may be a source region, while the other of a pair of source / drain epitaxial structures 1502 is located on the other side of the sacrificial gate stack 1102 and may be a drain region. A pair of source / drain epitaxial structures 1502 includes a source epitaxial structure and a drain epitaxial structure connected by a channel (i.e., the first semiconductor layer 106). In the embodiments of the present invention, the terms source and drain may be used interchangeably, and their structures are substantially the same.

[0115] exist Fig.16 In the embodiment of the present invention, the contact etch stop layer 1602 can be formed on the source / drain epitaxial structure 1502, the dielectric structure 906, and the adjacent spacer 1202. The contact etch stop layer 1602 can include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, the like, or a combination thereof. The contact etch stop layer 1602 can be formed by chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. In some embodiments, the contact etch stop layer 1602 is a compliant layer formed by an atomic layer deposition process.

[0116] An interlayer dielectric layer 1604 is then formed on the contact etch stop layer 1602. The material used for the interlayer dielectric layer 1604 may include an oxide of tetraethoxysilane, undoped silicate glass, doped silicon oxide (such as borophosphosilicate glass, fluorosilicate glass, phosphosilicate glass, or borosilicate glass) and / or other suitable dielectric materials. The deposition method of the interlayer dielectric layer 1604 may be a plasma-assisted chemical vapor deposition process or other suitable deposition technology. In some embodiments, after forming the interlayer dielectric layer 1604, a thermal process may be performed on the semiconductor device structure 100 to anneal the interlayer dielectric layer 1604. A planarization process (such as chemical mechanical polishing) may then be performed to expose the sacrificial gate layer 1106, such as Fig.16 The planarization process removes the interlayer dielectric layer 1604 and the contact etch stop layer 1602 located on the sacrificial gate stack 1102. The planarization process can also remove the mask structure 1108 ( Fig.15 The interlayer dielectric layer 1604 may be recessed to be lower than the upper surface of the sacrificial gate layer 1106, and a nitrogen-containing layer 1606 such as silicon nitride, silicon carbonitride, or titanium nitride may be formed on the recessed interlayer dielectric layer 1604. Fig.16 In the subsequent etching process, the nitrogen-containing layer 1606 can protect the interlayer dielectric layer 1604. After the planarization process, the nitrogen-containing layer 1606, the contact etch stop layer 1602, the spacer 1202, and the upper surface of the sacrificial gate layer 1106 can be coplanar.

[0117] exist Fig.17 1, a mask structure 1702 is formed on the upper surface of the nitrogen-containing layer 1606, the contact etch stop layer 1602, the spacer 1202, and the sacrificial gate layer 1106. The mask structure 1702 may include a mask layer 1704 and a photoresist layer 1706. The mask layer 1704 may be any suitable mask material. In some embodiments, the mask layer 1704 and the nitrogen-containing layer 1606 may be composed of the same material. The photoresist layer 1706 may be a single layer of photoresist or a three-layer photoresist. An exemplary three-layer photoresist may include a bottom layer 1708, an intermediate layer 1710 located on the bottom layer 1708, and a photosensitive top layer 1712 located on the intermediate layer 1710. The bottom layer 1708 may be a bottom anti-reflective coating, the middle layer 1710 may be a silicon-containing inorganic polymer to provide anti-reflective and / or hard mask properties for photolithography, and the photosensitive top layer 1712 may be a deep ultraviolet photoresist, argon fluoride photoresist and ultraviolet photoresist, electron beam photoresist, or ion beam photoresist.

[0118] Fig.18A and 18B to FIG. 25A to FIG. 25B In some embodiments, the various stages of manufacturing the semiconductor device structure 100 are respectively Fig.17 The side cross-sectional view of the section lines AA and BB of FIG. The section line AA is in the plane of the fin (such as the fin 202a) along the Y direction. The section line BB is in the plane of the sacrificial gate layer 1106 perpendicular to the section line AA and along the X direction. Fig.18A and FIG. 18B to FIG. 25A and Fig.25B In the various embodiments shown, the plurality of fins or sacrificial gate stacks 1102 are respectively along the X direction and the Y direction. Fig.18A and Fig.18B , the photosensitive top layer 1712 is patterned to form an opening 1802. To simplify the drawing, only one opening 1802 is shown. The patterned photosensitive top layer 1712 can be used as a mask in subsequent processes such as one or more photolithography processes to transfer the pattern (i.e., the opening 1802) in the photosensitive top layer 1712 to the intermediate layer 1710, the bottom layer 1708, and the mask layer 1704.

[0119] The opening 1802 defines an isolation region 1804 that is subsequently formed in the substrate portions 102a and 102b of the fins 202a and 202b. The isolation region 1804 may be located between adjacent active regions 1806. In other words, the active region 1806 may be located between the isolation regions 1804. The term "active region" may be viewed as an area where a transistor is formed. As described in detail below, the isolation region 1804 may be formed by performing a fin cutting process (or a sheet cutting process) and filling a dielectric layer into the fin cutting region (or sheet cutting region). The fin cutting process (or sheet cutting process) may be viewed as a continuous polycrystalline process on a diffusion edge. The term "diffusion edge" is equivalent to an active edge, which is an edge adjacent to an adjacent active region. The continuous polycrystalline process on a diffusion edge may be used to reduce the gate spacing, thereby increasing the density of multi-gate devices, and thereby increasing the device performance required for significantly reduced circuits and devices. In any case, the openings 1802 are configured at a location that may expose a portion of the sacrificial gate stack 1102 at a later stage. In some embodiments, the openings 1802 may each extend to overlap a single sacrificial gate stack 1102. In some embodiments, the openings 1802 may each extend to overlap a plurality of sacrificial gate stacks 1102 along the Y direction.

[0120] exist Fig.19A and Fig.19B In the embodiment of the present invention, the pattern (i.e., the opening 1802) in the photosensitive top layer 1712 is transferred to the mask layer 1704 to form a patterned mask layer 1704', and the bottom layer 1708, the middle layer 1710, and the photosensitive top layer 1712 are removed. The method of forming the patterned mask layer 1704' may be one or more photolithography processes. The one or more photolithography processes cause the opening 1802' to be formed in the patterned mask layer 1704' and expose a portion of the sacrificial gate layer 1106. The patterned mask layer 1704' is then used to protect the active area 1806 during the subsequent removal of the exposed sacrificial gate stack 1102 and the fin cutting process (or sheet cutting process).

[0121] exist Fig. 20A and Fig. 20B 1804, the exposed sacrificial gate stack 1102 is selectively removed to form an opening 2002. The opening 2002 exposes the sacrificial gate dielectric layer 1104 in the isolation region 1804. The patterned mask layer 1704' protects the sacrificial gate stack 1102 in the active region 1806. The method of removing the exposed sacrificial gate stack 1102 may adopt any suitable back etching process. The back etching process may be a selective etching process that removes the sacrificial gate stack 1102 but does not remove the spacer 1202 and the sacrificial gate dielectric layer 1104. In some embodiments, the sacrificial gate dielectric layer 1104 may also be removed.

[0122] exist Fig.21A and Fig. 21BIn the process, a fin cutting process (or a sheet cutting process) may be performed to remove the exposed sacrificial gate dielectric layer 1104, the first semiconductor layer 106, and the second semiconductor layer 108 of the isolation region 1804. The fin cutting process (or a sheet cutting process) uses a patterned mask layer 1704' as an etching mask. The fin cutting process (or a sheet cutting process) may be dry etching, reactive ion etching, and / or other suitable processes. A fin cutting process (or a sheet cutting process) is performed to selectively remove the exposed sacrificial gate dielectric layer 1104, the first semiconductor layer 106, and the second semiconductor layer 108, while the dielectric structure 906 remains substantially intact. In some embodiments, the fin cutting process is performed using reactive ion etching, and the physical bombardment of the bias power etching process may partially remove the dielectric cap 904. The first semiconductor layer 106 and the second semiconductor layer 108 are removed, resulting in an opening 2102 formed in the substrate portions 102a and 102b of the fins 202a and 202b of the isolation region 1804 between two adjacent active regions 1806. A dielectric material may be filled into the opening 2102 to form an isolation structure 2202 ( Fig.22A and Fig. 22B As described in detail below, the isolation structure 2202 can block leakage current paths in the well 107 between adjacent transistors in the active region 1806 .

[0123] In some embodiments, before the fin cutting process, the patterned mask layer 1704' may be exposed to a mixed gas containing methane and a diluent gas (such as argon and / or nitrogen) to form a protective layer (not shown) on the patterned mask layer 1704'. The protective layer can protect the patterned mask layer 1704' during the subsequent etching process to avoid or minimize damage. In these examples, the etching chemical used in the etching process may contain carbon tetrafluoride and argon to break through the protective layer and perform the fin cutting process.

[0124] Various embodiments perform a fin cutting process to make the bottom 2104 of the opening 2102 lower than the lower surface 2106 of the insulating material 402 (e.g., shallow trench isolation). Specifically, the substrate portions 102a and 102b of the fins 202a and 202b of the isolation region 1804 are recessed, leaving only a portion of the substrate portions 102a and 102b (e.g., silicon) on the bottom sidewall of the insulating material 402. In some embodiments, a fin cutting process (or a sheet cutting process) is performed to form a lateral recess on the upper sidewall of the insulating material 402. The lateral recess of the insulating material 402 ensures that the substrate portions 102a and 102b of the upper sidewall of the insulating material 402 are completely removed to create a larger space for the etching chemical to enter the opening 2102 and remove the substrate portions 102a and 102b on the insulating material 402 between the upper sidewall and the bottom sidewall of the insulating material 402. As a result, only a small portion of the substrate portions 102 a and 102 b remain at or near the bottom sidewall of the insulating material 402 .

[0125] Fig. 21C An enlarged view of a portion of the semiconductor device structure 100 is shown, showing the insulating material 402 of the isolation region after a fin cutting process (or a wafer cutting process). The insulating material 402 has an upper portion 402a adjacent to the dielectric structure, a bottom 402c extending to a depth in the substrate portions 102a and 102b and contacting the substrate portions 102a and 102b, and a middle portion 402b located between the upper portion 402a and the bottom 402c. An upper surface 2103 of the upper portion 402a contacts the bottom of the liner 702 of the dielectric structure 906. In some embodiments, the upper surface 2103 has a concave profile.

[0126] The upper portion 402a, the middle portion 402b and / or the bottom portion 402c may have a curved surface profile. In some embodiments, the sidewall 2112 of the bottom portion 402c has a first radius (R θ The side wall 2108 of the upper portion 402a has a second radius of curvature R2 (R θ ), which is greater than the first radius of curvature R1. The middle portion 402b of the insulating material 402 has a sidewall 2110, which can be substantially smooth. As shown, the sidewall 2108 of the upper portion 402a of the isolation region 1804 and the sidewall 2110 of the middle portion 402b do not have the substrate portions 102a and 102b, and the substrate portions 102a and 102b surround and contact the sidewall 2112 of the bottom 402c. The sidewalls 2108 and 2110 contact the dielectric material 2201 ( Fig. 22B ).

[0127] In some embodiments, the width W1 of the upper portion 402a of the insulating material 402 gradually increases from the side adjacent to the dielectric structure 906 to the side adjacent to the middle portion 402b. In one example, the width W1 of the upper portion 402a gradually increases along a direction away from the upper surface 2103 of the upper portion 402a. In some embodiments, the width W2 of the middle portion 402b gradually decreases from the side adjacent to the upper portion 402a to the side adjacent to the substrate portions 102a and 102b. In one example, the width W2 of the middle portion 402b gradually decreases along a direction away from the dielectric structure 906.

[0128] In some embodiments, the upper portion 402a has a height H3, the middle portion 402b has a height H4, and the bottom portion 402c has a height H5, the height H4 is greater than the height H3, and the height H5 is less than the height H3. The height H3 is measured from the highest point 2148 of the insulating material 402 to the point 2150 where the sidewall 2108 of the upper portion 402a contacts the sidewall 2110 of the middle portion 402b. The highest point 2148 of the insulating material 402 here can be regarded as the highest point of the unetched insulating material 402, which can be defined by the interface between the insulating material 402 and the liner 702 ( Fig.17 ). Height H5 can be measured from the highest point 2180 where substrate portions 102a and 102b contact insulating material 402 to the lower surface 2106 of insulating material 402. In other words, the depth of a portion of insulating material 402 (e.g., bottom portion 402c) is within substrate portions 102a and 102b, and the depth in some embodiments can correspond to height H5. In some embodiments, height H5 can be measured from the point where the thickness or lateral diameter D3 of substrate portions 102a and 102b on the sidewall of bottom portion 402c is about 1.5 nm to the lower surface 2106 of insulating material 402. Height H4 can be measured from point 2150 to the highest point 2180 where substrate portions 102a and 102b contact insulating material 402.

[0129] In some embodiments, the height H3 may be about 20 nm to about 40 nm (e.g., about 30 nm), and the height H5 may be about 5 nm to about 10 nm (e.g., about 6 nm). The height H6 of the insulating material 402 may be measured from the highest point where the insulating material contacts the dielectric structure 906 (e.g., the liner 702) to the lower surface 2106 of the insulating material 402. In various embodiments, the ratio of the height H3 to the height H4 (H3:H4) may be about 1:1.5 to about 1:2.5, such as about 1:2. In various embodiments, the ratio of the height H5 to the height H6 (H5:H6) may be about 1:10 to about 1:20, such as about 1:15 to about 1:18. If the ratio (H5:H6) is less than about 1:10, the substrate portions 102a and 102b may cover the sidewalls 2110 of the middle portion 402b (or even cover the sidewalls 2108 of the upper portion 402a), thereby causing the charge carriers diffused from the source / drain epitaxial structure 1502 to the substrate portions 102a and 102b to form an undesirable leakage current path in the subsequent depletion region 2101 (a conductive region located at or near the well 107 of the substrate 101, Fig.25B On the other hand, if the ratio (H5:H6) is greater than about 1:20, the amount of etchant used may increase, thereby increasing the risk of epitaxial damage.

[0130] In various embodiments, the fin cutting process (or sheet cutting process) includes a first etching scheme and a second etching scheme. The first etching scheme may be a plasma-based etching process, which uses one or more etchants that selectively remove the first semiconductor layer 106 and the second semiconductor layer 108 (and portions of the patterned mask layer 1704'), but does not substantially remove the dielectric structure 906 and the sacrificial gate layer 1106. In some embodiments, the first etching scheme may continue until the depth of the opening 2102 reaches the upper surface of the insulating material 402. The first etching scheme may additionally or alternatively continue until the sidewalls of the insulating material 402 (i.e., the sidewalls 2108 of the upper portion 402a) are exposed.

[0131] Once the opening 2102 reaches the desired depth of the first etching scheme, a second etching scheme is performed to extend the opening 2102 through the depletion region 2101 and to the desired depth in the accumulation region 2105. The accumulation region 2105 here refers to the non-conductive region within the substrate portions 102a and 102b and below the depletion region 2101, such as Fig.21A and Fig. 21BAs shown. In some embodiments, a second etching scheme is performed so that the height H5 of the bottom 402c of the insulating material 402 is less than or equal to about 10 nm. The second etching scheme may be a dry etching process, which uses one or more etchants that selectively remove the substrate portions 102a and 102b and a portion of the insulating material 402, but does not substantially remove the dielectric structure 906 and the sacrificial gate layer 1106. The etchant used in the first etching scheme may be a chlorine-based etching chemistry, a bromine-based etching chemistry, or a chlorine / bromine-based etching chemistry. The chlorine-based etching chemistry can effectively remove the dielectric cap 904. The etchant used in the second etching scheme may be a fluorine-based etching chemistry, a chlorine-based etching chemistry, a bromine-based etching chemistry, a fluorine / chlorine-based etching chemistry, a fluorine / bromine-based etching chemistry, a chlorine / bromine-based etching chemistry, or any combination thereof. In an exemplary embodiment, the first etching scheme uses a bromine-based etching chemistry, and the second etching scheme uses a fluorine-based etching chemistry and a bromine-based etching chemistry, or vice versa. In another exemplary embodiment, the first etching scheme uses a bromine-based etching chemical, and the second etching scheme may use a bromine-based etching chemical. Exemplary chlorine-based etching chemicals may include, but are not limited to, chlorine, chloroform, carbon tetrachloride, boron trichloride, the like, or a combination thereof. Exemplary bromine-based etching chemicals may include, but are not limited to, hydrogen bromide, bromine, boron tribromide, the like, or a combination thereof. Exemplary fluorine-containing gases may include, but are not limited to, carbon tetrafluoride, sulfur hexafluoride, difluoromethane, difluoroethane, fluoroform, hexafluoroethane, the like, or a combination thereof.

[0132] In some embodiments, after the first etching scheme and before the second etching scheme, the exposed dielectric structure 906 and the sacrificial gate layer 1106 may be exposed to a gas mixture including a silicon-containing precursor (e.g., silicon tetrachloride), a bromine-containing precursor (e.g., hydrogen bromide), and an inert gas (e.g., argon), followed by an oxidation process to form a silicon oxide layer on the exposed dielectric structure 906 and the sacrificial gate layer 1106. The silicon oxide layer helps reduce the critical dimension of the opening 2102 so that the opening 2102 extends into the substrate portions 102a and 102b in the depletion region 2101 with an appropriate critical dimension. In these examples, the etching process uses an etching chemistry including a fluorine-containing gas (e.g., carbon tetrafluoride) and an inert gas (e.g., argon) to break through the silicon oxide layer.

[0133] In some embodiments, the second etching scheme is a cyclic process that repeats the plasma etching process and the breakdown step. The plasma etching process may use an inert gas (such as argon), an oxygen-containing gas (such as oxygen), and any etching chemical mentioned in the second etching scheme above (such as hydrogen bromide), which is configured to remove the substrate portions 102a and 102b. The breakdown step may use an inert gas (such as argon) and / or any etching chemical mentioned in the second etching scheme above (such as carbon tetrafluoride), which is configured to remove the substrate portions 102a and 102b, the insulating material 402, and any debris / byproducts formed during the plasma etching step. The plasma etching step may last for a first time period (T1), and the breakdown step may last for a second time period (T2), and the ratio of T1:T2 may be about 3:1 to about 6:1. The cyclic process may be repeated 2 to 5 cycles. In some embodiments, the second etching process also includes an over-etching step after the cyclic process. The over-etching step may use an inert gas (e.g., argon), an oxygen-containing gas (e.g., oxygen) as appropriate, and any etching chemistry mentioned in the second etching scheme (e.g., hydrogen bromide), which is configured to remove additional portions of the substrate portions 102a and 102b and ensure that the height H5 of the bottom 402c of the insulating material 402 is less than or equal to about 10 nm. In any case, the second etching process is performed until the lowest point 2114 of the upper surface of the substrate portions 102a and 102b of the isolation region 1804 is lower than the lower surface 2106 of the insulating material 402. In some embodiments, the substrate portions 102a and 102b and the dielectric material 2201 ( Fig. 22B ) defined by the interface 2203 ( Fig. 22B ) has a lowest point 2114, which is lower than the lower surface 2106 of the bottom 402c and is located in the accumulation area 2105.

[0134] During the first etching scheme, the removal of the silicon oxide layer, the plasma etching step of the second etching scheme, and the over-etching step, a radio frequency bias power may be delivered to the pedestal on which the semiconductor device structure 100 is placed to perform anisotropic etching. The use of a radio frequency bias power may also compensate for the etching selectivity required to remove the insulating material 402 and the substrate portions 102a and 102b. The radio frequency bias power and the cyclic process may provide a combined etching effect such that the removal amount of the upper portion 402a of the insulating material 402 is greater than the removal amount of the middle portion 402b, resulting in the sidewall 2108 of the upper portion 402a having a radius of curvature (relative to the flat surface of the sidewall 2110 of the middle portion 402b). In some embodiments, the sidewall 2110 of the middle portion 402b is slightly etched to form a radius of curvature that is smaller than the radius of curvature of the sidewall 2108 of the upper portion 402a. In any case, the RF bias power and cycle process are performed to gradually reduce the diameter of the middle portion 402b from the side adjacent to the upper portion 402a toward the side adjacent to the substrate portions 102a and 102b. Fig. 21C By using RF bias power and cyclic process, the substrate portions 102a and 102b can be completely removed from the upper portion 402a and the middle portion 402b of the insulating material 402, and only a small amount of the substrate portions 102a and 102b (i.e. Fig. 21C The silicon corner indicated by the dotted circle C in the figure is reduced) to maintain contact with the bottom 402c of the insulating material. In some embodiments, the highest point 2180 where the substrate portions 102a and 102b meet the insulating material 402 is located at or slightly below the bottom of the accumulation region 2105 ( Fig.21A and Fig. 21B Since the small amount of substrate portions 102a and 102b remaining on the sidewalls 2112 of the bottom portion 402c is not located in the depletion region 2101 where the well portion 107 is located, leakage current (charge carriers diffused from the source / drain epitaxial structure 1502 to the substrate portions 102a and 102b) in the well portion 107 between adjacent transistors in the active region 1806 can be avoided.

[0135] An exemplary process used in the second etching scheme may use an inductively coupled plasma / antenna plasma source driven by a radio frequency power generator, and the adjustable frequency used by the radio frequency power generator is about 13.56 MHz or about 27 MHz. The operating pressure of the process chamber may be about 3 mTorr to about 150 mTorr, and the operating temperature may be about 20°C to about 140°C. The source power provided by the radio frequency power generator may be between about 100 W and about 1500 W, and the output of the radio frequency power generator may be controlled by a pulse signal, and the duty cycle of the pulse signal is about 20% to 100%. In the second etching scheme, the operating range of the radio frequency bias power applied to the base is about 10 W to about 600 W, and the frequency is about 13 MHz or about 1.2 MHz. The second etching scheme is a cyclic process, which includes a plasma etching step (using hydrogen bromide, oxygen, and argon) and a breakdown step (using argon and / or carbon tetrafluoride). The over-etching step is a plasma etching process using hydrogen bromide, oxygen, and argon.

[0136] Due to the presence of the dielectric structure 906, it is difficult to provide a high etching selectivity by a single etching process without affecting the integrity of the dielectric structure 906 when removing the first semiconductor layer 106, the second semiconductor layer 108, the substrate portions 102a and 102b, and the insulating material 402. The first etching scheme and the second etching scheme and the cyclic process can provide different etching selectivities for different materials (such as semiconductor materials and oxides), and have the advantages of multiple single-step etching (such as continuous etching) processes, such as effectively removing the first semiconductor layer 106, the second semiconductor layer 108, the substrate portions 102a and 102b, and the insulating material 402, and maintaining the integrity of the dielectric structure 906.

[0137] exist Fig.22A and Fig. 22B, a dielectric material 2201 is filled into the opening 2102 of the isolation region 1804. The dielectric material 2201 and the dielectric structure 906 together form the isolation structure 2202. The composition of the dielectric material 2201 can be an oxygen-containing material (such as silicon oxide), a nitrogen-containing material (such as silicon nitride, silicon oxynitride, silicon carbon nitride, or silicon carbon nitride), a low dielectric constant dielectric material, or any suitable dielectric material. The dielectric material 2201 and the insulating material 402 may include the same or different materials, and the method for forming the dielectric material 2201 may be any suitable process such as chemical vapor deposition, plasma-assisted chemical vapor deposition, flowable chemical vapor deposition, or atomic layer deposition. Once the opening 2102 is filled, a planarization process such as a chemical mechanical polishing process can be performed to remove a portion of the dielectric material on the patterned mask layer 1704'. The planarization process is performed until a portion of the patterned mask layer 1704' is exposed. The isolation structure 2202 extends through the depletion region 2101 and into the accumulation region 2105 to block a leakage current path in the well 107 between adjacent transistors in the active region 1806 .

[0138] exist Fig.23A and Fig. 23B , the sacrificial gate stack 1102, the sacrificial gate dielectric layer 1104, the cap layer 602, and the second semiconductor layer 108 are removed. Removing the sacrificial gate stack 1102 and the second semiconductor layer 108 can form an opening 2302 between the spacers 1202 and between the first semiconductor layer 106. During the removal process, the interlayer dielectric layer 1604 and the nitrogen-containing layer 1606 can protect the source / drain epitaxial structure 1502. The method for removing the sacrificial gate stack 1102 can use plasma dry etching and / or wet etching. The sacrificial gate layer 1106 can be removed first, and then the sacrificial gate dielectric layer 1104 can be removed, and the removal method can be any suitable process such as dry etching, wet etching, or a combination of the above. In some embodiments, a wet etchant such as tetramethylammonium hydroxide solution may be used to selectively remove the sacrificial gate layer 1106 and the sacrificial gate dielectric layer 1104 without etching the spacer 1202 , the isolation structure 2202 , the interlayer dielectric layer 1604 , and the contact etch stop layer 1602 .

[0139] After removing the sacrificial gate stack 1102, the capping layer 602 may be exposed. The capping layer 602 and the second semiconductor layer 108 are removed to expose the dielectric spacer 1402 and the first semiconductor layer 106. The removal process may be any suitable etching process, such as dry etching, wet etching, or a combination thereof. The etching process may be a selective etching process that removes the capping layer 602 and the second semiconductor layer 108 but does not remove the spacer 1202, the interlayer dielectric layer 1604, the contact etch stop layer 1602, the isolation structure 2202, and the first semiconductor layer 106. As a result, a portion of the first semiconductor layer 106 not covered by the dielectric spacer 1402 is exposed in the opening 2302.

[0140] exist Fig.24A and Fig. 24B In the embodiment of the present invention, a replacement gate structure 2401 is formed. The replacement gate structure 2401 may each include an interface layer 2402, a gate dielectric layer 2404, and a gate layer 2406. The interface layer 2402 is formed to surround the exposed surface of the first semiconductor layer 106. In some embodiments, the interface layer 2402 may also be formed on the well portion of the substrate 101. The interface layer 2402 may include or may be an oxygen-containing material or a silicon-containing material, such as silicon oxide, silicon oxynitride, oxynitride, hafnium silicate, or the like. In one embodiment, the interface layer 2402 is silicon oxide. The interface layer 2402 may be formed by chemical vapor deposition, atomic layer deposition, a cleaning process, or any suitable process. Then, a gate dielectric layer 2404 is formed on the exposed surface of the semiconductor device structure 100. In some embodiments, the gate dielectric layer 2404 is formed to cover and contact the interface layer 2402. The gate dielectric layer 2404 may include or may be a high-k dielectric material, such as hafnium oxide, hafnium silicate, hafnium silicon oxynitride, hafnium aluminum oxide, hafnium lanthanum oxide, hafnium zirconium oxide, hafnium tantalum oxide, hafnium titanium oxide, lanthanum oxide, aluminum oxide, aluminum silicon oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, silicon oxynitride, or other suitable high-k materials. The gate dielectric layer 2404 may be a compliant layer formed by a compliant process such as an atomic layer deposition process or a chemical vapor deposition process.

[0141] After forming the interface layer 2402 and the gate dielectric layer 2404, a gate layer 2406 is formed on the gate dielectric layer 2404. The gate layer 2406 fills the opening 2302 ( Fig.23A and Fig. 23B) and surrounds a portion of each first semiconductor layer 106. The gate layer 2406 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride, tungsten nitride, tungsten carbonitride, titanium aluminum, titanium tantalum nitride, titanium aluminum nitride, tantalum nitride, tantalum carbonitride, tantalum carbide, tantalum silicon nitride, metal alloys, other suitable materials and / or combinations thereof. The gate layer 2406 may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, or other suitable methods.

[0142] exist Fig.25A and Fig.25B In the embodiment, one or more metal gate etch-back processes may be performed on the gate layer 2406 to make the upper surface of the gate layer 2406 and the upper surface of the gate dielectric layer 2404 recessed to be lower than the upper surface of the spacer 1202. In some embodiments, the spacer 1202 is also recessed to be lower than the upper surface of the interlayer dielectric layer 1604. Fig.25A As shown. A self-aligned contact layer 2504 is formed on the gate layer 2406 and the gate dielectric layer 2404 between the spacers 1202. The self-aligned contact layer 2504 may be a dielectric material having an etching selectivity relative to the interlayer dielectric layer 1604. In some embodiments, the self-aligned contact layer 2504 includes silicon nitride. A gate contact (not shown) may then be formed in the self-aligned contact layer 2504 to contact the gate layer 2406.

[0143] After forming the self-aligned contact layer 2504, the nitrogen-containing layer 1606 is removed and a contact opening is formed through the interlayer dielectric layer 1604 and the contact etch stop layer 1602 to expose the source / drain epitaxial structure 1502. The self-aligned contact layer 2504 can protect the gate layer 2406 when forming the contact opening. Then, a silicide layer 2502 is formed on the source / drain epitaxial structure 1502, and a contact 2506 is formed in the contact opening on the silicide layer 2502. The contact 2506 may include a conductive material such as ruthenium, molybdenum, cobalt, nickel, tungsten, titanium, tantalum, copper, aluminum, titanium nitride, or tantalum nitride. Although not shown, a barrier layer (such as titanium nitride, tantalum nitride, or the like) may be formed on the sidewalls of the contact opening before forming the contact 2506.

[0144] It should be understood that other CMOS and / or back-end processing may be performed on the semiconductor device structure 100 to form various structures such as transistors, contacts / vias, interconnect metal layers, dielectric layers, passivation layers, or the like.

[0145] The present invention can improve the semiconductor device structure by providing an isolation structure in the isolation region between adjacent active regions of the substrate to prevent leakage current in the well between adjacent transistors. The isolation structure extends through the depletion region in the substrate and extends into the accumulation region below the depletion region. Therefore, any leakage current caused by the charge carriers diffused from the source / drain epitaxial structure to the substrate can be blocked from passing through the substrate between adjacent transistors. In this way, the device performance required for the significantly reduced circuit and device can be achieved.

[0146] A semiconductor device structure and a method for forming the same are described. One embodiment is a semiconductor device structure, comprising: a substrate; and an isolation structure located on the substrate and between two adjacent transistors. The isolation structure comprises a dielectric structure; and an insulating material located below the dielectric structure. The insulating material comprises an upper portion, comprising a first sidewall and an upper surface contacting the dielectric structure; and a bottom portion having a second sidewall, wherein the substrate surrounds and contacts the second sidewall. The insulating material also comprises a middle portion having a third sidewall located between the first sidewall and the second sidewall. The semiconductor device structure also comprises a dielectric material contacting the dielectric structure, the first sidewall, the third sidewall, and the substrate.

[0147] In some embodiments, a diameter of the upper portion gradually increases in a direction away from the dielectric structure.

[0148] In some embodiments, a diameter of the middle portion gradually decreases in a direction away from the dielectric structure.

[0149] In some embodiments, the bottom portion has a first height, the insulating material has a second height, and a ratio of the first height to the second height is about 1:10 to about 1:20.

[0150] In some embodiments, the lowest point of the interface defined by the dielectric material and the substrate is below the lower surface of the base.

[0151] In some embodiments, a radius of curvature of the first sidewall is smaller than a radius of curvature of the third sidewall.

[0152] In some embodiments, the dielectric structure further includes a dielectric core material; a liner surrounding and contacting at least three surfaces of the dielectric core material; and a dielectric cap located above and contacting an upper surface of the dielectric core material and the liner.

[0153] Another embodiment is a semiconductor device structure. The semiconductor device structure includes a first source / drain epitaxial structure formed on a substrate; a second source / drain epitaxial structure formed on the substrate and adjacent to the first source / drain structure; two or more first semiconductor layers located between the first source / drain epitaxial structure and the second source / drain epitaxial structure; a gate layer surrounding a portion of one of the first semiconductor layers; and an isolation structure located on the substrate and adjacent to the second source / drain epitaxial structure. The isolation structure includes a dielectric structure; a dielectric material contacting an exposed surface of the dielectric structure; and a shallow trench isolation located below the dielectric structure. The shallow trench isolation also includes a first portion adjacent to the dielectric structure, and the dielectric material surrounds and contacts the first portion. The shallow trench isolation also includes a second portion located below the first portion, and the substrate surrounds and contacts the second portion.

[0154] In some embodiments, the semiconductor device structure also includes a third source / drain epitaxial structure formed on a substrate; a fourth source / drain epitaxial structure formed on the substrate and adjacent to the third source / drain epitaxial structure; and two or more second semiconductor layers located between the third source / drain structure and the fourth source / drain structure; wherein the gate layer surrounds a portion of one of the second semiconductor layers, and the third source / drain structure is separated from the second source / drain structure by an isolation structure.

[0155] In some embodiments, the second portion has a first height, the shallow trench isolation has a second height, and a ratio of the first height to the second height is about 1:10 to about 1:20.

[0156] In some embodiments, the first portion of the shallow trench isolation has a first component, and a diameter of the first portion gradually increases in a direction away from the dielectric structure.

[0157] In some embodiments, the first portion of the shallow trench isolation has a second component below the first component, and a diameter of the second component gradually decreases in a direction away from the dielectric structure.

[0158] In some embodiments, the first portion of the shallow trench isolation has a curved surface profile.

[0159] In some embodiments, the first feature has a first height, the shallow trench isolation has a second height, and a ratio of the first height to the second height is about 1:1.5 to about 1:2.5.

[0160] In some embodiments, a lowest point of an interface defined by the dielectric material and the substrate is lower than a lower surface of the second portion.

[0161] Other embodiments are methods for forming a semiconductor device structure. The method includes forming a first fin structure, a second fin structure, and a third fin structure from a substrate, wherein the second fin structure is located between the first fin structure and the third fin structure, the first fin structure, the second fin structure, and the third fin structure each include a plurality of first semiconductor layers and a plurality of second semiconductor layers that are stacked alternately, and the first fin structure, the second fin structure, and the third fin structure are separated from each other by a plurality of trenches. The method includes forming an insulating material in the trench to surround a portion of each of the first fin structure, the second fin structure, and the third fin structure. The method also includes forming a coating on the exposed surfaces of each of the first fin structure, the second fin structure, and the third fin structure; forming a dielectric structure on the insulating material in the trench; forming a sacrificial gate structure on a portion of the first fin structure, the second fin structure, and the third fin structure; and removing portions of the first fin structure, the second fin structure, and the third fin structure that are not covered by the sacrificial gate structure. The method also includes forming a source / drain structure on both sides of the sacrificial gate structure, wherein the source / drain structure contacts the first semiconductor layer and the second semiconductor layer of the first fin structure, the second fin structure, and the third fin structure. The method also includes forming a contact etch stop layer and an interface layer on the source / drain structure; and removing a portion of the sacrificial gate structure to expose the top of the second fin structure. The method also includes forming an opening in the exposed second fin structure, wherein the opening exposes a first sidewall portion of the dielectric structure and the insulating material, and the second sidewall portion of the insulating material remains in contact with each of the first fin structure, the second fin structure, and the third fin structure. The method also includes filling the opening with a dielectric material so that the first sidewall portion of the dielectric structure and the insulating material contacts the dielectric material; and removing the capping layer and the second semiconductor layer to expose a portion of the first semiconductor layer of the first fin structure, the second fin structure, and the third fin structure. The method also includes forming a gate layer to surround at least an exposed portion of one of the first semiconductor layers of the first fin structure, the second fin structure, and the third fin structure.

[0162] In some embodiments, the step of forming the opening in the exposed second fin structure also includes performing a first etching process to remove the first semiconductor layer and the second semiconductor layer of the second fin structure; and once the first sidewall portion of the insulating material is exposed, performing a second etching process to remove a portion of the substrate and a portion of the insulating material.

[0163] In some embodiments, the second etching process is a cyclic process comprising repeating a first plasma etching step and a second plasma etching step, wherein the first plasma etching step employs a first etching chemistry configured to remove the substrate, and the second plasma etching step employs a second etching chemistry configured to remove the substrate and the insulating material.

[0164] In some embodiments, the method further includes applying a bias power during the cycling process.

[0165] In some embodiments, the second etching process causes the first sidewall portion of the insulating material to have a curved surface profile and a diameter, and the diameter gradually increases along a direction away from the dielectric structure.

[0166] The features of the above embodiments are helpful for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device structure, characterized in that: include: a first source / drain epitaxial structure formed on a substrate; a second source / drain epitaxial structure formed on the substrate and adjacent to the first source / drain structure; Two or more first semiconductor layers are located between the first source / drain epitaxial structure and the second source / drain epitaxial structure; a gate layer surrounding a portion of one of the plurality of first semiconductor layers; as well as an isolation structure, located on the substrate and adjacent to the second source / drain epitaxial structure, and comprising: a dielectric structure; a dielectric material contacting the exposed surface of the dielectric structure; and A shallow trench isolation is located below the dielectric structure, and the shallow trench isolation includes: a first portion adjacent to the dielectric structure, with the dielectric material surrounding and contacting the first portion; and A second portion is located below the first portion, and the substrate surrounds and contacts the second portion.

2. The semiconductor device structure according to claim 1, wherein: Also includes: a third source / drain epitaxial structure formed on the substrate; a fourth source / drain epitaxial structure formed on the substrate and adjacent to the third source / drain epitaxial structure; as well as Two or more second semiconductor layers are located between the third source / drain structure and the fourth source / drain structure; The gate layer surrounds a portion of one of the second semiconductor layers, and the third source / drain structure is separated from the second source / drain structure by the isolation structure.

3. The semiconductor device structure according to claim 1 or 2, wherein: The first portion of the shallow trench isolation has a first component, and the diameter of the first component gradually increases along a direction away from the dielectric structure.

4. The semiconductor device structure according to claim 3, wherein: The first portion of the shallow trench isolation has a second component located below the first component, and the diameter of the second component gradually decreases along a direction away from the dielectric structure.

5. The semiconductor device structure according to claim 3, wherein: The first portion of the shallow trench isolation has a curved surface profile.

6. The semiconductor device structure according to claim 5, wherein: The first radius of the first curvature of the sidewall of the first portion is greater than the second radius of the second curvature of the sidewall of the second portion.

7. The semiconductor device structure according to claim 3, wherein: The first component has a first height, the shallow trench isolation has a second height, and the ratio of the first height to the second height is 1:1.5 to 1:2.

5.

8. The semiconductor device structure according to claim 1 or 2, wherein: The lowest point of an interface defined by the dielectric material and the substrate is lower than the lower surface of the second portion.

9. The semiconductor device structure according to claim 1 or 2, wherein: The second portion has a first height, the shallow trench isolation has a second height, and the ratio of the first height to the second height is 1:10 to 1:

20.

10. The semiconductor device structure according to claim 1 or 2, wherein: The dielectric structure further comprises: a dielectric core material; a liner surrounding and contacting at least three surfaces of the dielectric core material; and A dielectric cap is located above and contacts the upper surface of the dielectric core material and the upper surface of the liner.

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