Novel four-output phase-locked loop satellite frequency demultiplier

Abstract

The utility model discloses a novel four-output phase-locked loop satellite frequency demultiplier, the frequency demultiplier is formed by assembling a housing and a frequency demultiplier circuit, the frequency demultiplier circuit is locked in the housing, and the housing comprises a feed source, a waveguide tube and an output terminal. The frequency reduction circuit comprises a two-stage horizontal signal common end amplification module, a two-stage vertical signal common end amplification module, a field effect transistor bias control module, four CMOS satellite tuners, four crystal oscillators and a DCamp. And a DC power supply module. The beneficial effects of the technical scheme are that after amplification, frequency mixing and tuning are carried out through the frequency reduction circuit in the housing, four paths of intermediate frequency signals VL, VH, HL and HH are respectively output through the four output terminals. The four paths of intermediate frequency signals are connected to the converter system through coaxial cables, and can be connected with a plurality of satellite receivers through the converter system to realize simultaneous use of a plurality of clients.

Description

Technical Field

[0001] The utility model relates to the technical field of satellite signal reception, in particular to a novel four-output phase-locked loop satellite frequency reducer. Background Art

[0002] With the rapid development of modern satellite communication technology, more and more satellites are being launched in various countries and regions, so satellite frequency converters have also been updated according to market demand. However, due to the shortage of chips and wafers required in the field of satellite communication in recent years, the prices of quad-output chips from some mainstream manufacturers have remained high and are on the rise. As a result, the original quad-output frequency converter has lost its competitive advantage in market prices. On the other hand, single-output chips have more advantages in terms of cost due to the large market demand and mature technology, so it was decided to use four single-output chips to develop a new quad-output phase-locked loop frequency converter. Utility Model Content

[0003] To achieve the above purpose, the utility model creates a technical solution: a novel four-output phase-locked loop satellite frequency reducer, including a housing and a frequency reduction circuit. The frequency reduction circuit is locked in the housing, and the frequency reduction circuit includes a two-stage horizontal signal common end amplification module, a two-stage vertical signal common end amplification module, a field effect tube bias control module, four CMOS satellite tuners, four crystal oscillators, and a DC&DC power supply module; the power supply module of the frequency reduction circuit is electrically connected to the four CMOS satellite tuners and the field effect tube bias control module to provide the voltage required for the two to work, the field effect tube bias control module is electrically connected to the two-stage horizontal signal common end amplification module and the two-stage vertical signal common end amplification module respectively, the two-stage horizontal signal common end amplification module and the two-stage vertical signal common end amplification module are electrically connected to the four CMOS satellite tuners respectively, the four CMOS satellite tuners are electrically connected to the four crystal oscillators, and the output ends of the four CMOS satellite tuners are electrically connected to the output terminals.

[0004] Furthermore, the shell includes a feed source, a waveguide tube, and an output terminal. The feed source is connected to the shell through the waveguide tube, and the received horizontal and vertical satellite signals are transmitted to the frequency reduction circuit through the waveguide tube.

[0005] Furthermore, the output terminals are locked on the housing, and the output terminals are four-way output terminals of VL, VH, HL, and HH.

[0006] Furthermore, the frequency reduction circuit amplifies the received horizontal and vertical signals through high frequency, and obtains intermediate frequency signals after mixing through four output terminals VL, VH, HL, HH to output four satellite intermediate frequency signals VL, VH, HL, HH respectively.

[0007] Furthermore, the four satellite intermediate frequency signals VL, VH, HL, and HH are connected to the converter system via coaxial cables and distributed to multiple satellite receivers connected to the system through the converter system.

[0008] Furthermore, the output terminals are divided into four output terminals of VL, VH, HL, and HH, and one or more four-input and four-output active satellite switch matrix modules with tone voltage decoders are arranged in front of the output terminals, so that each of the output ports in the downconverter can switch between VL, VH, HH, and HL signals, forming a four-output or more phase-locked loop downconverter with switching.

[0009] The beneficial effects of the utility model are: the price advantage and mature and stable characteristics of a single-output chip are used to design a quad-output downconverter, which reduces product costs, stabilizes the circuit structure, and improves product characteristics. In addition, the advantages of DC&DC power supply are used to reduce power loss and generate less heat than the original quad-output chip design, so that product characteristics are more stable. This not only reduces product costs, but also ensures product quality, making the product more competitive in the market. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the structure explosion of the utility model.

[0011] Figure 2 It is a schematic diagram of a frequency reduction circuit of the utility model.

[0012] Figure 3 This is a diagram of implementation mode 1 of the frequency reduction circuit of the present utility model.

[0013] Figure 4 FIG. 2 is a frequency reduction circuit implementation scheme of the present utility model. DETAILED DESCRIPTION

[0014] In order to enable those skilled in the art to better understand the technical solution of the utility model, the utility model is described in detail below in conjunction with the accompanying drawings. The description in this part is only exemplary and explanatory and should not have any limiting effect on the protection scope of the utility model.

[0015] Please refer to Figure 1A novel four-output phase-locked loop satellite frequency reducer is composed of two parts: a housing (1) and a frequency reduction circuit. The frequency reduction circuit is locked in the housing (1). The housing (1) includes a feed source (11), a waveguide (12), and an output terminal (13). The frequency reduction circuit includes a two-stage horizontal signal common end amplifier module, a two-stage vertical signal common end amplifier module, a field effect tube bias control module, four CMOS satellite tuners, four crystal oscillators, and a DC&DC power supply module. The feed source (11) is horn-shaped and connected to the housing (1) via the waveguide (12). The output terminal (13) is locked on the housing (1). The output terminals (13) are four output terminals: VL (13a), VH (13b), HL (13c), and HH (13d).

[0016] The feed source (11) transmits the received horizontal and vertical satellite signals to the frequency reduction circuit via the waveguide (12).

[0017] like Figure 2 As shown, the frequency reduction circuit amplifies the received horizontal and vertical signals through high frequency, and obtains the intermediate frequency signals after mixing, and outputs four satellite intermediate frequency signals of VL, VH, HL, and HH through four output terminals (13) of VL (13a), VH (13b), HL (13c), and HH (13d). The four satellite intermediate frequency signals of VL, VH, HL, and HH are connected to the converter system through coaxial cables, and are distributed to multiple satellite receivers connected to the system through the converter system. A four-input and four-output active satellite switch matrix module with a tone voltage decoder is provided in front of the four output terminals (13), so that each of the output ports in the frequency reducer can switch between the VL, VH, HH, and HL signals, forming a four-output phase-locked loop frequency reducer with switching.

[0018] like Figure 2 As shown, the power module of the frequency reduction circuit is electrically connected to the four CMOS satellite tuners and the field effect tube bias control module to provide the voltage required for the two to work. The field effect tube bias control module is electrically connected to the two-stage horizontal signal common end amplification module and the two-stage vertical signal common end amplification module respectively, and the two-stage horizontal signal common end amplification module and the two-stage vertical signal common end amplification module are electrically connected to the four CMOS satellite tuners respectively, and the four CMOS satellite tuners are electrically connected to the four crystal oscillators, and the output ends of the four CMOS satellite tuners are electrically connected to the output terminals.

[0019] After the downconverter is installed, the downconverter collects satellite signals in the 10.7-12.75 GHz general frequency band reflected by the parabolic antenna through the feed source (11), polarizes the satellite signals into one horizontal signal through the waveguide (12) and the polarization rod, and then the vertical signal is amplified, mixed and processed by the downconverter circuit. The output terminal (13) outputs four intermediate frequency signals, namely, a vertically polarized low local oscillator signal VL (13a), a vertically polarized high local oscillator signal VH (13b), a horizontally polarized low local oscillator signal HL (13c) and a horizontally polarized high local oscillator signal HH (13d). The signals are connected to the converter system through the output port (13) via a coaxial cable and distributed to multiple satellite receivers connected to the system through the converter system, so that one set of receiving system can be used by multiple user terminals at the same time. The system is particularly suitable for areas where user terminals are concentrated (such as residential units, hotels, apartments, etc.), reduces the number of outdoor receiving devices installed, and reduces the installation and maintenance costs to a certain extent. Specific implementation method 1

[0021] Each output port of the above utility model design can only output one frequency band respectively: P1 outputs VL, P2 outputs VH, P3 outputs HH, and P4 outputs HL. In order to meet different demand scenarios, a four-input and four-output active satellite switch matrix module with a tone / voltage decoder is added to this design, so that each of the four output ports in the downconverter can switch between VL, VH, HH, and HL signals, realizing a four-output phase-locked loop downconverter with switching.

[0022] like Figure 3The frequency reduction circuit shown includes a two-stage horizontal signal common end amplification module, a two-stage vertical signal common end amplification module, a field effect tube bias control module, four CMOS satellite tuners, four crystal oscillators, and a DC&DC power supply module; the power supply module of the frequency reduction circuit is electrically connected to the four CMOS satellite tuners and the field effect tube bias control module to provide the voltage required for the two to work, the field effect tube bias control module is electrically connected to the two-stage horizontal signal common end amplification module and the two-stage vertical signal common end amplification module respectively, the two-stage horizontal signal common end amplification module and the two-stage vertical signal common end amplification module are electrically connected to the four CMOS satellite tuners respectively, the four CMOS satellite tuners are electrically connected to the four crystal oscillators, and the output ends of the four CMOS satellite tuners are electrically connected to the output terminals. The frequency reduction circuit amplifies the received horizontal and vertical signals at high frequencies, and the intermediate frequency signals obtained after mixing are output through the four output terminals of VL, VH, HL, and HH, respectively, and the four satellite intermediate frequency signals of VL, VH, HL, and HH are output. Then, a four-input and four-output active satellite switch matrix module with a tone voltage decoder is added in front of the four output terminals of VL, VH, HL, and HH, so that each of the output ports in the downconverter can switch between VL, VH, HH, and HL signals, forming a four-output phase-locked loop downconverter with switching. Specific implementation method 2

[0024] By adding two four-input and four-output active satellite switch matrix modules with tone / voltage decoders to this design, each of the eight output ports in the downconverter can be switched between VL, VH, HH, and HL signals, realizing an eight-output phase-locked loop downconverter with switching.

[0025] like Figure 4The frequency reduction circuit shown includes a two-stage horizontal signal common end amplification module, a two-stage vertical signal common end amplification module, a field effect tube bias control module, four CMOS satellite tuners, four crystal oscillators, and a DC&DC power supply module; the power supply module of the frequency reduction circuit is electrically connected to the four CMOS satellite tuners and the field effect tube bias control module to provide the voltage required for the two to work, the field effect tube bias control module is electrically connected to the two-stage horizontal signal common end amplification module and the two-stage vertical signal common end amplification module respectively, the two-stage horizontal signal common end amplification module and the two-stage vertical signal common end amplification module are electrically connected to the four CMOS satellite tuners respectively, the four CMOS satellite tuners are electrically connected to the four crystal oscillators, and the output ends of the four CMOS satellite tuners are electrically connected to the output terminals. The frequency reduction circuit amplifies the received horizontal and vertical signals at high frequencies, and the intermediate frequency signals obtained after mixing are output through the four output terminals of VL, VH, HL, and HH, respectively, and the four satellite intermediate frequency signals of VL, VH, HL, and HH are output. Then, two four-input and four-output active satellite switch matrix modules with tone voltage decoders are added in front of the four output terminals of VL, VH, HL, and HH, so that each of the output ports in the downconverter can switch between VL, VH, HH, and HL signals, forming an eight-output phase-locked loop downconverter with switching.

[0026] The above is only a preferred implementation of the utility model. It should be pointed out that due to the limitations of textual expression, there are objectively infinite specific structures. For ordinary technicians in this technical field, without departing from the principle of the utility model, they can make several improvements, modifications or changes, and can also combine the above technical features in an appropriate manner; these improvements, modifications, changes or combinations, or the direct application of the concept and technical solution of the utility model to other occasions without improvement, should be regarded as the protection scope of the utility model.

Claims

1. A novel four-output phase-locked loop satellite downconverter, characterized in that: It comprises a shell and a frequency reduction circuit; the frequency reduction circuit is locked in the shell, and the frequency reduction circuit comprises a two-stage horizontal signal common end amplification module, a two-stage vertical signal common end amplification module, a field effect tube bias control module, four CMOS satellite tuners, four crystal oscillators, and a DC&DC power supply module; the power supply module of the frequency reduction circuit is electrically connected to the four CMOS satellite tuners and the field effect tube bias control module to provide the voltage required for the two to work, the field effect tube bias control module is electrically connected to the two-stage horizontal signal common end amplification module and the two-stage vertical signal common end amplification module respectively, the two-stage horizontal signal common end amplification module and the two-stage vertical signal common end amplification module are electrically connected to the four CMOS satellite tuners respectively, the four CMOS satellite tuners are electrically connected to the four crystal oscillators, and the output ends of the four CMOS satellite tuners are electrically connected to the output terminals.

2. A novel quad-output phase-locked loop satellite downconverter according to claim 1, characterized in that: The shell comprises a feed source, a waveguide tube and an output terminal. The feed source transmits the received horizontal and vertical satellite signals to the frequency reduction circuit through the waveguide tube.

3. A novel quad-output phase-locked loop satellite downconverter according to claim 2, characterized in that: The output terminals are locked on the housing, and the output terminals are divided into four output terminals: VL, VH, HL, and HH.

4. The novel quad-output phase-locked loop satellite downconverter according to claim 1, characterized in that: The frequency reduction circuit amplifies the received horizontal and vertical signals through high frequency, and obtains intermediate frequency signals after mixing, and outputs four satellite intermediate frequency signals of VL, VH, HL, and HH through four output terminals of VL, VH, HL, and HH respectively.

5. The novel quad-output phase-locked loop satellite downconverter according to claim 3, characterized in that: The four satellite intermediate frequency signals VL, VH, HL, and HH are connected to the converter system via coaxial cables and distributed to multiple satellite receivers connected to the system through the converter system.

6. A novel quad-output phase-locked loop satellite downconverter according to claim 2, characterized in that: One or more four-input and four-output active satellite switch matrix modules with tone voltage decoders are arranged in front of the four-way output terminals, so that each of the output ports in the downconverter can switch between VL, VH, HH, and HL signals, forming a four-output or more phase-locked loop downconverter with switching.

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