3D packaged quartz crystal clock module

Abstract

The utility model relates to the field of electronic component packaging structures, in particular to a 3D packaging quartz crystal clock module. The D-packaged quartz crystal clock module provided by the utility model comprises a substrate, a quartz crystal frequency component, an IC chip, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a test position connecting column, a test column and a conductive column, according to the 3D packaging quartz crystal clock module, circuit connection is realized through the layered insulating layer, the test position connecting column embedded in the insulating layer, the test column and the conductive column, and the 3D packaging quartz crystal clock module is compact in overall structure and convenient to process.

Description

Technical Field

[0001] The utility model relates to the field of electronic component packaging structures, in particular to a 3D packaged quartz crystal clock module. Background Art

[0002] The structure of traditional quartz crystal electronic devices usually consists of a metal cover, a quartz wafer, a chip and a ceramic base, and is vacuum packaged. The chip is connected to the circuit on the ceramic base by bonding and gold wire. The upper and lower surfaces of the quartz wafer need to be evaporated or sputtered with electrodes and connected to the pins of the ceramic base. The AC voltage can be connected to the upper and lower electrodes of the quartz wafer through the pins, causing the quartz wafer to produce an inverse piezoelectric effect, thereby generating oscillations.

[0003] With the rapid development of mobile communication electronics, the demand for device miniaturization is getting higher and higher, and the miniaturization of quartz crystal electronic devices is also imperative. However, if quartz crystal electronic devices are to be further reduced in size under the current traditional packaging structure, they will be subject to greatly reduced yields and higher material and manufacturing costs. Utility Model Content

[0004] In order to solve the defect that the existing quartz crystal electronic devices in the above-mentioned prior art are difficult to meet the miniaturization requirements, the utility model proposes a 3D packaged quartz crystal clock module.

[0005] A D-package quartz crystal clock module proposed by the present invention comprises: a substrate, a quartz crystal frequency component, an IC chip, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a test position connection column, a test column and a conductive column;

[0006] The quartz crystal frequency component is arranged on the base with its bottom facing upward, the IC is arranged on the bottom surface of the quartz crystal frequency component, the first insulating layer covers the quartz crystal frequency component and the IC chip, and the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are stacked from bottom to top and connected into one body;

[0007] The two test position connection posts correspond to the two test pins of the quartz crystal frequency component respectively, the test position connection posts are embedded in the first insulating layer and the second insulating layer, and the bottom of the test position connection posts is conductively connected to the corresponding test pins; the two test posts correspond to the two test pins of the IC chip respectively, the test posts are embedded in the second insulating layer, and the bottom of the test posts is conductively connected to the corresponding test pins;

[0008] The test connection posts correspond to the test posts one by one, and a first conductive strip connecting the corresponding test connection posts and the test posts is provided on the top surface of the second insulating layer;

[0009] The four conductive pillars correspond one-to-one to the four input and output pins of the IC chip. The conductive pillars are embedded in the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer. The bottom of the conductive pillar is conductively connected to the corresponding input and output pins. The fourth insulating layer is provided with a second conductive belt corresponding one-to-one to each conductive pillar, and the second conductive belt extends from one end of the conductive pillar to the edge of the fourth insulating layer.

[0010] Preferably, the IC chip is die-bonded to the quartz crystal frequency component.

[0011] Preferably, the two test pins of the quartz crystal frequency component are located in a diagonal direction.

[0012] Preferably, the test bit connection column is vertically embedded in the first insulating layer and the second insulating layer.

[0013] Preferably, the test column is vertically embedded in the second insulating layer.

[0014] Preferably, the conductive pillars are vertically embedded in the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer.

[0015] Preferably, the batch-processed clock module array is a structure cut into units of quartz crystal frequency components, and the batch-processed clock module array includes: a substrate, a quartz crystal frequency component, an IC chip, a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer;

[0016] Small grooves are distributed on the base, and a quartz crystal frequency component with the bottom facing upward is arranged in each small groove; an IC chip is arranged on the bottom surface of each quartz crystal frequency component;

[0017] The first insulating layer covers all quartz crystal frequency components and IC chips; two connection pins on the back of the quartz crystal frequency components are used as test pins, and a first small hole is provided on the first insulating layer corresponding to each test pin, and crystals are formed in the first small hole to form a test position connection column, and the top of the test position connection column is higher than the first insulating layer;

[0018] The second insulating layer is disposed on the first insulating layer and formed integrally, the top surface of the second insulating layer is flush with the top surface of the test bit connection column; second small holes corresponding to and connected to two test pins of each IC chip are formed on the second insulating layer, and crystals are grown in the second small holes to form test columns;

[0019] The two test pins of the quartz crystal frequency component respectively correspond to the two test pins of the connected IC chip; the second insulating layer also forms a first conductive strip connecting the corresponding test posts and the test position connection posts;

[0020] The third insulating layer is arranged on the second insulating layer and forms an integral body, the third insulating layer covers the first conductive strip, the third insulating layer is provided with third small holes corresponding to and connected to the four input and output pins of each IC chip, and the third small holes are formed to form conductive columns; the top of the conductive column is higher than the third insulating layer;

[0021] The fourth insulating layer is arranged on the third insulating layer and forms an integral body, and the fourth insulating layer is flush with the top of the conductive column; the fourth insulating layer is provided with a second conductive belt corresponding to each conductive column and conductively connected thereto.

[0022] The advantages of the utility model are:

[0023] (1) The 3D packaged quartz crystal clock module in the utility model realizes circuit connection through a layered insulating layer, a test position connection column embedded in the insulating layer, a test column and a conductive column. The overall structure is compact and easy to process.

[0024] (2) The utility model can realize batch processing of whole-board clock modules by processing a substrate supporting multiple quartz crystal frequency components, and then cut them to obtain single clock modules, thereby realizing wafer-level packaging of the modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is the connection diagram between the quartz crystal frequency components and the IC chip die;

[0026] Figure 2 A diagram showing a first insulating layer;

[0027] Figure 3 It is a diagram showing the connection column of the test position;

[0028] Figure 4 Shown is the diagram for the second small hole;

[0029] Figure 5 A diagram is shown for the second insulating layer and the first conductive tape;

[0030] Figure 6 A diagram showing a third insulating layer and a third small hole;

[0031] Figure 7 Show diagram for conductive column;

[0032] Figure 8 It is a three-dimensional diagram of a quartz crystal module;

[0033] Fig. 9 is a top view of the base;

[0034] Fig.10 It is a base stereogram.

[0035] 1. Quartz crystal frequency component; 1-1. Test pin; 2. IC chip; 3. First insulating layer; 3-1. First small hole; 4. Second insulating layer; 4-1. Second small hole; 5. Third insulating layer; 5-1. Third small hole; 6. Fourth insulating layer; 7. Test position connecting column; 8. Test column; 9. First conductive strip; 10. Conductive column; 11. Second conductive strip; 12. Base; 12-1. Small groove. DETAILED DESCRIPTION

[0036] Reference Figure 1-Figure 8 , a batch-processed clock module array proposed in this embodiment includes: a substrate 12, a quartz crystal frequency component 1, an IC chip 2, a first insulating layer 3, a second insulating layer 4, a third insulating layer 5 and a fourth insulating layer 6;

[0037] Small grooves 12-1 are distributed on the substrate 12, and a quartz crystal frequency component 1 with the bottom facing upward is arranged in each small groove 12-1; an IC chip 2 is arranged on the bottom surface of each quartz crystal frequency component 1, and specifically, the IC chip 2 can be solid-crystal-bonded on the quartz crystal frequency component 1;

[0038] The first insulating layer 3 covers all quartz crystal frequency components 1 and IC chips 2; two connecting pins at diagonal positions are selected on the back of the quartz crystal frequency component 1 as test pins 1-1, and a first small hole 3-1 is provided on the first insulating layer 3 corresponding to each test pin 1-1, and a test position connecting column 7 is formed in the first small hole 3-1, and the top of the test position connecting column 7 is higher than the first insulating layer 3;

[0039] The second insulating layer 4 is disposed on the first insulating layer 3 and formed integrally, and the top surface of the second insulating layer 4 is flush with the top surface of the test bit connection column 7; the second insulating layer 4 is formed with second small holes 4-1 corresponding to and connected to two test pins of each IC chip 2, and the test column 8 is formed in the second small hole 4-1;

[0040] The two test pins 1-1 of the quartz crystal frequency component 1 correspond to the two test pins of the connected IC chip 2 respectively; the second insulating layer 4 also forms a first conductive band 9 connecting the corresponding test column 8 and the test position connection column 7;

[0041] The third insulating layer 5 is disposed on the second insulating layer 4 and forms an integral body, the third insulating layer 5 covers the first conductive tape 9, the third insulating layer 5 is provided with third small holes 5-1 corresponding to and connected to the four input and output pins of each IC chip 2, and a conductive column 10 is formed in the third small hole 5-1; the top of the conductive column 10 is higher than the third insulating layer 5;

[0042] The fourth insulating layer 6 is disposed on the third insulating layer 5 and forms an integral body, and the fourth insulating layer 6 is flush with the top of the conductive pillar 10 ; the fourth insulating layer 6 is provided with a second conductive band 11 corresponding to and conductively connected to each conductive pillar 10 .

[0043] Reference Figure 1-Figure 8 The 3D packaged quartz crystal clock module proposed in this embodiment is a structure in which a batch-processed clock module array is cut into units of quartz crystal frequency components 1. On the clock module, each second conductive band 11 extends to the edge.

[0044] That is, the clock module includes: a substrate 12, a quartz crystal frequency component 1, an IC chip 2, a first insulating layer 3, a second insulating layer 4, a third insulating layer 5 and a fourth insulating layer 6; the quartz crystal frequency component 1 is arranged on the substrate 12 with its bottom facing upward, the IC is arranged on the bottom surface of the quartz crystal frequency component 1, the first insulating layer 3 covers the quartz crystal frequency component 1 and the IC chip 2, and the first insulating layer 3, the second insulating layer 4, the third insulating layer 5 and the fourth insulating layer 6 are stacked from bottom to top and connected as a whole;

[0045] The two test position connection posts 7 correspond to the two test pins 1-1 of the quartz crystal frequency component 1 respectively, the test position connection posts 7 are embedded in the first insulating layer 3 and the second insulating layer 4, and the bottom of the test position connection posts 7 is conductively connected to the corresponding test pins 1-1; the two test posts 8 correspond to the two test pins of the IC chip 2 respectively, the test posts 8 are embedded in the second insulating layer 4, and the bottom of the test posts 8 is conductively connected to the corresponding test pins;

[0046] The test connection posts correspond to the test posts 8 one by one, and the top surface of the second insulating layer 4 is provided with a first conductive band 9 connecting the corresponding test connection posts and the test posts 8;

[0047] The four conductive pillars 10 correspond one-to-one to the four input and output pins of the IC chip 2. The conductive pillars 10 are embedded in the first insulating layer 3, the second insulating layer 4, the third insulating layer 5 and the fourth insulating layer 6. The bottom of the conductive pillars 10 is conductively connected to the corresponding input and output pins. The fourth insulating layer 6 is provided with second conductive strips 11 corresponding one-to-one to each conductive pillar 10. The second conductive strip 11 extends from one end of the conductive pillar 10 to the edge of the fourth insulating layer 6.

[0048] Specifically, in this embodiment, the test bit connection pillar 7 , the test pillar 8 and the conductive pillar 10 are all perpendicular to the first insulating layer 3 , the second insulating layer 4 , the third insulating layer 5 and the fourth insulating layer 6 .

[0049] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A 3D packaged quartz crystal clock module, It is characterized in that include: A substrate (12), a quartz crystal frequency component (1), an IC chip (2), a first insulating layer (3), a second insulating layer (4), a third insulating layer (5), a fourth insulating layer (6), a test position connection column (7), a test column (8) and a conductive column (10); The quartz crystal frequency component (1) is arranged on a base (12) with its bottom facing upward, the IC is arranged on the bottom surface of the quartz crystal frequency component (1), the first insulating layer (3) covers the quartz crystal frequency component (1) and the IC chip (2), and the first insulating layer (3), the second insulating layer (4), the third insulating layer (5) and the fourth insulating layer (6) are stacked from bottom to top and connected into one body; The two test position connection columns (7) correspond to the two test pins (1-1) of the quartz crystal frequency component (1), respectively; the test position connection columns (7) are embedded in the first insulating layer (3) and the second insulating layer (4), and the bottom of the test position connection columns (7) is conductively connected to the corresponding test pins (1-1); the two test columns (8) correspond to the two test pins of the IC chip (2), respectively; the test columns (8) are embedded in the second insulating layer (4), and the bottom of the test columns (8) is conductively connected to the corresponding test pins; The test connection posts correspond to the test posts (8) one by one, and a first conductive band (9) connecting the corresponding test connection posts and the test posts (8) is provided on the top surface of the second insulating layer (4); The four conductive posts (10) correspond one-to-one to the four input and output pins of the IC chip (2); the conductive posts (10) are embedded in the first insulating layer (3), the second insulating layer (4), the third insulating layer (5) and the fourth insulating layer (6); the bottom of the conductive posts (10) is conductively connected to the corresponding input and output pins; the fourth insulating layer (6) is provided with second conductive strips (11) corresponding one-to-one to each conductive post (10); the second conductive strips (11) extend from one end of the conductive post (10) to the edge of the fourth insulating layer (6).

2. The 3D packaged quartz crystal clock module according to claim 1, It is characterized in that The IC chip (2) is solidly connected to the quartz crystal frequency component (1).

3. The 3D packaged quartz crystal clock module according to claim 1, It is characterized in that Two test pins (1-1) of the quartz crystal frequency component (1) are located in a diagonal direction.

4. The 3D packaged quartz crystal clock module according to claim 1, It is characterized in that The test bit connection column (7) is vertically embedded in the first insulating layer (3) and the second insulating layer (4).

5. The 3D packaged quartz crystal clock module according to claim 1, It is characterized in that The test column (8) is vertically embedded in the second insulating layer (4).

6. The 3D packaged quartz crystal clock module according to claim 1, It is characterized in that The conductive pillar (10) is vertically embedded in the first insulating layer (3), the second insulating layer (4), the third insulating layer (5) and the fourth insulating layer (6).

7. The 3D packaged quartz crystal clock module according to claim 1, It is characterized in that The clock module array for batch processing is a structure obtained by cutting the quartz crystal frequency components (1) as units. The clock module array for batch processing comprises: a substrate (12), a quartz crystal frequency component (1), an IC chip (2), a first insulating layer (3), a second insulating layer (4), a third insulating layer (5) and a fourth insulating layer (6); Small grooves (12-1) are distributed on the base (12), and a quartz crystal frequency component (1) with its bottom facing upward is arranged in each small groove (12-1); an IC chip (2) is arranged on the bottom surface of each quartz crystal frequency component (1); The first insulating layer (3) covers all quartz crystal frequency components (1) and the IC chip (2); two connection pins on the back of the quartz crystal frequency component (1) serve as test pins (1-1); a first small hole (3-1) is provided on the first insulating layer (3) corresponding to each test pin (1-1); a test position connection column (7) is formed in the first small hole (3-1); and the top of the test position connection column (7) is higher than the first insulating layer (3); The second insulating layer (4) is arranged on the first insulating layer (3) and forms an integral body, the top surface of the second insulating layer (4) being flush with the top surface of the test bit connection column (7); second small holes (4-1) corresponding to and connected to two test pins of each IC chip (2) are formed on the second insulating layer (4), and the test columns (8) are formed in the second small holes (4-1); Two test pins (1-1) of the quartz crystal frequency component (1) respectively correspond to two test pins of the connected IC chip (2); a first conductive band (9) connecting the corresponding test column (8) and the test position connection column (7) is also formed on the second insulating layer (4); The third insulating layer (5) is arranged on the second insulating layer (4) and forms an integral body, the third insulating layer (5) covers the first conductive band (9), the third insulating layer (5) is provided with third small holes (5-1) corresponding to and connected to four input and output pins of each IC chip (2), and the third small holes (5-1) are crystallized to form conductive pillars (10); the top of the conductive pillars (10) is higher than the third insulating layer (5); The fourth insulating layer (6) is arranged on the third insulating layer (5) and forms an integral body, and the fourth insulating layer (6) is flush with the top of the conductive pillar (10); and the fourth insulating layer (6) is provided with a second conductive band (11) corresponding to and conductively connected to each conductive pillar (10).

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