State self-locking circuit
By designing a state self-locking circuit including latch circuit and signal control circuit, using components such as MOS tubes and resistors, the problem of high circuit recovery cost and low versatility during processor restart is solved, and low cost is achieved. Circuit recovery effect without software cooperation.
Patent Information
- Application Number
- CN202323437360.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-15
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2033-12-15
AI Technical Summary
In the prior art, circuit recovery during processor restart requires complex software and hardware coordination, resulting in high cost and low versatility.
Design a state self-locking circuit, including a latch circuit, a first signal control circuit and a second signal control circuit, and connect components such as MOS tubes and resistors to realize the high-level state when the processor is restarted. Low cost and no software cooperation.
It realizes low-cost and highly versatile circuit recovery during the processor restart process. It connects to the signal control circuit through MOS tube Q1 and MOS tube Q3, latch the high voltage state when the power is turned on, and maintains the circuit state during the system restart, which is relatively costly. Low and no software cooperation is required.
Smart Images
Figure CN222147599U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electronic circuits, and more specifically to a state self-locking circuit. Background Art
[0002] During the restart process of existing processors such as the domestic Zhaoxin KX-6000G, the power of its working state will be completely lost. The restart process is equivalent to shutting down and restarting the hardware. Before this, OPS (Open Pluggable Specification) has always been detecting system power, and other platforms will not lose power in the working state during the restart process. Therefore, the existing technology usually uses MCU (Microcontroller Unit) programmable chips to write programs to achieve latch control of related signal states, so as to facilitate circuit recovery after the processor restarts. The use of MCU programmable chips requires coordination through complex software and hardware structures, with high application costs and low versatility. Utility Model Content
[0003] The technical problem to be solved by the utility model is to provide a state self-locking circuit in view of the above-mentioned defects of the prior art.
[0004] The technical solution adopted by the utility model to solve the technical problem is: a state self-locking circuit, including a latch circuit, a first signal control circuit and a second signal control circuit; the latch circuit includes a MOS tube Q1, a MOS tube Q3, a resistor R2, a resistor R5 and a resistor R6; the gate of the MOS tube Q1 is respectively connected to the drain of the MOS tube Q3 and the first signal control circuit; the drain of the MOS tube Q1 is respectively connected to one end of the resistor R5, the gate of the MOS tube Q3 and the second signal control circuit; the source of the MOS tube Q1 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the ALW end; the source of the MOS tube Q3 is connected to one end of the resistor R6; the other ends of the resistor R6 and the resistor R5 are both grounded.
[0005] In some embodiments, the first signal control circuit includes an input signal terminal, a MOS transistor Q2, a MOS transistor Q4, a resistor R1, a resistor R3 and a resistor R4; the drain of the MOS transistor Q2 is respectively connected to one end of the resistor R1 and one end of the resistor R4; the gate of the MOS transistor Q2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the VCC terminal; the other end of the resistor R1 is connected to the ALW terminal; the other end of the resistor R4 is respectively connected to the gate of the MOS transistor Q1 and the drain of the MOS transistor Q3; the source of the MOS transistor Q2 is connected to the drain of the MOS transistor Q4; the gate of the MOS transistor Q4 is respectively connected to the input signal terminal and the second signal control circuit; the source of the MOS transistor Q4 is grounded.
[0006] In some embodiments, the second signal control circuit includes a switching diode D1, a first output signal terminal, a second output signal terminal, a MOS transistor Q5, a MOS transistor Q6, a resistor R7 and a resistor R8; the cathode of the switching diode D1 is respectively connected to the gate of the MOS transistor Q4 and the input signal terminal; the anode of the switching diode D1 is respectively connected to the drain of the MOS transistor Q1, one end of the resistor R5, the gate of the MOS transistor Q3, one end of the resistor R7 and the first output signal terminal; the other end of the resistor R7 is connected to the gate of the MOS transistor Q5, and the drain of the MOS transistor Q5 is respectively connected to the drain of the MOS transistor Q6 and the second output signal terminal; the gate of the MOS transistor Q6 is connected to one end of the resistor R8, and the other end of the resistor R8 is connected to the VCC terminal; the sources of the MOS transistors Q5 and Q6 are both grounded.
[0007] In some embodiments, the MOS transistor Q1 is a P-channel MOS transistor; and the MOS transistor Q3 is an N-channel MOS transistor.
[0008] In some embodiments, the MOS transistor Q2 , the MOS transistor Q4 , the MOS transistor Q5 , and the MOS transistor Q6 are all N-channel MOS transistors.
[0009] In some embodiments, the MOS transistor Q1 , MOS transistor Q2 , MOS transistor Q3 , MOS transistor Q4 , MOS transistor Q5 , and MOS transistor Q6 are respectively connected in parallel with a parasitic diode.
[0010] In some embodiments, the parasitic diode is a Zener diode.
[0011] In some embodiments, the model of the MOS tube Q1 is CJ3401.
[0012] In some embodiments, the models of the MOS transistor Q2 , the MOS transistor Q3 , the MOS transistor Q4 , the MOS transistor Q5 and the MOS transistor Q6 are all 2N7002.
[0013] The beneficial effects of the utility model are as follows: different from the prior art, in the state self-locking circuit of the utility model, the latch circuit is mainly connected to the first signal control circuit and the second signal control circuit through the MOS tube Q1 and the MOS tube Q3; it is used to lock the high level state of the input voltage at the time of startup between the MOS tube Q1 and the MOS tube Q3 during the startup process of the processor restart; the circuit has low cost and does not require software cooperation, and has strong versatility. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 It is a schematic diagram of a state self-locking circuit in an embodiment of the utility model;
[0015] Names and numbers in the figure: latch circuit-10; first signal control circuit-20; second signal control circuit-30. DETAILED DESCRIPTION
[0016] In order to make the purpose, technical solutions and advantages of the embodiments of the utility model clearer, the technical solutions in the embodiments of the utility model will be clearly and completely described below. Obviously, the described embodiments are partial embodiments of the utility model, rather than all embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technical workers in this field without creative labor belong to the protection scope of the utility model. In addition, the directional terms mentioned in the utility model, such as "one end", "the other end", etc., are only referenced to the directions of the attached diagrams. The directional terms used are for better and clearer explanation and understanding of the utility model, rather than indicating or implying the orientation that the utility model must have, and therefore cannot be understood as limitations on the utility model.
[0017] The utility model is implemented as follows Figure 1 As shown in, a state self-locking circuit includes a latch circuit 10, a first signal control circuit 20 and a second signal control circuit 30; the latch circuit 10 includes a MOS tube Q1, a MOS tube Q3, a resistor R2, a resistor R5 and a resistor R6; the gate of the MOS tube Q1 is respectively connected to the drain of the MOS tube Q3 and the first signal control circuit 20; the drain of the MOS tube Q1 is respectively connected to one end of the resistor R5, the gate of the MOS tube Q3, and the second signal control circuit 30; the source of the MOS tube Q1 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the ALW end; the source of the MOS tube Q3 is connected to one end of the resistor R6; the other ends of the resistor R6 and the resistor R5 are both grounded.
[0018] Among them, the MOS tube Q1 is a P-channel MOS tube; the model of the MOS tube Q1 is CJ3401. The MOS tube Q3 is an N-channel MOS tube; the model of the MOS tube Q3 is 2N7002.
[0019] The first signal control circuit 20 includes an input signal terminal, a MOS transistor Q2, a MOS transistor Q4, a resistor R1, a resistor R3 and a resistor R4; the drain of the MOS transistor Q2 is connected to one end of the resistor R1 and one end of the resistor R4 respectively; the gate of the MOS transistor Q2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the VCC terminal; the other end of the resistor R1 is connected to the ALW terminal; the other end of the resistor R4 is connected to the gate of the MOS transistor Q1 and the drain of the MOS transistor Q3 respectively; the source of the MOS transistor Q2 is connected to the drain of the MOS transistor Q4; the gate of the MOS transistor Q4 is connected to the input signal terminal and the second signal control circuit 30 respectively; the source of the MOS transistor Q4 is grounded.
[0020] Among them, the MOS transistor Q2 and the MOS transistor Q4 are both N-channel MOS transistors; the models of the MOS transistor Q2 and the MOS transistor Q4 are both 2N7002. The input signal terminal is SPIO_PWRBTN, which is used to transmit the SPIO_PWRBTN signal.
[0021] The second signal control circuit 30 includes a switching diode D1, a first output signal terminal, a second output signal terminal, a MOS transistor Q5, a MOS transistor Q6, a resistor R7 and a resistor R8; the cathode of the switching diode D1 is respectively connected to the gate of the MOS transistor Q4 and the input signal terminal; the anode of the switching diode D1 is respectively connected to the drain of the MOS transistor Q1, one end of the resistor R5, the gate of the MOS transistor Q3, one end of the resistor R7 and the first output signal terminal; the other end of the resistor R7 is connected to the gate of the MOS transistor Q5, and the drain of the MOS transistor Q5 is respectively connected to the drain of the MOS transistor Q6 and the second output signal terminal; the gate of the MOS transistor Q6 is connected to one end of the resistor R8, and the other end of the resistor R8 is connected to the VCC terminal; the sources of the MOS transistors Q5 and Q6 are both grounded.
[0022] Among them, MOS transistor Q5 and MOS transistor Q6 are both N-channel MOS transistors; the models of MOS transistor Q5 and MOS transistor Q6 are both 2N7002. The first output signal terminal is SPIO_GP21, which is used to transmit the SPIO_GP21 signal. The second output signal terminal is PWR_STATUS, which is used to transmit the OPS_80PIN_PWR_STATUS signal.
[0023] In this embodiment, MOS transistor Q1, MOS transistor Q2, MOS transistor Q3, MOS transistor Q4, MOS transistor Q5 and MOS transistor Q6 are respectively connected in parallel with parasitic diodes, which are voltage regulator diodes.
[0024] In this embodiment, the ALW terminal is +3.3V_ALW, and the VCC terminal is VCC3.
[0025] The working principle is: during the boot process, VCC3 will pull up faster to turn on MOS tube Q6 and pull PWR_STATUS down, and the work of this circuit at this time is to lock the high level state of VCC3 at the boot to between MOS tube Q1 and MOS tube Q3. Process: When the power is turned on, the gates of MOS tube Q2 and MOS tube Q4 are high, MOS tube Q2 and MOS tube Q4 are turned on to pull the gate of MOS tube Q1 down, MOS tube Q1 is turned on, the gate of MOS tube Q3 is pulled up, MOS tube Q3 is turned on, and the gate of MOS tube Q1 will be pulled to the ground again. At this time, MOS tube Q2 and MOS tube Q4 are turned off, and the gate of MOS tube Q1 will not be pulled up, so as to achieve the purpose of state latching. At this time, the system restarts, VCC3 loses power, and the high state latched between MOS tube Q1 and MOS tube Q3 will turn on MOS tube Q5 and pull PWR_STATUS down.
[0026] During normal shutdown, SPIO_GP21 pulls down the gate of MOS tube Q3 to release the latched state. During forced shutdown, SPIO_PWRBTN pulls down the gate of MOS tube Q3 to release the latched state. This circuit has low cost and does not require software coordination, and has strong versatility.
[0027] It should be noted that when the state self-locking circuit of the embodiment of the utility model is applied, the system needs to turn off the quick start function.
[0028] It should be understood that ordinary technical workers in the field can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to the utility model.
Claims
1. A state self-locking circuit, Features: It includes a latch circuit, a first signal control circuit and a second signal control circuit; the latch circuit includes a MOS tube Q1, a MOS tube Q3, a resistor R2, a resistor R5 and a resistor R6; the gate of the MOS tube Q1 is respectively connected to the drain of the MOS tube Q3 and the first signal control circuit; the drain of the MOS tube Q1 is respectively connected to one end of the resistor R5, the gate of the MOS tube Q3 and the second signal control circuit; the source of the MOS tube Q1 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the ALW end; the source of the MOS tube Q3 is connected to one end of the resistor R6; the other ends of the resistor R6 and the resistor R5 are both grounded.
2. The state self-locking circuit according to claim 1, Features: The first signal control circuit includes an input signal terminal, a MOS tube Q2, a MOS tube Q4, a resistor R1, a resistor R3 and a resistor R4; the drain of the MOS tube Q2 is respectively connected to one end of the resistor R1 and one end of the resistor R4; the gate of the MOS tube Q2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the VCC terminal; the other end of the resistor R1 is connected to the ALW terminal; the other end of the resistor R4 is respectively connected to the gate of the MOS tube Q1 and the drain of the MOS tube Q3; the source of the MOS tube Q2 is connected to the drain of the MOS tube Q4; the gate of the MOS tube Q4 is respectively connected to the input signal terminal and the second signal control circuit; the source of the MOS tube Q4 is grounded.
3. The state self-locking circuit according to claim 2, Features: The second signal control circuit includes a switching diode D1, a first output signal terminal, a second output signal terminal, a MOS transistor Q5, a MOS transistor Q6, a resistor R7 and a resistor R8; the cathode of the switching diode D1 is respectively connected to the gate of the MOS transistor Q4 and the input signal terminal; the anode of the switching diode D1 is respectively connected to the drain of the MOS transistor Q1, one end of the resistor R5, the gate of the MOS transistor Q3, one end of the resistor R7 and the first output signal terminal; the other end of the resistor R7 is connected to the gate of the MOS transistor Q5, and the drain of the MOS transistor Q5 is respectively connected to the drain of the MOS transistor Q6 and the second output signal terminal; the gate of the MOS transistor Q6 is connected to one end of the resistor R8, and the other end of the resistor R8 is connected to the VCC terminal; the sources of the MOS transistors Q5 and Q6 are both grounded.
4. The state self-locking circuit according to any one of claims 1 to 3, Features: The MOS transistor Q1 is a P-channel MOS transistor; the MOS transistor Q3 is an N-channel MOS transistor.
5. The state self-locking circuit according to claim 3, Features: The MOS transistor Q2 , MOS transistor Q4 , MOS transistor Q5 and MOS transistor Q6 are all N-channel MOS transistors.
6. The state self-locking circuit according to claim 3, Features: The MOS transistor Q1 , MOS transistor Q2 , MOS transistor Q3 , MOS transistor Q4 , MOS transistor Q5 and MOS transistor Q6 are respectively connected in parallel with a parasitic diode.
7. The state self-locking circuit according to claim 6, Features: The parasitic diode is a voltage regulator diode.
8. The state self-locking circuit according to claim 1, Features: The model of the MOS tube Q1 is CJ3401.
9. The state self-locking circuit according to claim 3, Features: The models of the MOS tube Q2, MOS tube Q3, MOS tube Q4, MOS tube Q5 and MOS tube Q6 are all 2N7002.