Clock frequency multiplication sharing circuit applied to multiple wireless modules
By designing a clock frequency multiplication sharing circuit in the WIFI wireless multi-module system, the system bloat and high cost problems caused by multi-clock circuits are solved, and the clock signal saving and delay control are realized to ensure the normal operation of the circuit.
Patent Information
- Application Number
- CN202420277814.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-04
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2034-02-04
AI Technical Summary
In WIFI wireless multi-module system, setting up multiple clock circuits leads to bloated system circuits, high cost and occupies a lot of circuit board space.
Design a clock frequency multiplication sharing circuit, generate a 48MHz clock signal through the clock circuit, and transmit it to the second module after the frequency multiplication through the first module, and is electrically connected through the PCIe bus to realize the sharing of the clock signal. The first frequency is 48MHz, the second frequency is 96MHz.
It realizes the saving of clock signals, reduces the circuit cost and space occupied, and controls the delay time at the ms level, without affecting the normal operation of the circuit.
Smart Images
Figure CN222167498U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of circuits, and in particular to a clock frequency multiplication sharing circuit applied to wireless multi-modules. Background Art
[0002] The clock circuit is a basic component in the electronic circuit. When multiple WIFI wireless modules work at the same time, if multiple clock circuits are set, the system circuit will be bloated, and the high-cost circuit will occupy more circuit board space.
[0003] Therefore, the prior art has defects and needs to be improved. Utility Model Content
[0004] The utility model aims to overcome the shortcomings of the prior art and provide a clock frequency multiplication sharing circuit applied to wireless multi-modules.
[0005] The technical solution of the utility model is as follows: The utility model provides a clock multiplication sharing circuit applied to wireless multi-modules, including: a clock circuit, a first module and a second module, the clock circuit is electrically connected to the first module, the first module is electrically connected to the second module, the clock circuit is used to generate a clock signal of a first frequency to the first module, the first module processes the clock signal of the first frequency after receiving it and generates a clock signal of a second frequency to the second module, and the first frequency and the second frequency are not equal.
[0006] Further, the first frequency is 48 MHz, and the second frequency is 96 MHz.
[0007] Furthermore, the first module is also electrically connected to the second module via a PCIe bus.
[0008] Furthermore, the solution also includes a third module, which is electrically connected to the second module and receives a clock signal of a second frequency sent by the second module.
[0009] Furthermore, the first module is also electrically connected to the third module via a PCIe bus, and the second module is also electrically connected to the third module via a PCIe bus.
[0010] By adopting the above scheme, the beneficial effect of the utility model is that the clock signal of a clock circuit can be shared after being multiplied, which can save circuit board space and reduce circuit costs, and the delay time of the clock sharing circuit can be controlled at the ms level without affecting the normal operation of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 This is a structural block diagram of the first embodiment of the utility model.
[0012] Figure 2 This is a structural block diagram of the second embodiment of the utility model.
[0013] Figure 3 FIG. 4 is a circuit diagram of a clock circuit according to a third embodiment of the present invention.
[0014] Figure 4 This is a circuit diagram of the first module of the third embodiment of the utility model. DETAILED DESCRIPTION
[0015] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0016] Please refer to Figure 1 In the first embodiment of the present scheme, the utility model provides a clock frequency multiplication sharing circuit applied to wireless multi-modules, including: a clock circuit, a first module and a second module, the clock circuit is electrically connected to the first module, the first module is electrically connected to the second module, the clock circuit is used to generate a clock signal of a first frequency to the first module, the first module processes the clock signal of the first frequency after receiving it and generates a clock signal of a second frequency to the second module, and the first frequency and the second frequency are not equal, wherein the first frequency is 48MHz, the second frequency is 96MHz, and the first module multiplies the clock signal of the first frequency and sends it to the second module.
[0017] Furthermore, the first module is also electrically connected to the second module via a PCIe bus to achieve data transmission.
[0018] Please refer to Figure 2 In the second embodiment of the present scheme, the utility model provides a clock frequency multiplication sharing circuit applied to wireless multi-modules, including: a clock circuit, a first module, a second module and a third module, the clock circuit is electrically connected to the first module, the first module is electrically connected to the second module, the clock circuit is used to generate a clock signal of a first frequency to the first module, the first module processes the clock signal of the first frequency after receiving it and generates a clock signal of a second frequency to the second module, the third module is electrically connected to the second module, the third module receives the clock signal of the second frequency sent by the second module, and the first frequency and the second frequency are not equal, wherein the first frequency is 48MHz, the second frequency is 96MHz, the first module multiplies the clock signal of the first frequency and sends it to the second module, and the second module then sends the clock signal of the second frequency to the third module.
[0019] Furthermore, the first module is also electrically connected to the third module via a PCIe bus, and the second module is also electrically connected to the third module via a PCIe bus to achieve data transmission.
[0020] Please refer to Figure 3 and Figure 4 , in the third embodiment of this solution, Figure 3 The clock circuit generates a 48MHz clock signal, which is sent to the Figure 4 The first module in the circuit then generates a 96MHz clock signal by frequency multiplication and sends it to the next module through the CLK_OUTP and CLK_OUTN terminals.
[0021] In summary, the beneficial effects of this solution are: the clock signal of a clock circuit can be shared after multiplying, which can save circuit board space and reduce circuit costs, and the delay time of the clock sharing circuit can be controlled at the ms level without affecting the normal operation of the circuit.
[0022] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A clock frequency multiplication sharing circuit applied to wireless multi-modules, characterized in that: include: A clock circuit, a first module and a second module, wherein the clock circuit is electrically connected to the first module, and the first module is electrically connected to the second module, the clock circuit is used to generate a clock signal of a first frequency to the first module, and the first module processes the clock signal of the first frequency after receiving the clock signal to generate a clock signal of a second frequency to the second module, and the first frequency and the second frequency are not equal.
2. The clock frequency multiplication sharing circuit applied to wireless multi-modules according to claim 1, characterized in that: The first frequency is 48 MHz, and the second frequency is 96 MHz.
3. The clock frequency multiplication sharing circuit applied to wireless multi-modules according to claim 1 or 2, characterized in that: The system further includes a third module, which is electrically connected to the second module and receives a clock signal of a second frequency sent by the second module.
4. The clock frequency multiplication sharing circuit applied to wireless multi-modules according to claim 1 or 2, characterized in that: The first module is also electrically connected to the second module via a PCIe bus.
5. The clock frequency multiplication sharing circuit applied to wireless multi-modules according to claim 3, characterized in that: The first module is also electrically connected to the third module via a PCIe bus, and the second module is also electrically connected to the third module via a PCIe bus.