Adaptive capability testing device of memory

Abstract

The utility model relates to the technical field of servers, in particular to an adaptive capacity testing device for a memory, which comprises a memory slot used for carrying a memory to be tested; a to-be-tested memory carried by the memory slot is respectively connected with the main control chip and the BMC through the either-or switch chip, and the BMC is connected with a control port of the either-or switch chip; the IO interface of the main control chip is connected with the BMC; the BMC is connected with the complex programmable logic device through an I2C line; the memory slot is connected with a power supply, and a power supply switch is connected in series between the memory slot and the power supply. According to the utility model, the reliability of memory adaptation capability detection is improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of servers, and in particular relates to a device for testing the adaptability of a memory. Background Art

[0002] Memories can be divided into volatile memories and non-volatile memories based on whether they retain the stored information after power failure. Read-only memory (ROM) is the main non-volatile memory. Its characteristic is that once data is stored in it, it cannot be rewritten or deleted, but the stored content will not be lost when the power is turned off.

[0003] As an electrically erasable programmable read-only memory, Flash memory can not only perform erasing and programming operations, but also has non-volatility and can quickly read data. The Flash memories that currently occupy the mainstream market are divided into NOR Flash and NAND Flash. NOR Flash has a faster reading speed and is often used to store system firmware, boot programs and operating systems. NAND Flash has a faster writing speed and is often used to store large amounts of data, such as images, audio and video files.

[0004] In the server field, NOR Flash is usually used to store the boot code of the main control chip, initialize the relevant hardware configuration, and implement the corresponding functional logic. Therefore, the main control chip needs to be adapted to NOR Flash before it can be used normally. Usually, chip manufacturers will list the Flash models that the chip is adapted to in the AVL list. However, in actual use, the NOR Flash in the AVL list may have EOL or delivery delay. At this time, we need to adapt the NOR Flash of the main control chip by ourselves. Faced with various NOR Flashes of different packages and different manufacturers, the flying wire method is usually used to connect the SPI bus of the main control board to the NOR Flash to be adapted. If the adaptation fails, the flying wire needs to be re-flying, which is time-consuming and labor-intensive, and the effect is not ideal. In addition, multiple flying wire operations need to be performed on the board. Improper operation can easily cause the board to short-circuit and burn the board. Utility Model Content

[0005] In view of the above-mentioned deficiencies in the prior art, the utility model provides a memory adaptability testing device to solve the above-mentioned technical problems.

[0006] The utility model provides a memory adaptability testing device, comprising:

[0007] A memory slot, wherein the memory slot is used to carry a memory to be tested; the memory to be tested carried by the memory slot is respectively connected to a main control chip and a BMC through a two-choice switch chip, and the BMC is connected to a control port of the two-choice switch chip; the IO interface of the main control chip is connected to the BMC; the BMC is connected to a complex programmable logic device through an I2C line; the memory slot is connected to a power supply, and a power switch is connected in series between the memory slot and the power supply.

[0008] In an optional embodiment, it includes multiple memory slots, multiple memory slots are equipped with multiple memories, the SPI bus ports of the multiple memories are all connected to the output end of the two-to-one switch chip, one input end of the two-to-one switch chip is connected to the SPI interface of the main control chip, and the other input end of the two-to-one switch chip is connected to the SPI interface of the BMC.

[0009] In an optional embodiment, the BMC is connected to the first input end of the two-to-one switch chip through a synchronous serial signal line, the main control chip is connected to the second input end of the two-to-one switch chip through a synchronous serial signal line, and the output end of the two-to-one switch chip is connected to multiple memory slots through a synchronous serial signal line.

[0010] In an optional embodiment, the memory slot is connected to a first power supply via a first line, the memory slot is connected to a second power supply via a second line, a first pin switch is connected in series on the first line, and a second pin switch is connected in series on the second line.

[0011] In an optional implementation, the first power supply is a 3.3V power supply, and the second power supply is a 1.8V power supply.

[0012] In an optional implementation, the BMC is connected to an auxiliary chip via an I2C line, and an IO pin of the auxiliary chip is connected to a power interface of a memory slot.

[0013] In an optional embodiment, the auxiliary chip is electrically connected to the LED lamp.

[0014] In an optional implementation, the auxiliary chip is a CA9555 chip.

[0015] In an optional implementation, the BMC is connected to the target selection chip via three IO pins.

[0016] In an optional embodiment, a plurality of output branches of the two-choose-one switch chip connected to the memory to be tested are each provided with a switch chip; a plurality of pins of the target selection chip are respectively connected to the control terminals of the corresponding switch chips.

[0017] The beneficial effect of the utility model is that the memory adaptability testing device provided by the utility model, by constructing a connection topology among the BMC, the main control chip, the target selection chip and the memory to be tested, distinguishes the situation where the Flash chip fails to be erased and written and causes the failure to adapt to the main control chip, eliminates the result that the Flash model is incompatible with the main control chip in this situation, and improves the reliability of the detection.

[0018] In addition, the utility model has a reliable design principle, a simple structure and a very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 The figure is a schematic architecture diagram of a memory adaptability testing device according to an embodiment of the present invention.

[0021] Figure 2 It is a schematic principle diagram of the status display of a memory adaptability testing device according to an embodiment of the utility model.

[0022] Figure 3 A flow chart of the testing process of a memory adaptability testing device provided in an embodiment of the utility model. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0025] The key terms appearing in the present invention are explained below.

[0026] BMC, the server remote management controller, is called Baseboard Management Controller in English. It can perform firmware upgrades, check machine equipment, and other operations on the machine when the machine is not turned on. Fully implementing IPMI functions in BMC requires a powerful 16-bit or 32-bit microcontroller, RAM for data storage, flash memory for non-volatile data storage, and firmware, which can provide basic remote manageability in terms of safe remote restart, safe power-on, LAN warning, and system health monitoring. In addition to basic IPMI functions and system operation monitoring functions, mBMC can also realize the selection and protection of BIOS fast components by using one of the two flash memories to store the previous BIOS. For example, when the system cannot be started after a remote BIOS upgrade, the remote administrator can switch back to the previously working BIOS image to start the system. Once the BIOS is upgraded, the BIOS image can also be locked to effectively prevent viruses from invading it.

[0027] The I2C bus is a simple, bidirectional, two-wire synchronous serial bus developed by Philips. It only requires two wires to transmit information between devices connected to the bus. The master device is used to start the bus to transmit data and generate a clock to open the transmitting device. At this time, any addressed device is considered a slave device. The relationship between the master and slave, send and receive on the bus is not constant, but depends on the direction of data transmission at this time. If the host wants to send data to the slave device, the host first addresses the slave device, then actively sends data to the slave device, and finally the host terminates the data transmission; if the host wants to receive data from the slave device, the master device first addresses the slave device. Then the host receives the data sent by the slave device, and finally the host terminates the receiving process. In this case, the host is responsible for generating a timing clock and terminating data transmission.

[0028] BIOS is the abbreviation of "Basic Input Output System". The Chinese name is "Basic Input Output System". On IBM PC compatible systems, it is an industry-standard firmware interface. It is a set of programs fixed to a ROM chip on the motherboard of the computer. It stores the most important basic input and output programs of the computer, the self-test program after power-on, and the system self-starting program. It can read and write specific information of system settings from CMOS. Its main function is to provide the lowest-level and most direct hardware settings and control for the computer. In addition, BIOS also provides some system parameters to the operating system. Changes in system hardware are hidden by BIOS, and programs use BIOS functions instead of directly controlling hardware. Modern operating systems ignore the abstraction layer provided by BIOS and directly control hardware components.

[0029] The central processing unit (CPU) is the computing and control core of the computer system and is the final execution module for information processing and program running.

[0030] For details, please refer to Figure 1 , the memory adaptability testing device comprises:

[0031] The memory slot is used to carry the memory to be tested; the memory to be tested carried by the memory slot is connected to the main control chip and the BMC respectively through a two-choice switch chip, and the BMC is connected to the control port of the two-choice switch chip; the IO interface of the main control chip is connected to the BMC; the BMC is connected to the target selection chip, and the target selection chip is connected to the memory to be tested carried by the memory slot; the BMC is connected to the complex programmable logic device through the I2C line; the memory slot is connected to the power supply, and a power switch is connected in series between the memory slot and the power supply.

[0032] Specifically, the main control chip and BMC use the SPI bus to adapt to the Flash. When the device is not powered on, put the Flash chip to be tested into the memory slot (Flash Socket). There are many types of NOR Flash chips with different packages and different manufacturers. Commonly used packages in the server field include SOP, BGA, WSON, etc. In order to facilitate replacement and use, the Flash Sockets corresponding to several commonly used packages are designed in the detection device. Each time the test is performed, the Flash chip to be tested can be placed in the Flash Socket.

[0033] According to the model of the Flash chip to be tested, the corresponding power supply voltage is selected. The specific power supply topology includes: the memory slot is connected to the first power supply through the first line, the memory slot is connected to the second power supply through the second line, the first line is connected in series with a first pin switch, and the second line is connected in series with a second pin switch. The first power supply is a 3.3V power supply, and the second power supply is a 1.8V power supply.

[0034] Different types of Flash have different power supply voltages. Commonly used NOR Flash power supply voltages are 3.3V and 1.8V. The power supply voltage corresponding to the Flash is selected through the pin. For sockets without Flash chips, no pins are placed.

[0035] When the device is powered on, the BMC detects the number of Flash chips to be adapted through the auxiliary chip, such as Figure 2As shown. The BMC is connected to the auxiliary chip through the I2C line, and the IO pins of the auxiliary chip are connected to the power interface of the memory slot. The pins of the auxiliary chip are connected to the LED light. The auxiliary chip uses the CA9555 chip. The BMC detects the number of Flash chips to be adapted through the I2C bus according to whether the Flash Socket is powered.

[0036] The BMC chip controls the two-choice switch chip to switch channels. At this time, the BMC connects itself to the memory under test and obtains control of the memory under test. The firmware stored in the BMC system is erased and written to the Flash program through the SPI bus using the MDI interface, and the flag indicating whether the erase is successful is written into the register of the complex programmable logic device (CPLD) through the I2C bus.

[0037] Specifically, the target selection chip (74HC138 chip) includes multiple execution pins, and the multiple execution pins are respectively connected to the control end of the corresponding switch chip. When executing erase, the BMC controls the 74HC138 chip through three IO pins, and controls the 74HC138 chip to turn on the switch chip of the target memory to be tested, and turn off other switch chips, so that it only erases one Flash chip each time. After the BMC successfully records the erase flag of the current Flash chip, it detects whether the current Flash fails to erase. If the erase fails and the number of times is less than 3 times, the result that the Flash model is incompatible with the main control chip is excluded, and the material is replaced to join the next round of detection. If the number of erase failures exceeds 2 times, it is considered that the Flash chip is incompatible.

[0038] If the current Flash is successfully erased and it is confirmed that there are still Flash chips to be adapted that have not been erased, the 74HC138 chip is controlled to enable the next Flash chip to erase the Flash program. After all the erasures are completed, the BMC controls the LED to light up through I2C, indicating that all erasures are completed.

[0039] After all BMCs are erased, the two-choice switch chip is controlled to switch channels. At this time, the main control chip loads the firmware program of the current Flash chip through the SPI bus. After the main control chip is adapted, the adaptation information is passed to the BMC through the IO pin. Similarly, the BMC writes the adaptation information into the CPLD register through the IIC bus.

[0040] After the BMC successfully records the adaptation information of the current Flash chip, it controls the 74HC138 chip to switch to the next Flash chip until all the Flash chips to be tested are adapted. The LED is lit through the IIC bus, indicating that the Flash chips to be tested have been adapted and the detection is completed.

[0041] Use the MDI interface to view the CPLD registers in the BMC system to confirm the adaptation result of the Flash chip, and select the successfully adapted Flash chip for material preparation and board investment.

[0042] Please refer to Figure 3 The memory adaptability testing device provided in this embodiment performs the following process:

[0043] (1) The device is not powered on. Place the Flash chip to be tested into the Flash Socket.

[0044] (2) Select the corresponding power supply voltage according to the Flash chip model to be tested;

[0045] (3) After the device is powered on, the number of Flash chips to be adapted is detected;

[0046] (4) Use the firmware stored in the BMC to erase the Flash program online;

[0047] (5) BMC determines whether the firmware program of the Flash chip is successfully erased;

[0048] (6) Record the erase flag of the current Flash chip and determine whether the erase is successful. If the erase fails and the number of times is less than 3, replace the material and join the next round of testing. If the erase is successful or the erase fails more than 2 times (if the erase fails more than 2 times, it is considered unmatched), proceed to step (7);

[0049] (7) Determine whether all the Flash chips to be tested have been erased (excluding the Flash chips that failed to be erased). If not, repeat steps (4) to (7). If all the Flash chips have been erased, proceed to step (8).

[0050] (8) The main control chip loads the firmware program and adapts the Flash chip;

[0051] (9) The main control chip determines whether the Flash is successfully adapted;

[0052] (10) Record the current Flash chip's adaptation information and determine whether all the Flash chips to be tested are adapted (excluding the Flash chips that failed to be erased). If not all are adapted, repeat steps (8) to (10). If all are adapted, the test is completed.

[0053] (11) Check the recorded erase flag and adaptation information, confirm the test results, and repeat steps (1) to (11) until the adaptation status of all Flash chips is confirmed.

[0054] Although the present invention is described in detail by referring to the accompanying drawings and in combination with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, a person skilled in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions shall be within the scope of the present invention. Any person skilled in the art who is familiar with the present technical field may easily think of changes or substitutions within the technical scope disclosed in the present invention, and these shall be within the scope of protection of the present invention.

Claims

1. A memory adaptability testing device, characterized in that: include: A memory slot, wherein the memory slot is used to carry a memory to be tested; the memory to be tested carried by the memory slot is respectively connected to a main control chip and a BMC through a two-choice switch chip, and the BMC is connected to a control port of the two-choice switch chip; the IO interface of the main control chip is connected to the BMC; the BMC is connected to a complex programmable logic device through an I2C line; the memory slot is connected to a power supply, and a power switch is connected in series between the memory slot and the power supply.

2. The memory adaptability testing device according to claim 1, characterized in that: It includes multiple memory slots, multiple memory slots are equipped with multiple memories, SPI bus ports of multiple memories are connected to the output end of the two-to-one switch chip, one input end of the two-to-one switch chip is connected to the SPI interface of the main control chip, and the other input end of the two-to-one switch chip is connected to the SPI interface of the BMC.

3. The memory adaptability testing device according to claim 2, characterized in that: The BMC is connected to the first input end of the two-to-one switch chip through a synchronous serial signal line, the main control chip is connected to the second input end of the two-to-one switch chip through a synchronous serial signal line, and the output end of the two-to-one switch chip is connected to multiple memory slots through a synchronous serial signal line.

4. The memory adaptability testing device according to claim 1, characterized in that: The memory slot is connected to a first power supply via a first line, and the memory slot is connected to a second power supply via a second line. A first pin switch is connected in series to the first line, and a second pin switch is connected in series to the second line.

5. The memory adaptability testing device according to claim 4, characterized in that: The first power supply is a 3.3V power supply, and the second power supply is a 1.8V power supply.

6. The memory adaptability testing device according to claim 1, characterized in that: The BMC is connected to an auxiliary chip via an I2C line, and an IO pin of the auxiliary chip is connected to a power interface of a memory slot.

7. The memory adaptability testing device according to claim 6, characterized in that: The auxiliary chip is electrically connected to the LED lamp.

8. The memory adaptability testing device according to claim 7, characterized in that: The auxiliary chip adopts CA9555 chip.

9. The memory adaptability testing device according to claim 2, characterized in that: The BMC is connected to the target selection chip via three IO pins.

10. The memory adaptability testing device according to claim 9, characterized in that: A plurality of output branches of the two-select-one switch chip connected to the memory to be tested are all provided with switch chips; a plurality of pins of the target selection chip are respectively connected to the control terminals of the corresponding switch chips.

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