Multilayer ceramic capacitor

Abstract

The utility model provides a laminated ceramic capacitor which can realize miniaturization and simultaneously considers large capacitance and reliability. A laminated ceramic capacitor (1) is provided with: a laminated body (2) including an effective part (16) in which a plurality of internal electrode layers (15) face each other with the dielectric layers (14) interposed therebetween in a lamination direction (Z) in which the dielectric layers (14) and the internal electrode layers (15) are laminated; and a pair of external electrodes (3) disposed on the surface of the laminated body (2) and connected to the internal electrode layers (15), in the laminated ceramic capacitor, when the effective part (16) is divided into three regions by trisecting the effective part (16) in the lamination direction (Z), the external electrodes (3) are connected to the internal electrode layers (15). The grain diameter (D50) of the crystal grains constituting the dielectric layer (14) in the middle region (16b) of the effective part (16) is larger than the grain diameter (D50) of the crystal grains constituting the dielectric layer (14) in the other two regions.

Description

Technical Field

[0001] The utility model relates to a stacked ceramic capacitor. Background Art

[0002] In the past, the laminated ceramic capacitors widely used in electronic devices such as mobile phones and portable music players have: an inner layer portion, which is formed by laminating multiple dielectric layers and multiple internal electrode layers made of ceramic materials to form an electrostatic capacitor; an outer layer portion, which is arranged on both sides of the inner layer portion in the lamination direction; and a side edge portion, which is arranged on both sides of the width direction of the inner layer portion. In addition, with the recent performance improvement and miniaturization of electronic devices, laminated ceramic capacitors are also required to have higher capacitance and smaller size.

[0003] One of the methods for obtaining a dielectric layer with a high dielectric constant in order to increase the capacitance of a multilayer ceramic capacitor is to grow ceramic particles (crystal grains) (for example, Patent Document 1).

[0004] On the other hand, in a multilayer ceramic capacitor in which dielectric layers and internal electrode layers are thinned in response to a demand for miniaturization of multilayer ceramic capacitors, there is a problem that the dielectric layer becomes locally thinner during grain growth, and insulation and moisture resistance are reduced, thereby reducing reliability.

[0005] Therefore, there is a demand for a multilayer ceramic capacitor that can achieve both high capacitance and reliability while achieving miniaturization.

[0006] Prior Art Literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2014-210685 Utility Model Content

[0009] Problems to be solved by utility models

[0010] An object of the present invention is to provide a multilayer ceramic capacitor that can achieve both large capacitance and reliability while achieving miniaturization.

[0011] Technical solutions to solve problems

[0012] The inventors of the present utility model discovered the following fact and finally completed the utility model, namely, when the effective part constituting the stacked ceramic capacitor is divided into three regions by three equal parts in the stacking direction, the grain size of the dielectric layer in the middle region is made larger than the grain size of the dielectric layer in the other two regions, thereby achieving both large capacitance and reliability while miniaturizing the stacked ceramic capacitor.

[0013] That is, the utility model is a laminated ceramic capacitor, comprising: a laminated body including an effective portion in which a plurality of internal electrode layers are opposed to each other with the dielectric layers interposed therebetween in a lamination direction of dielectric layers and internal electrode layers; and a pair of external electrodes arranged on a surface of the laminated body and connected to the internal electrode layers. In the laminated ceramic capacitor,

[0014] When the effective portion is divided into three equal parts in the stacking direction,

[0015] The grain size D50 of the crystal grains constituting the dielectric layer in the middle region of the effective portion is larger than the grain size D50 of the crystal grains constituting the dielectric layer in the other two regions.

[0016] Utility Model Effect

[0017] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can achieve both large capacitance and reliability while achieving miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 1 is a diagram showing the appearance of the multilayer ceramic capacitor 1 .

[0019] Figure 2 It is along Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II.

[0020] Figure 3 It is along Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III.

[0021] Figure 4(a) and Figure 4(b) are Figure 2 The A part and the B part are enlarged views, wherein FIG4(a) is an enlarged view of the A part, and FIG4(b) is an enlarged view of the B part.

[0022] Figure 5(a) to Figure 5(d) The diagrams are for explaining the manufacturing process of the multilayer ceramic capacitor 1 .

[0023] Description of Reference Numerals

[0024] 1: Multilayer ceramic capacitor;

[0025] 2: laminate;

[0026] 2a: main surface;

[0027] 2b: lateral view;

[0028] 2c: end face;

[0029] 3: External electrode;

[0030] 11: inner layer;

[0031] 12: outer layer;

[0032] 13: lateral clearance;

[0033] 14: dielectric layer;

[0034] 15: internal electrode layer;

[0035] 16: effective part;

[0036] 16a: upper region;

[0037] 16b: middle zone;

[0038] 16c: lower region;

[0039] 17: end gap;

[0040] 20: grain;

[0041] 20a: Area;

[0042] 30: base electrode layer;

[0043] 31: Plating layer. DETAILED DESCRIPTION

[0044] Hereinafter, a multilayer ceramic capacitor 1 is described as an embodiment of the present invention, but the present invention is not limited thereto. In addition, in order to explain the contents of the utility model, the drawings are sometimes simplified and drawn schematically, and sometimes the ratio of the dimensions of the drawn components or components is inconsistent with the ratio of these dimensions described in the specification. In addition, there are cases where the components described in the specification are omitted in the drawings or the number of components is omitted and drawn.

[0045] Figure 1 It is a schematic perspective view of the multilayer ceramic capacitor 1 . Figure 2 is a multilayer ceramic capacitor 1 along Figure 1 Cross-sectional view along line II-II. Figure 3 is a multilayer ceramic capacitor 1 along Figure 1 Figure 4(a) and Figure 4(b) are cross-sectional views of the III-III line in FIG. Figure 2 The state diagram of part A and part B is enlarged. In addition, Figure 2 The section shown is also called the XZ section. Figure 3 The section shown is also called a YZ section.

[0046] The multilayer ceramic capacitor 1 is substantially in the shape of a rectangular parallelepiped and includes a multilayer body 2 and a pair of external electrodes 3 provided at both ends of the multilayer body 2. The multilayer body 2 includes an inner layer portion 11 in which a dielectric layer 14 and an internal electrode layer 15 are stacked.

[0047] In the following description, as terms indicating the orientation of the multilayer ceramic capacitor 1, in the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided is referred to as the length direction X. The direction in which the dielectric layer 14 and the internal electrode layer 15 are stacked is referred to as the stacking direction Z. The direction intersecting both the length direction X and the stacking direction Z is referred to as the width direction Y. In the embodiment, the width direction Y is orthogonal to both the length direction X and the stacking direction Z.

[0048] (Outer surface of laminate 2)

[0049] In addition, among the six outer surfaces of the stacked body 2, a pair of outer surfaces that are opposite to each other in the stacking direction Z are referred to as the first main surface 2a1 and the second main surface 2a2, a pair of outer surfaces that are opposite to each other in the width direction Y are referred to as the first side surface 2b1 and the second side surface 2b2, and a pair of outer surfaces that are opposite to each other in the length direction X are referred to as the first end surface 2c1 and the second end surface 2c2. In addition, when it is not necessary to distinguish the first main surface 2a1 and the second main surface 2a2 in particular, they are collectively referred to as the main surface 2a in the description, when it is not necessary to distinguish the first side surface 2b1 and the second side surface 2b2 in the description, they are collectively referred to as the side surface 2b in the description, and when it is not necessary to distinguish the first end surface 2c1 and the second end surface 2c2 in particular, they are collectively referred to as the end surface 2c in the description.

[0050] The laminate 2 preferably has rounded edges R1 including corners. The edges R1 are where two surfaces of the laminate 2 (i.e., the main surface 2a and the side surface 2b, the main surface 2a and the end surface 2c, or the side surface 2b and the end surface 2c) intersect.

[0051] (Laminate 2)

[0052] The laminate 2 includes an inner layer portion 11 forming an electrostatic capacitor, outer layer portions 12 arranged on both sides of the inner layer portion 11 in a lamination direction Z, and side gap portions 13 arranged on both sides of the inner layer portion 11 in a width direction Y.

[0053] (Inner layer portion 11)

[0054] The inner layer portion 11 includes dielectric layers 14 and internal electrode layers 15 alternately stacked along the stacking direction Z. In addition, the inner layer portion 11 includes: an effective portion 16, in which a first opposing portion 152a and a second opposing portion 152b of an internal electrode layer 15 described later are opposed to each other via the dielectric layer 14; a first end gap portion 17a, in which a first lead portion 151a of an internal electrode layer 15 described later is opposed to each other via the dielectric layer 14; and a second end gap portion 17b, in which a second lead portion 151b of the internal electrode layer 15 is opposed to each other via the dielectric layer 14.

[0055] (Dielectric layer 14)

[0056] The dielectric layer 14 is made of a ceramic material. As the ceramic material, for example, a dielectric ceramic containing BaTiO3 as a main component can be used.

[0057] (Internal Electrode Layer 15)

[0058] The internal electrode layer 15 includes a plurality of first internal electrode layers 15a and a plurality of second internal electrode layers 15b. The first internal electrode layers 15a and the second internal electrode layers 15b are arranged alternately. The first internal electrode layer 15a includes a first opposing portion 152a opposed to the second internal electrode layer 15b and a first lead portion 151a led from the first opposing portion 152a to the first end face 2c1. The end of the first lead portion 151a is exposed at the first end face 2c1 and is electrically connected to the first external electrode 3a described later. The second internal electrode layer 15b includes a second opposing portion 152b opposed to the first internal electrode layer 15a and a second lead portion 151b led from the second opposing portion 152b to the second end face 2c2. The end of the second lead portion 151b is electrically connected to the second external electrode 3b described later. Electric charges are accumulated in the first opposing portion 152a of the first internal electrode layer 15a and the second opposing portion 152b of the second internal electrode layer 15b.

[0059] The internal electrode layer 15 is preferably formed of a metal material represented by, for example, nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), a silver-palladium (Ag-Pd) alloy, gold (Au), or the like.

[0060] (Outer layer 12)

[0061] The outer layer portion 12 includes a first outer layer portion 12a and a second outer layer portion 12b arranged to sandwich the inner layer portion 11 from the stacking direction Z. The first outer layer portion 12a forms a first main surface 2a1 of the multilayer ceramic capacitor 1, and the second outer layer portion 12b forms a second main surface 2a2 of the multilayer ceramic capacitor 1.

[0062] The outer layer portion 12 can be formed of the same material as the dielectric layer 14 of the inner layer portion 11 .

[0063] (Side gap 13)

[0064] The side gap 13 includes a first side gap 13a and a second side gap 13b which are arranged to sandwich the inner layer portion 11 from the width direction Y. The first side gap 13a forms a first side surface 2b1 of the multilayer ceramic capacitor 1, and the second side gap 13b forms a second side surface 2b2 of the multilayer ceramic capacitor 1. The side gap 13 can be formed of the same material as the dielectric layer 14.

[0065] (Determination of particle size D50)

[0066] The particle size D50 can be measured, for example, by the following method. The multilayer ceramic capacitor 1 is vertically erected so that the first side surface 2b1 is exposed, and the periphery of the multilayer ceramic capacitor 1 is fixed with resin. Then, the multilayer ceramic capacitor 1 is ground to a height approximately in the center by a grinder. A scanning electron microscope (SEM) photograph of the obtained cross section is taken at a magnification of 10,000 times, and the D50 of the grain is calculated using image processing software.

[0067] In addition, D50 is the diameter of a circle of equal area that becomes 50% of the cumulative distribution of the diameters of equal area circles of the crystal grains based on the number of grains.

[0068] In addition, in the SEM photograph, the SEM photograph can be binarized according to a given threshold value and only crystal grains can be extracted to evaluate their grain sizes (circle diameters of equal area).

[0069] The effective portion 16 is divided into three equal parts in the stacking direction Z, and divided into three regions, namely, the upper region 16a, the middle region 16b, and the lower region 16c, from the top. At this time, the grain size D50 of the grains 20 constituting the dielectric layer 14 in the middle region 16b is larger than the grain size D50 of the grains 20 constituting the dielectric layer 14 in the other two regions (i.e., the upper region 16a or the lower region 16c). FIG. 4(a) shows the effect of dividing the effective portion 16 into three equal parts, namely, the upper region 16a, the middle region 16b, and the lower region 16c. Figure 2 FIG. 4( b ) shows an enlarged state of the upper region 16 a of the effective portion 16. Figure 2 4(a) and 4(b) show the portion A of the upper region 16a of the effective portion 16 and the portion B of the middle region 16b in comparison, but it can be confirmed that the lower region 16c of the effective portion 16 is substantially the same as the upper region 16a.

[0070] By making the crystal grains 20 of the dielectric layer 14 in the middle region 16 b larger than the crystal grains 20 of the dielectric layer 14 in the other two regions, it is possible to achieve both increased capacitance and reliability when miniaturizing the multilayer ceramic capacitor.

[0071] The grain size D50 of the grains 20 constituting the dielectric layer 14 in the middle region 16b is preferably not less than 2 times and not more than 20 times the grain size D50 of the grains constituting the dielectric layer 14 in the other two regions. When the grain size D50 of the grains 20 constituting the dielectric layer 14 in the middle region 16b is not less than 2 times and not more than 20 times the grain size D50 of the grains constituting the dielectric layer 14 in the other two regions, even when the multilayer ceramic capacitor is miniaturized, a large capacitance can be maintained, and insulation and moisture resistance can be maintained, and reliability can be maintained.

[0072] The dielectric layer 14 in the middle region 16b includes a region 20a in which the number of crystal grains 20 forming one layer of the dielectric layer 14 is one when viewed in the stacking direction Z. As shown in FIG4(b), in the region 20a of the dielectric layer 14 in the middle region 16b, the number of crystal grains forming one layer of the dielectric layer 14 is one when viewed in the stacking direction Z. By providing such a region 20a in the middle region 16b, a large capacitance can be maintained even when the multilayer ceramic capacitor 1 is miniaturized.

[0073] (External electrode 3)

[0074] The external electrode 3 includes a first external electrode 3a provided on the first end surface 2c1 and a second external electrode 3b provided on the second end surface 2c2. The external electrode 3 covers not only the end surface 2c but also a part of the main surface 2a and the side surface 2b continuous with the end surface 2c.

[0075] As described above, the end of the first lead portion 151a of the first internal electrode layer 15a is exposed at the first end surface 2c1 and is electrically connected to the first external electrode 3a. In addition, the end of the second lead portion 151b of the second internal electrode layer 15b is exposed at the second end surface 2c2 and is electrically connected to the second external electrode 3b. Thus, a structure in which a plurality of capacitor elements are electrically connected in parallel is formed between the first external electrode 3a and the second external electrode 3b.

[0076] The external electrode 3 includes, for example, a base electrode layer 30 and a plating layer 31. The external electrode 3 does not necessarily have to have such a layered structure.

[0077] The base electrode layer 30 is formed by, for example, applying and baking a conductive paste containing copper (Cu). Alternatively, the base electrode layer 30 may contain glass.

[0078] The plating layer 31 includes a nickel (Ni) plating layer 31a disposed on the surface of the base electrode layer 30 and a tin (Sn) plating layer 31b disposed on the surface of the nickel (Ni) plating layer 31a. The structure of the plating layer 31 is not limited thereto.

[0079] (Method for Manufacturing Multilayer Ceramic Capacitor 1)

[0080] use Figure 5(a) to Figure 5(d) A method for manufacturing the multilayer ceramic capacitor 1 will be described.

[0081] A ceramic slurry containing ceramic powder, a binder and a solvent is formed into a sheet on the surface of a carrier film by a die coater, a gravure coater, a micro gravure coater or the like, thereby producing a laminated ceramic green sheet 101 to be the dielectric layer 14. Next, a conductor paste is printed in a strip shape on the laminated ceramic green sheet 101 by screen printing, inkjet printing, gravure printing or the like, and a conductive pattern 102 to be the internal electrode layer 15 is printed on the surface of the laminated ceramic green sheet 101, thereby producing a raw material sheet 103.

[0082] Next, as shown in FIG5(a), a plurality of green sheets 103 are stacked so that the conductive patterns 102 face the same direction and the conductive patterns 102 are staggered by half a pitch in the length direction between adjacent green sheets 103. Furthermore, ceramic green sheets 112 for the outer layer portion, which will become the outer layer portion 12, are stacked on both sides of the stacked green sheets 103.

[0083] The stacked plurality of raw material sheets 103 and the outer layer ceramic green sheets 112 are bonded by thermal compression to produce a mother block 110 as shown in FIG. 5( b ).

[0084] Next, the mother block 110 is cut along the cutting line x shown in FIG. 5( b ) and the cutting line y intersecting the cutting line x, thereby manufacturing a plurality of laminated bodies 2 shown in FIG. 5( c ).

[0085] According to the above process, the outer layer portion 12 and the side gap portion 13 can be formed at the same time as the laminate 2 is formed. However, it is also possible to form the laminate 2 by cutting from the mother block member, so that the inner layer portion 11 with the ends of the internal electrode layer 15 in the width direction Y exposed on both sides is first formed, and then the side gap portion 13 is adhered to both sides of the inner layer portion 11 so as to cover the exposed ends of the internal electrode layer 15. In this case, the side gap portion 13 to be adhered can use the same dielectric ceramic material as the dielectric layer 14. In addition, the side gap portion 13 can also be formed by applying a ceramic paste on both sides of the inner layer portion 11.

[0086] Next, a conductive paste containing copper (Cu) is applied and sintered on the end faces 2c of the stack 2, thereby forming a base electrode layer 30. The base electrode layer 30 is formed to not only cover the end faces 2c on both sides of the stack 2, but also to extend to the main surface 2a side and the side surface 2b side of the stack 2 to cover a portion of the end face 2c side of the main surface 2a.

[0087] Next, a nickel (Ni) plating layer 31a is formed on the surface of the base electrode layer 30, and a tin (Sn) plating layer 31b is formed on the surface of the nickel (Ni) plating layer 31a, thereby manufacturing the multilayer ceramic capacitor 1 shown in FIG. 5(d).

[0088] As mentioned above, although embodiment of this invention was described, this invention is not limited to embodiment, It can implement in various forms within the range which does not deviate from the summary of this invention.

Claims

1. A laminated ceramic capacitor comprising: a laminate including an effective portion in which a plurality of internal electrode layers are opposed to each other with the dielectric layers interposed therebetween in a lamination direction of dielectric layers and internal electrode layers; and a pair of external electrodes arranged on a surface of the laminate and connected to the internal electrode layers, characterized in that: When the effective portion is divided into three equal parts in the stacking direction, The grain size D50 of the crystal grains constituting the dielectric layer in the middle region of the effective portion is larger than the grain size D50 of the crystal grains constituting the dielectric layer in the other two regions.

2. The multilayer ceramic capacitor according to claim 1, wherein: The grain size D50 of the crystal grains constituting the dielectric layer in the middle region is not less than 2 times and not more than 20 times the grain size D50 of the crystal grains constituting the dielectric layers in the other two regions.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The dielectric layer in the intermediate region includes a region where the number of crystal grains forming one layer of the dielectric layer when viewed in the stacking direction is one.

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