Phase change memory
By introducing a thermal insulation structure into the phase change memory, the heat dissipation rate of the phase change memory unit is reduced, the problem of signal crosstalk during the write operation is solved, and the number of writes and performance of the phase change memory is improved.
Patent Information
- Application Number
- CN202420945313.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-30
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2034-04-30
AI Technical Summary
During the write operation, existing phase change memory is prone to signal crosstalk due to heat dissipation, which reduces the number of writes and memory performance of the surrounding phase change memory units.
The thermal insulation structure is adopted, including the gap between the first and second thermal insulation layers, to reduce the heat dissipation rate of the phase change memory unit, slow down the temperature influence, and increase the number of write operations of the phase change memory unit.
It effectively reduces the probability of signal crosstalk during phase change memory write operation, improves the effective number of data write operations, and improves the product performance of phase change memory.
Smart Images
Figure CN222192952U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of memory technology, and in particular to a phase change memory. Background Art
[0002] Phase change memory (PCM) is a non-volatile memory device for data storage and data reading and writing using the conductivity or impedance difference between the crystalline and amorphous states of a specific phase change material. The phase change material is heated by different pulses to control the conversion between the crystalline and amorphous states of the phase change material. Utility Model Content
[0003] In view of this, an embodiment of the present application provides a phase change memory, which can reduce the impact of the temperature of the phase change memory unit on the number of write times of the phase change memory units around it, reduce the probability of signal crosstalk during the write operation of the phase change memory, increase the number of write times of the phase change memory, and improve the product performance of the phase change memory.
[0004] To achieve the above purpose, the technical solution of this application is implemented as follows:
[0005] In one aspect, an embodiment of the present application provides a phase change memory, which includes a phase change memory unit and a heat insulation structure.
[0006] The phase change memory unit at least comprises a phase change memory layer. The heat insulation structure comprises a first heat insulation layer at least covering the side wall of the phase change memory unit, a second heat insulation layer spaced apart from the first heat insulation layer and away from the side wall of the phase change memory unit, and a first gap between the first heat insulation layer and the second heat insulation layer.
[0007] In some examples, the first gap is a void.
[0008] In some examples, an area enclosed by an orthographic projection of a boundary of the first gap on a plane where a sidewall of the phase-change memory unit is located at least covers the phase-change memory layer.
[0009] In some examples, the phase change memory further includes a substrate, the phase change memory unit and the thermal insulation structure are both arranged on the same side of the substrate; and the first thermal insulation layer covers the phase change memory unit.
[0010] In some examples, the phase change memory further includes an encapsulation layer, which is disposed on a side of the phase change memory unit away from a substrate of the phase change memory, and the encapsulation layer, the substrate, the first thermal insulation layer and the second thermal insulation layer together enclose the first gap.
[0011] In some examples, along the direction from the first thermal insulation layer to the second thermal insulation layer, the size of the first gap is greater than or equal to the size of the first thermal insulation layer, and / or the size of the first gap is greater than or equal to the size of the second thermal insulation layer.
[0012] In some examples, the number of the phase change memory cells includes a plurality; the plurality of phase change memory cells are spaced apart along a first direction, the first direction being parallel to a direction from the first thermal insulation layer to the second thermal insulation layer. A second gap is provided between two thermal insulation structures between two adjacent phase change memory cells.
[0013] In some examples, a size of the second gap along the first direction is greater than or equal to a size of the first gap along the first direction.
[0014] In some examples, the number of the phase-change memory cells includes a plurality; the plurality of phase-change memory cells are spaced apart along a first direction, the first direction being parallel to a direction from the first thermal insulation layer to the second thermal insulation layer. The two thermal insulation structures between two adjacent phase-change memory cells share one second thermal insulation layer.
[0015] In some examples, the material of the first thermal insulation layer and the material of the second thermal insulation layer are independently selected from one of silicon nitride, silicon carbide, silicon germanium, silicon selenide, silicon sulfide, silicon telluride, and tin telluride.
[0016] The thermal insulation structure in the above-mentioned phase change memory has a first gap between the first thermal insulation layer and the second thermal insulation layer. The structure of the first gap has a lower heat conduction efficiency than the structure of the material layer, which can slow down the rate at which the heat generated by the phase change memory unit due to operation is dissipated to other surrounding phase change memory units, reduce the probability of the material properties of other surrounding phase change memory units changing from amorphous to crystalline due to temperature increase, and is beneficial to increase the probability of resetting the material properties of other surrounding phase change memory units from crystalline to amorphous, which is characterized by reducing the probability of signal crosstalk occurring during the write operation of the phase change memory unit, increasing the effective number of subsequent data write operations performed by other surrounding phase change memory units, and improving the product performance of the phase change memory.
[0017] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application;
[0019] Figure 2 A schematic diagram of a readable storage medium provided in an embodiment of the present application Figure 1 ;
[0020] Figure 3 A schematic diagram of a readable storage medium provided in an embodiment of the present application Figure 2 ;
[0021] Figure 4 A schematic diagram of the structure of a phase change memory provided by an embodiment of the present application;
[0022] Figure 5 A schematic diagram of the structure of a phase change memory array of a phase change memory provided in an embodiment of the present application;
[0023] Figure 6 A schematic diagram of the structure of a peripheral circuit of a phase change memory provided in an embodiment of the present application;
[0024] Figure 7 A schematic diagram of the structure of a phase change memory provided in an embodiment of the present application Figure 1 ;
[0025] Figure 8 A schematic diagram of the structure of a phase change memory provided in an embodiment of the present application Figure 2 ;
[0026] Fig. 9 A schematic diagram of the structure of a phase change memory provided in an embodiment of the present application Figure 3 ;
[0027] Fig.10 A schematic diagram of the structure of a phase change memory provided in an embodiment of the present application Figure 4 ;
[0028] Fig.11 A schematic diagram of the structure of a phase change memory provided in an embodiment of the present application Figure 5 ;
[0029] Fig.12 A schematic diagram of the structure of a phase change memory provided in an embodiment of the present application Figure 6 ;
[0030] Fig.13 A schematic diagram of the structure of a phase change memory provided in an embodiment of the present application Figure 7 ;
[0031] Fig.14 A schematic diagram of the structure of a phase change memory provided in an embodiment of the present application Figure 8 . DETAILED DESCRIPTION
[0032] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.
[0033] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.
[0034] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.
[0035] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.
[0036] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.
[0037] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0038] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.
[0039] Phase Change Material (PCM) refers to a material that changes its state and provides latent heat without changing its temperature. The process of changing physical properties is called phase change, during which the PCM absorbs or releases a large amount of latent heat.
[0040] Phase change materials have the ability to change their physical state within a certain temperature range. Taking solid-liquid phase change as an example, when heated to the melting temperature, a phase change from solid to liquid occurs. During the melting process, the phase change material absorbs and stores a large amount of latent heat; when the phase change material cools, the stored heat must be dissipated to the environment within a certain temperature range, and the reverse phase change from liquid to solid is performed. In these two phase change processes, the energy stored or released is called the latent heat of phase change. When the physical state changes, the temperature of the material itself remains almost unchanged before the phase change is completed, forming a wide temperature platform. Although the temperature remains unchanged, the latent heat absorbed or released is quite large.
[0041] Phase Change Memory (PCM) is a non-volatile memory device that uses phase change materials to store data. PCM can be based on heating and quenching the phase change material in an electrothermal manner, using the difference between the resistivity of the amorphous state and the crystalline state in the phase change material (e.g., a chalcogenide alloy). The phase change material in the PCM cell can be located between two electrodes, and a current can be applied to repeatedly switch the material (or at least a portion of it blocking the current path) between the two phases to store data. The set state is a low resistance state of the PCM cell, which can be obtained by generating a crystalline region in the chalcogenide material. When the chalcogenide material is heated at a crystallization temperature for a sufficient time, crystallization occurs. Conversely, the reset state is a high resistance state of the PCM cell, which can be obtained by generating a non-crystalline region in the chalcogenide material. The amorphous state can be generated when the chalcogenide material is heated above its melting temperature and then rapidly quenched to form an amorphous state. Among them, the set state can be referred to as the on state; and the reset state can be referred to as the off state.
[0042] As described above, when the phase change material in the PCM switches between the crystalline state and the amorphous state, different pulses (such as light pulses, electric pulses) can be used to control the heating of the phase change material. For example, a feasible implementation includes applying a long and medium-intensity programming pulse (also referred to as Set Pulse) to raise the temperature of the phase change material layer of the phase change memory unit to below the melting temperature and above the crystallization temperature (the crystallization temperature is lower than the melting temperature), and maintaining it for a period of time and promoting the growth of the crystal nucleus, so that the phase change material layer of the phase change memory unit can be transformed from the amorphous state (corresponding to the high resistance state) to the crystalline state (corresponding to the low resistance state). The process of realizing the phase change material of the phase change memory unit from the high state (0 state) to the low resistance state (1 state) is usually called the set process, or the write operation process; after applying a short and strong reset pulse (also referred to as Reset Pulse) to raise the temperature of the phase change material layer of the phase change memory unit to above the melting temperature, and then undergoing rapid cooling (Cooling) Dow), the phase change material layer of the phase change memory unit can be changed from the crystalline state to the amorphous state. The process of changing the phase change material layer of the phase change memory unit from the low resistance state (1 state) to the high resistance state (0 state) is usually called the reset process, or the erase operation process. Among them, the Reset process and the Set process are mutually reversible processes. Therefore, the phase change memory unit can use the crystalline state to represent the unit binary data 1, and use the amorphous state to represent the binary data 0.
[0043] Exemplarily, the phase change memory may include a plurality of memory arrays, and the phase change memory cells contained in each memory array have a plurality of threshold voltage distributions, and each phase change memory cell in the memory array may have a different threshold voltage. It should be noted that there may be some differences in the threshold voltage distributions corresponding to the phase change memory cells in different memory arrays, that is, the threshold voltage distributions calculated for different numbers of phase change memory cells may have slightly different shapes, but generally similar shapes. The threshold voltage distribution of a memory array can be obtained through a preliminary durability test cycle. In addition, after applying a very weak read pulse that will not affect the phase change material layer, the resistance value of the phase change memory cell is measured to achieve the reading of the data stored in the phase change memory cell.
[0044] In the related art, heating the phase change material of some phase change memory cells of the phase change memory causes the phase change material to change from an amorphous state to a crystalline state. During the writing operation, the phase change memory will also generate heat and release the heat to the surrounding structures. Since the heat is dissipated to the adjacent phase change memory cells, it is easy to affect the phase change material of the surrounding phase change memory cells from an amorphous state to a crystalline state, and the surrounding phase change memory cells cannot be reset, that is, the signal crosstalk problem is generated, and thus, effective data cannot be written to the surrounding phase change memory cells, which is characterized by a small number of data writes in the performance of the entire memory.
[0045] In order to solve the above problems, an embodiment of the present application provides a phase change memory, which can reduce the probability of signal crosstalk occurring during the write operation of the phase change memory, increase the number of write operations implemented by the phase change memory, and improve the product performance of the phase change memory.
[0046] like Figure 1 As shown, first, the embodiment of the present application shows an electronic device 10. For example, the electronic device 10 may include but is not limited to a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device 32 therein.
[0047] Please continue reading Figure 1 , the electronic device 10 may include a host 20 and a memory system 30 .
[0048] The host 20 may be a processor (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device 10. The host 20 may be configured to send data to the memory system 30 or receive data from the memory system 30.
[0049] The memory system 30 includes a memory controller 31 and one or more memory devices 32, as well as other integrated circuit structures for signal transmission. The memory controller 31 and one or more memory devices 32 may be integrated and packaged in the same storage medium 40 (see Figure 2 and Figure 3 ). In this way, it is beneficial to apply the memory system 30 to different types of terminal electronic products. For example, the memory device 32 may include a phase change memory.
[0050] like Figure 2 and Figure 3 As shown, in some embodiments, the present application provides a readable storage medium 40. The readable storage medium 40 includes a stored computer program or instruction; when the computer program or instruction is executed, the device where the computer readable storage medium is located is controlled to implement the operation method of the memory system provided in any subsequent example.
[0051] The readable storage medium 40 integrates the memory controller 31 and one or more memory devices 32. For example, the types of the readable storage medium 40 include: Universal Flash Storage (UFS) or Embedded Multi Media Card (eMMC) and other types of storage devices.
[0052] Furthermore, the readable storage medium 40 may be in the form of an integrated circuit in various ways, for example, a memory card 410 (eg, a memory card 410 formed by integrating a single memory device 32 and a memory controller 31) may be formed. Figure 2 ), or a plurality of memory devices 32 and a memory controller 31 may be integrated to form an SSD 420 (such as Figure 3 shown).
[0053] By way of example, the memory card 410 may include one or more types of storage devices including a Personal Computer Memory Card International Association (PC) card, a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMC micro), an SD card (SD, miniSD, microSD, SDHC (Secure Digital High Capacity)), and UFS.
[0054] Please continue to read Figure 2 , the memory card 410 further includes a memory card connector 41. The memory card connector 41 is configured to connect the memory card 410 to a host (eg, Figure 1 For example, the memory card connector 41 includes a gold finger.
[0055] Alternatively, continue to Figure 3 , SSD 420 also includes an SSD connector 41. SSD connector 41 is configured to connect SSD 420 to a host (e.g., Figure 1 For example, the SSD connector 41 includes a gold finger.
[0056] It is understood that the storage capacity and / or operating speed of the SSD 420 is greater than the storage capacity and / or operating speed of the memory card 410 .
[0057] The memory controller 31 integrated in the same storage device is coupled to the memory device 32 (and the host 20 ), and the memory controller 31 is configured to control the memory device 32 .
[0058] Exemplarily, the memory controller 31 may be designed to operate in a low duty cycle environment. For example, for operating in a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive; or for operating in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Also exemplarily, the memory controller 31 may be designed to operate in a high duty cycle environment, for example, for operating in an SSD or an embedded Multi-Media Card (eMMC). Among them, the SSD or eMMC can be used as a data storage device for mobile devices such as smart phones, tablet computers, laptop computers, and enterprise storage arrays.
[0059] Further, the memory controller 31 can manage the data in the memory device 32 and communicate with the host 20. The memory controller 31 can be configured to control the operations such as reading, erasing and programming of the memory device 32; it can also be configured to manage various functions related to the data stored or to be stored in the memory device 32, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc.; it can also be configured to process error correction codes (Error Checking and Correction, ECC) on the data read from the memory device 32 or written to the memory device 32.
[0060] In addition, the memory controller 31 may also perform any other suitable functions, such as formatting the memory device 32, or communicating with an external device (eg, Figure 1For example, the memory controller 31 can communicate with the host 20 through at least one of various interface protocols. The interface protocols include one or more of USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Development Equipment (IDE) protocol, Firewire protocol, etc.
[0061] The above-mentioned memory device 32 may include but is not limited to one or more memories selected from NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Nano Random Access Memory (NRAM), etc.
[0062] Based on the above description, the present application takes the memory device 32 as a semiconductor memory, such as a solid-state electronic device (such as a NAND memory) for storing data information made by a semiconductor integrated circuit process as an example to explain the subsequent embodiments. The subsequent examples of the present application do not limit the specific internal structures of the memory device 32 and the memory controller 31.
[0063] It can be understood that in order to facilitate the distinction between the adaptive adjustments made by the memory device 32 for different scenarios, for example, based on the various structures of the memory device 32 (such as NAND-type memory) exemplified in the foregoing content, the memory system 50 provided in the subsequent examples of this application includes a phase change memory 60 and a memory controller 51 for illustration.
[0064] In some embodiments, Figure 4 As shown, the memory system 50 includes a memory controller 51 and a phase change memory 60 .
[0065] The memory controller 51 is used to control the phase change memory 60 .
[0066] like Figure 5 and Figure 6 As shown, the phase change memory 60 may include a phase change memory cell array 61 and a peripheral circuit 62 coupled to the phase change memory cell array 61 and other circuit structures.
[0067] like Figure 5 As shown, the memory cell array 61 is coupled to a plurality of bit lines (BL) and word lines (WL). For example, the memory cell array 61 may be a NAND flash memory cell array. For example, the memory cell array 61 may include a plurality of phase change memory cells (cells) 611 formed of phase change materials, which are coupled in series and stacked vertically. Each phase change memory cell 2013 may include a PCM element (containing phase change material, not shown in the figure) connected in series with a selector (not shown in the figure). In some embodiments, the phase change memory cell 611 may include a DRAM cell of a paired transistor and capacitor. In order to operate the phase change memory cell array 61, a word line voltage may be applied to a selected word line WL, and a bit line voltage may be applied to a selected bit line BL.
[0068] For example, each memory cell in the memory cell array 61 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor, which is not limited in the present application.
[0069] Please continue reading Figure 6The above peripheral circuit 62 can be coupled to the memory cell array 61 through the bit line BL, the word line WL, the source (Source Line), the source select gate (Source Select Gate, SSG) and the drain select gate (Drain Select Gate, DSG). The peripheral circuit 62 is configured to implement the logic operation (such as programming, reading or writing operation) of the memory cell array 61 by applying a voltage signal and / or a current signal to each target memory cell through the bit line BL, the word line WL, the source SL, the source select gate SSG or the drain select gate DSG, etc., and sensing the voltage signal and / or the current signal from each target memory cell.
[0070] For example, the peripheral circuit 62 includes various types of circuit structures formed using metal-oxide-semiconductor (MOS) transistors. Figure 6 As shown, the peripheral circuit 62 may include a row decoder / word line driver 620, a page buffer (PB) / sense amplifier 621, a column decoder / bit line driver 623, a voltage generator 624, a control logic unit 625, a latch circuit 626, an interface 627 and a data bus 628 and other circuit structures.
[0071] The following embodiments illustrate how to reduce the impact of the heat dissipation problem of the phase change memory unit 611 performing a write operation on the surrounding phase change memory units 611 from the layer structure of the phase change memory unit 60 .
[0072] In some embodiments, Figure 7 As shown, the present application provides a phase change memory 60. The phase change memory 60 includes: a phase change memory unit 611 and a heat insulation structure 612.
[0073] The phase change memory unit 611 at least includes a phase change memory layer 6111. For example, the phase change memory layer 6111 is a layer formed of a phase change material, which can be converted between an amorphous state and a crystalline state under heating and quenching process conditions, and then the phase change memory layer 6111 stores data by using the difference between the resistivity of the amorphous state and the resistivity of the crystalline state.
[0074] The heat insulation structure 612 is located between adjacent phase change memory cells 611, and is used to reduce the effect of heat dissipated by the phase change memory cell 611 being transferred to the adjacent phase change memory cell, thereby slowing down the heat dissipation. For example, the heat insulation structure 612 includes a first heat insulation layer 6121 covering at least the side wall of the phase change memory cell 611, a second heat insulation layer 6122 spaced apart from the first heat insulation layer 612 and away from the side wall direction of the phase change memory cell 611, and a first gap 6123 between the first heat insulation layer 6121 and the second heat insulation layer 6122.
[0075] In the above-mentioned phase change memory 60, the insulation structure 612 has a first gap 6123 separating the first insulation layer 6121 and the second insulation layer 6122. The structure of the first gap 6123 has a lower heat conduction efficiency than the structure of the (solid) material layer, and can slow down the rate at which the heat generated by the phase change memory unit 611 due to operation is dissipated to other surrounding phase change memory units 611, reduce the probability of the material properties of other surrounding phase change memory units 611 changing from amorphous to crystalline due to temperature increase, and help to increase the probability of resetting the material properties of other surrounding phase change memory units 611 from crystalline to amorphous, which is characterized by reducing the probability of signal crosstalk occurring during the write operation of the phase change memory unit 611, increasing the effective number of subsequent data write operations performed by other surrounding phase change memory units 611, and improving the product performance of the phase change memory 60.
[0076] In some examples, the first gap 6123 is a gap. In some examples, the first gap 6123 is filled with air. Considering that the thermal conductivity of air is lower than that of the material layer, the first gap 6123 is filled with air, which can reduce the speed at which the heat generated by the phase change memory unit 611 is transferred from the first insulation layer 6121 to the second insulation layer 6122, and reduce the probability that the heat generated by the phase change memory unit 611 affects the normal operation of the surrounding phase change memory units 611.
[0077] It is understandable that the first gap 6123 may be filled with gas or in a vacuum state. For example, the first gap 6123 is filled with air or an inert gas.
[0078] In some examples, a region enclosed by an orthographic projection of a boundary of the first gap 6123 on a plane where a sidewall of the phase-change memory unit 611 is located at least covers the phase-change memory layer 6111 .
[0079] Please continue reading Figure 7Considering that the data writing operation is mainly affected by the phase-change memory layer 6111 in the phase-change memory unit 611, it is necessary to at least reduce the probability of the phase-change memory layer 6111 being affected by temperature. In this way, the spacing between the two opposite boundaries of the first gap 6123 along the direction Y is L2. The spacing between the two opposite boundaries of the phase-change memory layer 6111 along the direction Y is L1, and L1 is smaller than L2. The area enclosed by the orthographic projection of the boundary of the first gap 6123 on the plane where the side wall of the phase change memory unit 611 is located at least covers the phase change memory layer 6111. The first gap 6123 is filled with air, and the air slows down the rate at which the heat generated by the phase change memory unit 611 due to operation is dissipated to other surrounding phase change memory units 611, thereby reducing the probability of the material properties of other surrounding phase change memory units 611 (such as the phase change memory layer 6111) changing from an amorphous state to a crystalline state due to temperature increase, and is beneficial to increasing the probability of the material properties of other surrounding phase change memory units 611 (such as the phase change memory layer 6111) being reset from a crystalline state to an amorphous state, which is characterized by reducing the probability of signal crosstalk occurring during the write operation of the phase change memory unit 611, increasing the effective number of subsequent data write operations performed by other surrounding phase change memory units 611, and improving the product performance of the phase change memory 60.
[0080] In addition, if Figure 7 As shown, when the first gap 6123 extends along the direction Y to the boundary of the phase change memory layer 6111, other materials for heat insulation may be provided between the first heat insulation layer 6121 and the second heat insulation layer 6122. For example, the heat insulation material may include at least one of silicon oxide, silicon nitride, silicon carbide, silicon germanium, silicon selenide, silicon sulfide, silicon telluride, and tin telluride. It can be understood that although the effect of the heat insulation material in slowing down the heat dissipation is weaker than that of air, the area enclosed by the orthographic projection of the boundary of the first gap 6123 on the plane where the side wall of the phase change memory unit 611 is located has covered the phase change memory layer 6111, and a better heat insulation effect can also be achieved.
[0081] In some examples, the material of the first thermal insulation layer 6121 and the material of the second thermal insulation layer 6122 are independently selected from one of silicon nitride, silicon carbide, silicon germanium, silicon selenide, silicon sulfide, silicon telluride, and tin telluride.
[0082] For example, the material of the first thermal insulation layer 6121 includes any one of silicon nitride, silicon carbide, silicon germanium, silicon selenide, silicon sulfide, silicon telluride, and tin telluride. And / or, the material of the second thermal insulation layer 6122 includes any one of silicon nitride, silicon carbide, silicon germanium, silicon selenide, silicon sulfide, silicon telluride, and tin telluride. The material of the first thermal insulation layer 6121 and the material of the second thermal insulation layer 6122 can be the same or different, and can be set according to actual needs.
[0083] For example, the material of the first thermal insulation layer 6121 includes silicon nitride, and the material of the second thermal insulation layer 6122 includes silicon nitride. The thermal insulation structure 612 includes a structure composed of silicon nitride, air, and silicon nitride.
[0084] In some examples, such as Figure 8 As shown, the phase change memory 60 further includes a substrate 613. The phase change memory unit 611 and the heat insulation structure 612 are both arranged on the same side of the substrate 613. The heat insulation structure 612 is located between adjacent phase change memory units 611, and is used to reduce the effect of heat dissipated by the phase change memory unit 611 being transferred to the adjacent phase change memory unit 611, thereby slowing down the heat dissipation.
[0085] It is understandable that the substrate 613 can be retained and a through hole can be set to realize the electrical connection of the stacked multiple phase change memory units 611, or it can be removed to realize electrical connection with other memories, which can be set according to the function and structure of the memory required in practice.
[0086] In some examples, such as Figure 8 As shown, the phase change memory unit 611 includes: a signal line layer 6112 , a first electrode layer 6113 , a gating layer 6114 , a second electrode layer 6115 , a phase change memory layer 6111 and a third electrode layer 6116 .
[0087] The signal line layer 6112 is disposed on the substrate 613. For example, the signal line layer 6112 may be a single layer; or a composite layer of multiple layers stacked together, with insulation between the multiple layers. Also, the signal line layer 6112 may include signal lines electrically connected to the word lines WL and the bit lines BL, or may include signal lines connected to other electronic components. This example does not limit this, and the number and type of signal lines of the signal line layer 6112 may be set as required.
[0088] The first electrode layer 6113 is disposed on a side of the signal line layer 6112 away from the substrate 613. For example, the constituent material of the first electrode layer 6113 includes but is not limited to amorphous carbon, such as α-phase carbon.
[0089] The gating layer 6114 is disposed on a side of the first electrode layer 6113 away from the signal line layer 6112. For example, the gating layer 6114 may be made of a material constituting a threshold selection switch (OTS), such as one or more of zinc telluride (ZnaTeb), germanium telluride (GeTe), niobium oxide (NbO), or silicon arsenic telluride (SiAsTe).
[0090] The second electrode layer 6115 is disposed on a side of the gate layer 6114 away from the first electrode layer 6113. For example, the constituent material of the second electrode layer 6115 includes but is not limited to amorphous carbon, such as α-phase carbon.
[0091] The phase change memory layer 6111 is disposed on a side of the second electrode layer away from the gate layer 6114. For example, the phase change memory 60 can transform the phase change memory layer 6111 between an amorphous state and a crystalline state based on heating and quenching the phase change memory layer 6111, and then store data by utilizing the difference between the resistivity of the phase change memory layer 6111 in the amorphous state and the resistivity of the crystalline state.
[0092] The third electrode layer 6116 is disposed on a side of the phase change memory layer 6111 away from the second electrode layer 6115. For example, the constituent material of the third electrode layer 6116 includes but is not limited to amorphous carbon, such as α-phase carbon.
[0093] It is understood that the layer structure of the above-mentioned phase change memory unit 611 is an exemplary description, and may also include multiple conductive material layers arranged on both sides of the phase change memory layer 6111, and the examples provided in this application are not limited to this. The thermal insulation structure 612 can at least isolate the stacked structure with storage function, wherein the common circuit structure used to connect with different phase change memory units 611 to provide electrical signals (not shown in the figure of this application) may not be isolated by the isolation structure 612. The following examples include Figure 8 The phase change memory 60 of the phase change memory unit 611 is shown as an example to illustrate the thermal insulation structure 612 .
[0094] In some examples, such as Figure 8 As shown, the phase change memory 60 further includes an encapsulation layer 614, which is disposed on a side of the phase change memory unit 611 away from the substrate 613 of the phase change memory 60. The encapsulation layer 614 is used to encapsulate the memory unit 611, the heat insulation structure 612 and other functional layers on the substrate 613, and protect the memory unit 611.
[0095] In some examples, such as Fig. 9 As shown, the phase change memory 60 provided in the present application may also include a mask layer 616 located on the side of the phase change memory unit 611 away from the substrate 613. The mask layer 616 can be used to protect the phase change memory unit 611 during the process of making a portion of the thermal insulation structure 612, and can be retained or removed as required after the thermal insulation structure 612 is formed. For example, the mask layer 616 may include a photoresist mask or a hard mask patterned based on a photolithography mask, such as silicon nitride.
[0096] Understandably, the subsequent Figure 10 to Figure 14 The example provided in the phase change memory 60 does not include the mask layer 616, but does not limit the phase change memory 60 to not having the mask layer 616. The example provided in this application does not limit the layer structure (number and shape) between the phase change memory unit 611 and the encapsulation layer 614, which can be set according to actual needs.
[0097] In some examples, such as Figure 7 to Figure 9 As shown, the first gap 6123 (and the second gap 6124 or the third gap 6125 mentioned in subsequent examples) extends along direction Y from the surface of the encapsulation layer 614 close to the phase change memory unit 611, and at least extends to the surface of the phase change memory layer 6111 away from the encapsulation layer 614.
[0098] For example, Figure 7 As shown, when other materials are included between the first thermal insulation layer 6121 and the second thermal insulation layer 6122, the encapsulation layer 614, the substrate 613, the first thermal insulation layer 6121, the second thermal insulation layer 6122 and the material layer located between the first thermal insulation layer 6121 and the second thermal insulation layer 6122 together form a first gap 6123.
[0099] In this way, the first gap 6123 extends at least from the surface of the encapsulation layer 614 close to the phase change storage layer 6111 to the surface of the phase change storage layer 6111 away from the encapsulation layer 614, at least reducing the heat dissipation rate generated by the phase change storage layer 6111 during operation, reducing the influence of signal crosstalk, and thereby increasing the number of write times of the phase change storage unit 611.
[0100] It can be understood that the "material layer located between the first thermal insulation layer 6121 and the second thermal insulation layer 6122" can be a structure formed by removing part of the material used to form the first gap 6123, or it can be a material with good thermal insulation effect formed by other process steps. The examples provided in this application do not limit this.
[0101] Another example, such as Figure 8 As shown, the encapsulation layer 614 , the substrate 613 , the first thermal insulation layer 6121 and the second thermal insulation layer 6122 together form a first gap 6123 .
[0102] In this way, the first gap 6123 extends along direction Y from the surface of the encapsulation layer 614 close to the phase change memory unit 611 to the substrate 613. The formed first gap 6123 (and the second gap 6124 or the third gap 6125 mentioned in subsequent examples) has a larger space and a larger gas content, which is beneficial to slowing down the rate at which heat from the phase change memory unit 611 is dissipated to the surrounding phase change memory units 611.
[0103] Another example, such as Fig. 9As shown, when the phase change memory 60 includes a mask layer 616, the encapsulation layer 614, the substrate 613, the first thermal insulation layer 6121, the second thermal insulation layer 6122 and the mask layer 616 together enclose a first gap 6123. In this way, the size of the first gap 6123 along the direction Y is greater than the size of the phase change memory unit 611 along the direction Y, and the space of the formed first gap 6123 (and the second gap 6124 or the third gap 6125 mentioned in the subsequent examples) is larger, which is conducive to further slowing down the rate at which the heat of the phase change memory unit 611 is dissipated to the surrounding phase change memory units 611.
[0104] In some examples, such as Fig.10 As shown, the first heat insulating layer 6121 covers the phase change memory unit 6111. The material properties of the first heat insulating layer 6121 are conducive to slowing down the rate at which the heat of the phase change memory unit 611 is dissipated to the surrounding phase change memory units 611.
[0105] In this way, combined with the various examples of the size of the first gap 6123 along the direction Y mentioned in some of the above examples, and the example in which the phase change memory 60 includes a mask layer 616, when the first thermal insulation layer 6121 covers the phase change memory unit 6111, the space of the first gap 6123 can be increased, which is beneficial to further slow down the rate at which heat from the phase change memory unit 611 is dissipated to the surrounding phase change memory units 611, reduce the impact of signal crosstalk, and thereby increase the number of write times of the phase change memory unit 611.
[0106] In some examples, such as Fig.10 As shown, along the direction from the first thermal insulation layer 6121 to the second thermal insulation layer 6122 , the size L3 of the first gap 6123 is greater than or equal to the size of the first thermal insulation layer 6121 , and / or the size L3 of the first gap 6123 is greater than or equal to the size of the second thermal insulation layer 6122 .
[0107] The example provided in the present application does not limit the size of the first thermal insulation layer 6121 and the second thermal insulation layer 6122 along the direction from the first thermal insulation layer 6121 to the second thermal insulation layer 6122, and can be set according to actual needs. For example, in the case where the size of the first thermal insulation layer 6121 is larger than the size of the second thermal insulation layer 6122 along the direction from the first thermal insulation layer 6121 to the second thermal insulation layer 6122, the size L3 of the first gap 6123 can be set to be larger than or equal to the size of the first thermal insulation layer 6121; or, in the case where the size of the second thermal insulation layer 6122 is larger than the size of the first thermal insulation layer 6121 along the direction from the first thermal insulation layer 6121 to the second thermal insulation layer 6122, the size L3 of the first gap 6123 can be set to be larger than or equal to the size of the second thermal insulation layer 6122. In this way, the size of the first gap 6123 can be increased as much as possible based on the thickness of a material, slowing down the rate at which the heat of the phase-change memory unit 611 is dissipated to the surrounding phase-change memory units 611.
[0108] It should be noted that, combined with Fig.10 In the thermal insulation structure 612 shown, the steps for making a first gap 6123 may include: depositing an oxide layer on a side of the first thermal insulation layer 6121 away from the phase change memory unit 611; then depositing an initial second thermal insulation layer 6122 on a side of the oxide layer away from the phase change memory unit 611; then using a chemical polishing process to remove a portion of the material of the initial second thermal insulation layer 6122 extending along a direction X to expose the oxide layer; then using an etching process to remove the material of the oxide layer to form a first gap 6123.
[0109] Setting the size L3 of the first gap 6123 to be greater than or equal to the size L4 of the first thermal insulation layer 6121 or the second thermal insulation layer 6122 is beneficial to the subsequent process operation of removing the material located between the first thermal insulation layer 6121 and the second thermal insulation layer 6122, and is beneficial to increasing the air in the thermal insulation structure 612, thereby slowing down the rate at which heat from the phase change memory unit 611 is dissipated to the surrounding phase change memory units 611.
[0110] For example, Fig.10 As shown, along the direction from the first thermal insulation layer 6121 to the second thermal insulation layer 6122, the size L4 of the second thermal insulation layer 6122 is 0.5 microns, and the size L3 of the first gap 6123 is larger than the size L4 of the second thermal insulation layer 6122, that is, larger than 0.5 microns.
[0111] In some examples, such as Fig.11 and Fig.12 As shown, the number of the phase change memory unit 611 includes a plurality; the plurality of phase change memory units 611 are arranged at intervals along a first direction X, and the first direction X is parallel to a direction from the first heat insulation layer 6121 to the second heat insulation layer 6122 .
[0112] like Fig.11 As shown, there is a second gap 6124 between two heat insulating structures 612 between two adjacent phase change memory units 611. Providing multiple gaps between two adjacent phase change memory units 611 can further slow down the rate at which heat from the phase change memory unit 611 is dissipated to the surrounding phase change memory units 611.
[0113] For example, Fig.12 As shown, based on the first thermal insulation layer 6121 covering the phase change memory unit 611 on the semiconductor substrate 613, the size of the first gap 6123 along the direction Y is larger than the size of the phase change memory unit 611 along the direction Y, and the structure with a second gap 6124 between the two thermal insulation structures 612 between two adjacent phase change memory units 611, the rate at which heat from the phase change memory unit 611 is dissipated to the surrounding phase change memory units 611 can be further slowed down.
[0114] In some examples, such as Fig.11 and Fig.12 As shown, a dimension L5 of the second gap 6124 along the first direction X is greater than or equal to a dimension L3 of the first gap 6123 along the first direction X.
[0115] When multiple phase change memory units 611 are arranged on the substrate 613 at intervals, the second gap 6124 can not only separate the multiple phase change memory units 611, which is beneficial to the functional realization and structural manufacturing of different phase change memory units 611, but also the second gap 6124 can further increase the spacing between adjacent phase change memory units 611, slowing down the rate at which heat from the phase change memory unit 611 is dissipated to the surrounding phase change memory units 611.
[0116] In other examples, such as Fig.13 As shown, the number of the phase change memory unit 611 includes a plurality; the plurality of phase change memory units 611 are arranged at intervals along a first direction X, and the first direction X is parallel to a direction from the first heat insulation layer 6121 to the second heat insulation layer 6122 .
[0117] The two thermal insulation structures 612 between two adjacent phase-change memory units 611 share a second thermal insulation layer 6122 .
[0118] It can be understood that in order to exemplarily reflect the change of the first gap 6123 of the insulation structure 615 between two adjacent phase change memory units 611 when sharing a second insulation layer 6122, the name "third gap 6125" is used to reflect the difference from the "first gap 6123". In essence, the third gap 6125 is the first gap 6123 in the isolation structure 615, and the third gap 6125 does not represent a newly added gap structure.
[0119] For example, Fig.13 As shown, a dimension L6 of the third gap 6125 along the first direction X is greater than or equal to a dimension L3 of the first gap 6123 along the first direction X.
[0120] By sharing the second insulation layer 6122 between two adjacent phase change memory units 611, not only the process complexity is reduced, but also the dimension L6 of the third gap 6125 along the first direction X is increased, and the air in the insulation structure 612 is increased, which can further slow down the rate at which heat from the phase change memory unit 611 is dissipated to the surrounding phase change memory units 611.
[0121] In some examples, such as Fig.14As shown, the phase change memory 60 further includes an isolation structure 615, which is disposed between the phase change memory unit 611 and the thermal insulation structure 612. The isolation structure 615 can protect the electrical effect and structure of the phase change memory unit 611, and reduce the adverse effects of the subsequent manufacturing process of the thermal insulation structure 612 on the phase change memory unit 611.
[0122] The isolation structure 615 includes a first isolation layer 6151 and a second isolation layer 6152 .
[0123] The first isolation layer 6151 is disposed on one side of the first heat insulation layer 6121 close to the phase change memory unit 611 and at least covers the side wall of the phase change memory layer 6111. Fig.14 As shown, the first isolation layer 6151 extends along the direction Y and covers the side walls of the phase change memory layer 6111 and the third electrode layer 6116 .
[0124] The second isolation layer 6152 is disposed between the first isolation layer 6151 and the first heat insulation layer 6121 and covers at least the side wall of the phase change memory layer 6111. Fig.14 As shown, the second isolation layer 6152 extends along the direction Y and covers the side walls of the phase change memory layer 6111 and the third electrode layer 6116 .
[0125] For example, the materials used for the first isolation layer 6151 and the second isolation layer 6152 may include insulating materials.
[0126] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.
[0127] It should be noted that the phase change memory embodiments provided in this application and the memory system and electronic device are embodiments of the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the phase change memory structure provided in the embodiments of this application, the combination of its various technical features can already solve the technical problems to be solved by this application; therefore, the phase change memory provided in the embodiments of this application may not be limited by the memory system and electronic device provided in the embodiments of this application, and any device containing the phase change memory provided in the embodiments of this application is within the scope of protection of this application.
[0128] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.
Claims
1. A phase change memory, characterized in that: include: A phase change memory unit, comprising at least a phase change memory layer; The thermal insulation structure includes a first thermal insulation layer at least covering the side wall of the phase change memory unit, a second thermal insulation layer spaced apart from the first thermal insulation layer and away from the side wall of the phase change memory unit, and a first gap between the first thermal insulation layer and the second thermal insulation layer.
2. The phase change memory according to claim 1, characterized in that: The first gap is a void.
3. The phase change memory according to claim 1, characterized in that: An area enclosed by an orthographic projection of the boundary of the first gap on the plane where the side wall of the phase-change memory unit is located at least covers the phase-change memory layer.
4. The phase change memory according to claim 1, characterized in that: The phase change memory further comprises a substrate, the phase change memory unit and the heat insulation structure are both arranged on the same side of the substrate; and the first heat insulation layer covers the phase change memory unit.
5. The phase change memory according to claim 1 or 4, characterized in that: The phase change memory further includes a packaging layer, which is arranged on a side of the phase change memory unit away from the substrate of the phase change memory. The packaging layer, the substrate, the first thermal insulation layer and the second thermal insulation layer together enclose the first gap.
6. The phase change memory according to claim 1, characterized in that: Along the direction from the first thermal insulation layer to the second thermal insulation layer, the size of the first gap is greater than or equal to the size of the first thermal insulation layer, and / or the size of the first gap is greater than or equal to the size of the second thermal insulation layer.
7. The phase change memory according to claim 1, characterized in that: The number of the phase change memory units includes a plurality; the plurality of phase change memory units are arranged at intervals along a first direction, and the first direction is parallel to a direction from the first heat insulation layer to the second heat insulation layer; A second gap is provided between the two thermal insulation structures between two adjacent phase-change memory units.
8. The phase change memory according to claim 7, characterized in that: A size of the second gap along the first direction is greater than or equal to a size of the first gap along the first direction.
9. The phase change memory according to claim 1, characterized in that: The number of the phase-change memory units includes a plurality; the plurality of phase-change memory units are arranged at intervals along a first direction, and the first direction is parallel to a direction from the first heat-insulating layer to the second heat-insulating layer; The two thermal insulation structures between two adjacent phase-change memory units share one second thermal insulation layer.
10. The phase change memory according to claim 1, characterized in that: The material of the first thermal insulation layer and the material of the second thermal insulation layer are independently selected from one of silicon nitride, silicon carbide, silicon germanium, silicon selenide, silicon sulfide, silicon telluride, and tin telluride.