Display panel

Abstract

The utility model discloses a display panel, a display area of the display panel comprises a plurality of pixel units arranged in an array, and each pixel unit comprises a device area and a pixel area; the display panel comprises a substrate, a thin film transistor located in a device area and a pixel electrode located in a pixel area. The thin film transistor comprises a first electrode, an interlayer dielectric layer, a second electrode and an active layer which are sequentially located on a substrate. The interlayer dielectric layer covers the substrate and the first electrode; a first via hole for exposing the first electrode is formed in the interlayer dielectric layer; the second electrode is located on the interlayer dielectric layer; the active layer covers the first electrode exposed in the first via hole, the hole wall of the first via hole and the second electrode; the interlayer dielectric layer extends from the device area to the pixel area, and the pixel electrode is located on the side, away from the substrate, of the interlayer dielectric layer and connected with the second electrode; the pixel electrode and the second electrode or the active layer are arranged on the same layer. The manufacturing cost of the display panel can be effectively reduced while the high aperture ratio and the high charging rate of the display panel are achieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] In high refresh rate, low energy consumption, demultiplexing (demux) driven products, thin film transistor (TFT) devices need to have a large on-state current to meet the charging rate requirements, or reduce the size of thin film transistor devices to achieve narrow borders and high penetration. Short channel technology can greatly increase the on-state current of the device and reduce the size of the device. If the channel of the thin film transistor device is reduced to within 1 micron (um) through short channel technology, the on-state current of the device can be increased by more than 5 times compared to conventional thin film transistor devices.

[0003] Generally, the exposure resolution of the 4.5 generation factory (G4.5) is above 1.5um, and the exposure resolution of the 8.5 generation factory (G8.5) is above 2um, which makes it difficult to realize the production of short channel devices by direct exposure. However, the thin film transistor device with vertical channel structure is not limited by the accuracy of the exposure machine, so that the production of ultra-short channel devices can be realized on the large generation line. Utility Model Content

[0004] The present application provides a display panel that can achieve a high aperture ratio and a high charging rate of the display panel while effectively reducing its manufacturing cost.

[0005] The present application provides a display panel, the display panel comprising a display area and a non-display area arranged adjacent to each other, the display area comprising a plurality of pixel units arranged in an array, each of the pixel units comprising a device area and a pixel area arranged adjacent to each other; the display panel comprises a substrate located in the display area and the non-display area, a thin film transistor located in the device area, and a pixel electrode located in the pixel area;

[0006] The thin film transistor comprises:

[0007] A first electrode, located on the substrate;

[0008] an interlayer dielectric layer, covering the substrate and the first electrode; a first via hole is provided on the interlayer dielectric layer, and the first via hole exposes at least a portion of the first electrode;

[0009] A second electrode is located on a side of the interlayer dielectric layer away from the substrate;

[0010] an active layer, covering the first electrode exposed to the first via hole, a hole wall of the first via hole, and at least a portion of the second electrode;

[0011] The interlayer dielectric layer extends from the device area to the pixel area, the pixel electrode is located on a side of the interlayer dielectric layer away from the substrate and is connected to the second electrode; the pixel electrode is arranged in the same layer as the second electrode or the active layer.

[0012] Optionally, the pixel electrode and the second electrode are arranged in the same layer; the pixel electrode and the second electrode are made of the same material and include a transparent metal oxide conductor material.

[0013] Optionally, the material of the pixel electrode and the second electrode includes any one of indium tin oxide and indium zinc oxide, or a combination of the two materials.

[0014] Optionally, the pixel electrode is provided in the same layer as the active layer; the material of the active layer is a semiconductor material, the material of the pixel electrode is a conductive semiconductor material, and the material of the pixel electrode contains all chemical elements contained in the material of the active layer.

[0015] Optionally, the material of the active layer includes a metal oxide semiconductor material; and the material of the second electrode includes a metal material or a metal oxide conductor material.

[0016] Optionally, the thin film transistor further comprises a gate insulating layer and a gate; the gate insulating layer at least covers the active layer; the gate is located on a side of the gate insulating layer away from the substrate and is arranged in alignment with the active layer;

[0017] The edge of the gate electrode close to the pixel electrode is completely overlapped with the edge of the pixel electrode close to the gate electrode.

[0018] Optionally, an edge of the gate insulating layer is aligned with an edge of the gate.

[0019] Optionally, the pixel electrode extends from the interlayer dielectric layer to cover a portion of the second electrode; an edge of the pixel electrode on the second electrode close to the gate is completely overlapped with an edge of the gate close to the pixel electrode.

[0020] Optionally, a second via hole is provided on the second electrode; the second via hole is aligned with and connected to the first via hole; the active layer also covers the side wall of the second via hole; the aperture of the first via hole close to the second via hole is greater than or equal to the aperture of the second via hole close to the first via hole.

[0021] Optionally, the display panel further includes a gate insulating layer and a gate; the gate insulating layer at least covers the active layer; and the gate is at least arranged on a side of the gate insulating layer away from a hole wall of the first via hole.

[0022] In the display panel provided by the present application, the first electrode, the second electrode, the active layer and the gate of the thin film transistor in the device area are distributed in a direction perpendicular to the substrate, and the channel is formed on the side wall of the first via hole of the interlayer dielectric layer, and the nanometer or submicron ultra-short channel can be realized by controlling the thickness of the interlayer dielectric layer, thereby realizing a high aperture ratio and a high charging rate; and, since the pixel electrode in the pixel area is arranged in the same layer as the second electrode or the active layer in the device area, the pixel electrode can be formed in the same photomask process as the second electrode or the active layer, which is conducive to saving a photomask process for making the pixel electrode, thereby saving the production cost of the display panel; at the same time, the pixel electrode is connected to the second electrode and is arranged in the same layer, which can avoid increasing the overlap of the openings, thereby reducing the number of openings, and further reducing the production cost of the display panel. Therefore, the display panel provided by the present application can effectively reduce its production cost while achieving a high aperture ratio and a high charging rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0024] Figure 1 A schematic diagram of a partial cross-sectional structure of a display panel provided in an embodiment of the present application;

[0025] Figure 2 for Figure 1 A top view of a local structure of a pixel unit of a display panel shown;

[0026] Figure 3 for Figure 2 A top view of a first electrode, a second electrode and a pixel electrode;

[0027] Figure 4 for Figure 1 The manufacturing flow chart of the display panel shown;

[0028] Figures 5 to 10 for Figure 4 A schematic diagram of the structure of the display panel corresponding to each step in the embodiment;

[0029] Fig.11 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0030] Fig.12 for Fig.11 A top view of a local structure of a pixel unit of a display panel shown;

[0031] Fig.13 for Fig.11 The manufacturing flow chart of the display panel shown;

[0032] Figures 14 to 19 for Fig.13 A schematic diagram of the structure of the display panel corresponding to each step in the embodiment;

[0033] Fig. 20 A schematic diagram of the cross-sectional structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0035] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0036] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0037] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0038] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0039] The present application provides a display panel, which includes a display area and a non-display area that are adjacent to each other, the display area includes a plurality of pixel units arranged in an array, each pixel unit includes a device area and a pixel area that are adjacent to each other; the display panel includes a substrate located in the display area and the non-display area, a thin film transistor located in the device area, and a pixel electrode located in the pixel area.

[0040] Specifically, the thin film transistor includes at least a first electrode, an interlayer dielectric layer, a second electrode and an active layer. The first electrode is located on the substrate; the interlayer dielectric layer covers the substrate and the first electrode; a first via hole is provided on the interlayer dielectric layer, and the first via hole exposes at least a portion of the first electrode; the second electrode is located on a side of the interlayer dielectric layer away from the substrate; the active layer covers the first electrode exposed to the first via hole, the hole wall of the first via hole and at least a portion of the second electrode; wherein the interlayer dielectric layer extends from the device area to the pixel area, the pixel electrode is located on a side of the interlayer dielectric layer away from the substrate, and is connected to the second electrode; the pixel electrode is provided on the same layer as the second electrode or the active layer.

[0041] Specifically, one of the first electrode and the second electrode is a drain, and the other is a source.

[0042] Specifically, in the display panel provided by the present application, the first electrode, the second electrode, the active layer and the gate of the thin film transistor in the device area are distributed in a direction perpendicular to the substrate, and the channel is formed on the side wall of the first via hole of the interlayer dielectric layer. An ultra-short channel at the nanometer or submicron level can be achieved by controlling the thickness of the interlayer dielectric layer.

[0043] Specifically, the ultra-short channel thin film transistor has an ultra-high on-state current and switching ratio, which can effectively improve the device charging rate; and the ultra-short channel thin film transistor can effectively reduce the device size, thereby effectively improving the panel aperture ratio. Therefore, the display panel provided by the present application can achieve a high aperture ratio and a high charging rate, and can be applied to micro, small, and medium-sized liquid crystal display (LCD) products with high aperture ratio requirements, or can be applied to other products such as electronic paper and reflective LCD, but is not limited thereto.

[0044] Specifically, the display panel provided by the present application is preferably applicable to LCD products of the Fringe Field Switching (FFS) type. For the FFS type liquid crystal display panel, it also includes a common electrode located in the pixel area, that is, the common electrode and the pixel electrode are both arranged on the array substrate. Of course, the display panel provided by the present application can also be applicable to LCD products of the Vertical Alignment (VA) type. For the VA type liquid crystal display panel, the common electrode and the pixel electrode are respectively arranged on two oppositely arranged substrates, for example, the pixel electrode is arranged on the array substrate, and the common electrode is arranged on the color film substrate or the opposing substrate.

[0045] Specifically, in the display panel provided by the present application, the pixel electrode is arranged in the same layer as the second electrode or the active layer, so that the pixel electrode and one of the second electrode and the active layer can be formed in the same mask process, which can save a mask process for making the pixel electrode. At the same time, the pixel electrode and the second electrode are electrically connected by direct connection, and there is no need to increase the opening overlap, which can reduce the number of openings. Therefore, the display panel provided by the present application can also effectively reduce the production cost of the display panel.

[0046] It can be understood that since the thin film transistor with a vertical channel structure is not limited by the accuracy of the exposure machine, the display panel provided in the present application can be manufactured on an existing generation line (such as G4.5 or G8.5) to achieve mass production.

[0047] The structure of the display panel will be described in detail below through several specific embodiments.

[0048] like Figure 1As shown, an embodiment of the present application provides a display panel 1, which includes a display area A and a non-display area B that are adjacent to each other, the display area includes a plurality of pixel units P arranged in an array, each pixel unit P includes a device area 2 and a pixel area 3 that are adjacent to each other; the display panel 1 includes a substrate located in the display area A and the non-display area B, a thin film transistor 4 located in the device area 2, and a pixel electrode 5 located in the pixel area 3.

[0049] It can be understood that the device area 2 of the display panel 1 is used to set electronic devices for driving the display, the pixel area 3 is used to set pixel electrodes 5 for light-transmitting display, and the non-display area B is used to set other drive circuits and connection wiring structures.

[0050] Specific, combined Figures 1 to 3 As shown, the thin film transistor 4 at least includes a first electrode 7, an interlayer dielectric layer 8, a second electrode 9 and an active layer 10. The first electrode 7 is located on the substrate 6. The interlayer dielectric layer 8 covers the substrate 6 and the first electrode 7; a first via k1 is provided on the interlayer dielectric layer 8, and the first via k1 exposes a portion of the first electrode 7. The second electrode 9 is located on the side of the interlayer dielectric layer 8 away from the substrate 6. The active layer 10 covers the first electrode 7 exposed to the first via k1, the hole wall of the first via k1 and at least a portion of the second electrode 9. Among them, the interlayer dielectric layer 8 extends from the device area 2 to the pixel area 3, and the pixel electrode 5 is located on the side of the interlayer dielectric layer 8 away from the substrate 6; the pixel electrode 5 and the second electrode 9 are arranged in the same layer and are connected to each other.

[0051] In a specific embodiment, the pixel electrode 5 and the second electrode 9 are made of the same material.

[0052] It can be understood that the pixel electrode 5 and the second electrode 9 are made of the same material and are arranged in the same layer, so that the pixel electrode 5 and the second electrode 9 can be formed in the same mask process; and, since the pixel electrode 5 and the second electrode 9 are arranged in the same layer and are connected to each other, the pixel electrode 5 and the second electrode 9 are two different parts in the same conductive film layer, and the two parts are directly contacted and connected. This design can not only save a mask process for making the pixel electrode 5, but also make the pixel electrode 5 and the second electrode 9 connected in an integrated manner in the same layer, avoiding overlapping of openings, thereby effectively reducing the production cost of the display panel 1.

[0053] Specifically, the substrate 6 may be a rigid substrate or a flexible substrate. The material of the substrate 6 includes glass, but is not limited thereto.

[0054] Specifically, the material of the first electrode 7 includes a metal material or a metal oxide material, which is not limited here.

[0055] Specifically, the display panel 1 further includes a first wiring 15 disposed in the same layer as the first electrode 7 , and the first wiring 15 is located in the non-display area B. It can be understood that the first wiring 15 and the first electrode 7 are made of the same material and are formed in the same process.

[0056] Of course, in other embodiments, the first wiring 15 may also be located in the display area A. For example, the first wiring 15 may be a data line located in the display area A and electrically connected to the first electrode 7 for transmitting a data signal to the first electrode 7, but is not limited thereto.

[0057] Specifically, the material of the interlayer dielectric layer 8 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide and titanium oxide. The interlayer dielectric layer 8 can be a single inorganic layer containing the above insulating materials, or a multi-layer stacked structure containing the above insulating materials.

[0058] Specifically, a via hole (such as the third via hole k3 described below) for exposing a portion of the first wiring 15 may be further provided on the interlayer dielectric layer 8 .

[0059] Specifically, one of the first electrode 7 and the second electrode 9 is a source electrode, and the other is a drain electrode.

[0060] Specifically, the materials of the second electrode 9 and the pixel electrode 5 include transparent metal oxide conductor materials.

[0061] In a specific embodiment, the material of the pixel electrode 5 and the second electrode 9 includes any one of indium tin oxide (ITO) and indium zinc oxide (IZO) or a combination of the two materials, but is not limited thereto.

[0062] It can be understood that, since the pixel electrode 5 and the second electrode 9 are arranged in the same layer, made of the same material and connected to each other, the electrical connection performance between the two is good, and overlapping of openings can be avoided, which is conducive to cost saving.

[0063] Specifically, the second electrode 9 has good light transmittance and good overlapping characteristics with the active layer 10 .

[0064] Specifically, the second electrode 9 is at least located on one side of the first via hole k1, for example, the second electrode 9 is located on one side of the first via hole k1; or, the second electrode 9 is located on the opposite side of the first via hole k1; or, the second electrode 9 is extended around the periphery of the first via hole k1.

[0065] Preferably, combined Figures 1 to 3 As shown, the second electrode 9 is extended around the periphery of the first via hole k1 , and at this time, the second electrode 9 is ring-shaped.

[0066] Specifically, Figures 1 to 3As shown, a second via hole k2 is provided on the second electrode 9; the second via hole k2 is aligned with and connected to the first via hole k1; the active layer 10 also covers the side wall of the second via hole k2; the aperture of the first via hole k1 close to the second via hole k2 is greater than or equal to the aperture of the second via hole k2 close to the first via hole k1.

[0067] It can be understood that the pattern of the second electrode 9 can be used to perform self-aligned etching on the interlayer dielectric layer 8 to form the first via k1 . This design can also save a photomask process.

[0068] It should be noted that when the first via k1 is manufactured by a self-alignment process, generally, the aperture of the first via k1 close to the second via k2 is equal to the aperture of the second via k2 close to the first via k1. When the interlayer dielectric layer 8 is over-etched, the aperture of the first via k1 close to the second via k2 may be slightly larger than the aperture of the second via k2 close to the first via k1.

[0069] Specific, combined Figure 1 and Figure 2 As shown, the active layer 10 is arranged in the first via hole k1 and extends to the side of the second electrode 9 away from the substrate 6. The active layer 10 covers the first electrode 7 in the first via hole k1, the hole wall of the first via hole k1, and the side of the second electrode 9 away from the substrate 6, and the active layer 10 located on the side of the second electrode 9 away from the substrate 6 is also extended around the periphery of the first via hole k1, so that the contact area between the active layer 10 and the second electrode 9 is maximized, thereby ensuring that the active layer 10 and the second electrode 9 have good overlapping characteristics.

[0070] Specifically, the material of the active layer 10 includes but is not limited to oxide semiconductor materials.

[0071] Specifically, Figure 1 and Figure 2 As shown, the thin film transistor 4 further includes a gate insulating layer 11 and a gate 12. The gate insulating layer 11 at least covers the active layer 10; of course, the gate insulating layer 11 may also cover the interlayer dielectric layer 8, the second electrode 9 and the pixel electrode 5. The gate 12 is at least arranged on one side of the gate insulating layer 11 away from the hole wall of the first via hole k1, that is, the gate 12 is at least arranged in the first via hole k1 and is arranged corresponding to the active layer 10 in the first via hole k1.

[0072] Preferably, if Figure 1 and Figure 2 As shown, the gate 12 is disposed in the first via hole k1 and extends around the periphery of the first via hole k1 , ensuring that the gate 12 can be completely disposed corresponding to the channel of the active layer 10 .

[0073] Specifically, Figure 1As shown, the display panel 1 further includes a passivation layer 13 covering the gate insulating layer 11 and the gate electrode 12 .

[0074] Specifically, Figure 1 As shown, for an FFS type display panel, the display panel 1 further includes a common electrode 14 located on the passivation layer 13, and the common electrode 14 is located at least in the pixel area 3. For a VA type display panel, it is not necessary to make a common electrode on the passivation layer 13, but the common electrode is disposed on another substrate.

[0075] It can be understood that the embodiments of the present application are described only by taking the FFS type display panel as an example.

[0076] It should be noted that when it is necessary to expand the capacitance between the pixel electrode 5 and the common electrode 14 due to driving requirements, the gate insulating layer 11 between the common electrode 14 and the pixel electrode 5 can be etched away. At this time, the gate insulating layer 11 can be self-aligned and etched using the pattern of the gate 12, thereby saving a photomask process.

[0077] Specifically, Figure 1 As shown, the display panel 1 may further include a second routing line 16 disposed in the same layer as the gate electrode 12 and located in the non-display area B. Part of the common electrode 14 is also formed in the non-display area B and overlapped on the first routing line 15 and the second routing line 16, thereby realizing the switching between routing lines of different layers.

[0078] The following describes in detail the manufacturing process of the display panel 1 provided in the embodiment of the present application.

[0079] like Figure 4 As shown, the manufacturing process of the display panel 1 provided in the embodiment of the present application includes the following steps S401 to S407.

[0080] S401: forming a first source-drain metal layer covering the substrate, and patterning the first source-drain metal layer using a first mask process (mask1) to form a first electrode.

[0081] like Figure 5 As shown, the first electrode 7 is formed on the substrate 6 , and the first electrode 7 is located in the display area A, specifically in the device area 2 .

[0082] In step S401, the first source-drain metal layer is patterned to form other electrodes or wiring structures disposed in the same layer as the first electrode 7, for example, Figure 5 The first wiring 15 shown is located in the non-display area B. Of course, in other embodiments, other electrodes or wiring structures disposed in the same layer as the first electrode 7 may also be located in the display area A.

[0083] S402: An interlayer dielectric material layer and a second source-drain metal layer covering the substrate and the first electrode are sequentially formed, and the second source-drain metal layer is patterned using a second mask process (mask2) to form a conductor pattern; the conductor pattern includes a first conductor portion used as a second electrode and a second conductor portion used as a pixel electrode.

[0084] like Figure 6 As shown, the interlayer dielectric material layer 17 covers the substrate 6, the first electrode 7 and the first wiring 15; the conductor pattern 18 is located in the display area A, and the conductor pattern 18 includes a first conductor portion 18a used as the second electrode and a second conductor portion 18b used as the pixel electrode 5.

[0085] Specifically, the first conductor portion 18a is located in the device region 2, and the second conductor portion 18b is located in the pixel region 3. The first conductor portion 18a and the second conductor portion 18b may be divided by a boundary between the device region 2 and the pixel region 3, but is not limited thereto.

[0086] S403: using a third mask process (mask3) to perform a hole opening process on the first conductor portion to form a second electrode having a second via hole, and using a self-alignment process to perform a patterning process on the interlayer dielectric material layer to form an interlayer dielectric layer having a first via hole.

[0087] like Figure 7 As shown, after the first conductor portion 18a is subjected to a hole-opening process, a second electrode 9 having a second via hole k2 is formed, and the interlayer dielectric material layer 17 is patterned by a self-alignment process to form an interlayer dielectric layer 8 having a first via hole k1.

[0088] In step S403, a photoresist pattern may be formed on the surface of the conductor pattern 18 and the interlayer dielectric material layer 17 by using an exposure and development technique, and then a second via hole k2 may be formed on the conductor pattern 18 by using a wet etching technique, and then a first via hole k1 may be formed on the interlayer dielectric material layer 17 by using a dry etching technique, and finally the photoresist pattern may be removed. It is understandable that when the interlayer dielectric material layer 17 is dry-etched, other positions of the interlayer dielectric material layer 17 may also be etched, and it is only necessary to open corresponding holes on the photomask so that other positions to be etched of the interlayer dielectric material layer 17 are exposed by the photoresist.

[0089] S404: forming a semiconductor layer covering the second electrode and the interlayer dielectric layer, and patterning the semiconductor layer using a fourth mask process (mask4) to form an active layer.

[0090] like Figure 8As shown, the active layer 10 is located in the first via hole k1 and extends to the side of the second electrode 9 away from the substrate 6 ; the active layer 10 located on the side of the second electrode 9 away from the substrate 6 also extends around the periphery of the first via hole k1 .

[0091] It can be understood that the active layer 10 covers the first electrode 7 in the first via hole k1 , the hole wall of the first via hole k1 , and the side of the second electrode 9 away from the substrate 6 .

[0092] S405: forming a gate insulating layer and a gate metal layer covering the interlayer dielectric layer and the active layer in sequence, and patterning the gate metal layer using a fifth mask process (mask5) to form a gate.

[0093] like Fig. 9 As shown, the gate insulating layer 11 covers the interlayer dielectric layer 8 , the active layer 10 , the pixel electrode 5 and the first wiring 15 , and the gate 12 is arranged in alignment with the active layer 10 .

[0094] It should be noted that the gate 12 is not required to be completely aligned with the edge of the active layer 10 , and the gate 12 only needs to cover at least the channel portion of the active layer 10 , that is, the gate 12 is at least disposed in the first via hole k1 .

[0095] Specifically, when the capacitance between the pixel electrode 5 and the common electrode above the pixel electrode 5 needs to be increased, the gate insulating layer 11 can be removed by self-aligning etching the gate insulating layer 11 using the patterned gate 12, thereby saving a photomask process.

[0096] Furthermore, in the process of patterning the gate metal layer, a second wiring 16 disposed in the same layer as the gate 12 may be formed. The second wiring 16 is located in the non-display area B, but is not limited thereto.

[0097] S406: forming a passivation material layer covering the gate insulating layer and the gate, and patterning the passivation material layer using a sixth mask process (mask6) to form a passivation layer.

[0098] like Fig.10 As shown, the passivation layer 13 covers the gate insulating layer 11 and the gate 12. After the passivation material layer is patterned, a third via hole k3 located in the non-display area B is formed, and the third via hole k3 exposes the first wiring 15 and the second wiring 16.

[0099] It is understandable that if the gate insulating layer 11 is not patterned in step S405 , the gate insulating layer 11 below the passivation layer 13 may be patterned simultaneously in step S406 , so that the third via hole k3 also penetrates the gate insulating layer 11 .

[0100] Specifically, when the display panel is a VA type liquid crystal display panel, the following step S407 is not required, that is, it is not required to form a common electrode located in the pixel area 3 on the passivation layer 13; when the display panel is an FFS type liquid crystal display panel, the following step S407 is required. Since the embodiment of the present application is described by taking the FFS type liquid crystal display panel as an example, the following step S407 is also required.

[0101] S407: forming a common electrode material layer covering the passivation layer, and patterning the common electrode material layer using a seventh mask process (mask7) to form a common electrode.

[0102] like Figure 1 As shown, the common electrode 14 is at least located in the pixel area 3 .

[0103] In a specific embodiment, part of the common electrode 14 is located in the third via hole k3 in the non-display area B, and is used to connect the first wiring 15 and the second wiring 16 to achieve switching between wirings of different layers.

[0104] It should be noted that the present application does not limit the specific position of the common electrode 14 , that is, for different types of display products, the position of the common electrode 14 can be adjusted according to driving requirements.

[0105] It can be understood that the substrate 6, the first electrode 7, the interlayer dielectric layer 8, the second electrode 9, the active layer 10, the gate insulating layer 11 and the gate 12 located in the device area 2 constitute a thin film transistor 4 with a vertical channel structure, and the FFS type display panel 1 provided in the embodiment of the present application only requires seven mask (7mask) processes to be completed, which can effectively reduce the production cost of the display panel 1.

[0106] In the display panel 1 provided in the embodiment of the present application, the first electrode 7, the second electrode 9, the active layer 10 and the gate 12 of the thin film transistor 4 in the device area 2 are distributed in a direction perpendicular to the substrate 6, and the channel is formed on the side wall of the first via hole k1 of the interlayer dielectric layer 8. The ultra-short channel at the nanometer or submicron level can be achieved by controlling the thickness of the interlayer dielectric layer 8, thereby achieving a high aperture ratio and a high charging rate; and, since the pixel electrode 5 and the second electrode 9 in the pixel area 3 are arranged in the same layer and are interconnected, the pixel electrode 5 and the second electrode 9 can be formed in the same mask process, which is conducive to saving a mask process for making the pixel electrode 5, thereby saving the production cost of the display panel 1; at the same time, the pixel electrode 5 and the second electrode 9 are arranged in the same layer and are interconnected, which can avoid increasing the overlap of the openings, thereby reducing the number of openings, and further reducing the production cost of the display panel 1; in addition, the first via hole k1 on the interlayer dielectric layer 8 can be formed by a self-alignment process, and a mask process for openings can be used, thereby further reducing the production cost of the display panel 1. Therefore, the display panel 1 provided in the embodiment of the present application can effectively reduce its manufacturing cost while achieving a high aperture ratio and a high charging rate.

[0107] like Fig.11 and Fig.12 As shown, an embodiment of the present application further provides a display panel 1', which is different from the aforementioned embodiment in that the pixel electrode 5' is arranged in the same layer as the active layer 10, the material of the active layer 10 is a semiconductor material, the material of the pixel electrode 5' is a conductive semiconductor material, and the material of the pixel electrode 5' contains all the chemical elements contained in the material of the active layer 10.

[0108] Specifically, the pixel electrode 5' is also connected to the active layer 10; Fig.11 As shown, the boundary between the pixel electrode 5' and the active layer 10 is the position shown by the dotted line L. When the active layer 10 pattern is made, the active layer 10 of the semiconductor material can be extended to the pixel area 3, and then the pixel electrode 5' is formed by conducting the active layer 10 at least in the pixel area 3, thereby saving a photomask process.

[0109] Specifically, the conductorization method includes dry etching, ion implantation, plasma hydrogen implantation or metal oxygen absorption, but is not limited thereto.

[0110] Specifically, the material of the active layer 10 includes a metal oxide semiconductor material, and the material is a transparent material.

[0111] Specifically, in the embodiment of the present application, the material of the second electrode 9 includes a metal material or a metal oxide conductor material. It is understandable that the material of the second electrode 9 in the display panel 1' provided in this embodiment can be a transparent conductor material or an opaque conductor material, as long as the overlap property with the active layer 10 is good.

[0112] Specifically, Fig.11 and Fig.12 As shown, the edge of the gate electrode 12 of the thin film transistor 4 close to the pixel electrode 5 ′ is completely overlapped with the edge of the pixel electrode 5 ′ close to the gate electrode 12 .

[0113] It is understandable that the gate electrode 12 can be directly used as a mask to conduct the extended portion of the active layer 10 not blocked by the gate electrode 12 to form the pixel electrode 5 ′, thereby saving one photomask and helping to reduce the number of photomasks.

[0114] It can be understood that since the embodiment of the present application needs to use the gate 12 as a mask to conduct the extended portion of the active layer 10 not blocked by the gate 12, the gate 12 in the embodiment of the present application must not only be located in the first via hole k1 but also extend around the periphery of the first via hole k1, so that the gate 12 can cover at least part of the active layer 10 on the second electrode 9.

[0115] In a specific embodiment, the edge of the gate insulating layer 11 is aligned with the edge of the gate 12, that is, the orthographic projection of the gate insulating layer 11 on the substrate 6 is completely overlapped with the orthographic projection of the gate 12 on the substrate 6, or in other words, in the orthographic viewing direction of the display panel 1', the gate insulating layer 11 is completely overlapped with the gate 12. At this time, the gate insulating layer 11 is formed by etching through a self-alignment process.

[0116] It should be noted that the normal viewing angle direction of the display panel 1 ′ refers to the direction in which the display area is observed by human eyes.

[0117] Of course, in other embodiments, the edge of the gate insulating layer 11 may also exceed the edge of the gate 12 .

[0118] Specifically, when ion implantation or plasma hydrogen implantation is used for conductorization, the gate insulating layer 11 located in the pixel area 3 can be retained. In this case, the edge of the gate insulating layer 11 can extend beyond the edge of the gate 12. However, when other methods are used for conductorization, in order to prevent the gate insulating layer 11 from interfering with the conductorization effect, it is necessary to remove at least the gate insulating layer 11 located in the pixel area 3. In this case, the gate 12 can be used to perform self-aligned etching on the gate insulating layer 11, so that at least the active layer 10 located in the pixel area 3 is exposed, which is convenient for implementing subsequent conductorization steps. At this time, the edge of the gate insulating layer 11 is aligned with the edge of the gate 12.

[0119] Of course, when the gate insulating layer 11 is etched using a self-aligned process, the morphology of the side surface of the etched gate insulating layer 11 may be different depending on the selectivity of the etching material. In some embodiments, the sidewall positions of the gate 12 and the gate insulating layer 11 may be stepped.

[0120] Specifically, Fig.11 As shown, the pixel electrode 5' extends from the interlayer dielectric layer 8 to cover part of the second electrode 9; the edge of the pixel electrode 5' located on the second electrode 9 close to the gate 12 is completely overlapped with the edge of the gate 12 close to the pixel electrode 5'. In other words, the edge of the gate 12 close to the pixel electrode 5' cannot exceed the edge of the second electrode 9 close to the pixel electrode 5', so as to ensure that the formed pixel electrode 5' can be partially located on the second electrode 9, avoid the contact position resistance of the second electrode 9 and the pixel electrode 5' is too high, thereby ensuring that the second electrode 9 and the pixel electrode 5' have good overlapping characteristics.

[0121] Specifically, other structures of the display panel 1 ′ provided in the embodiment of the present application may refer to the aforementioned embodiment, which will not be described in detail here.

[0122] Specifically, the display panel 1' provided in the embodiment of the present application can also be manufactured through the 7mask process. Unlike the aforementioned embodiment, the display panel 1' provided in the embodiment of the present application needs to use the gate 12 as a mask to conduct the active layer 10 not blocked by the gate 12 after forming the gate 12. This process does not require the addition of a mask process.

[0123] like Fig.13 As shown, the manufacturing process of the display panel 1 ′ provided in the embodiment of the present application includes steps S1301 to S1308 .

[0124] S1301: forming a first source-drain metal layer covering the substrate, and patterning the first source-drain metal layer using a first mask process (mask1) to form a first electrode.

[0125] The manufacturing process of the first electrode in the embodiment of the present application is the same as the manufacturing process of the first electrode in the above embodiment, and can be referred to Figure 5 The structure shown will not be described in detail here.

[0126] S1302: sequentially forming an interlayer dielectric material layer and a second source-drain metal layer covering the substrate and the first electrode, and patterning the second source-drain metal layer using a second mask process (mask2) to form a conductor pattern.

[0127] like Fig.14 As shown, the interlayer dielectric material layer 17 covers the substrate 6 , the first electrode 7 and the first wiring 15 ; different from the above embodiment, the conductor pattern 18 ′ in the embodiment of the present application is located in the device area 2 and does not need to extend to the pixel area 3 .

[0128] S1303: using a third mask process (mask3) to perform a hole-opening process on the conductor pattern to form a second electrode having a second via hole, and using a self-alignment process to perform a patterning process on the interlayer dielectric material layer to form an interlayer dielectric layer having a first via hole.

[0129] like Fig.15 As shown, after the conductor portion 18' is subjected to a hole-opening process, a second electrode 9 having a second via hole k2 is formed, and the interlayer dielectric material layer 17 is patterned by a self-alignment process to form an interlayer dielectric layer 8 having a first via hole k1.

[0130] The preparation process of the interlayer dielectric layer in the embodiment of the present application is the same as that in the above embodiment, and will not be repeated here.

[0131] S1304: forming a semiconductor layer covering the second electrode and the interlayer dielectric layer, and patterning the semiconductor layer using a fourth mask process (mask4) to form a semiconductor pattern; the semiconductor pattern includes a first semiconductor portion covering the first electrode, the side wall of the first via hole and a portion of the second electrode, and a second semiconductor portion located on a portion of the second electrode and the interlayer dielectric layer.

[0132] like Fig.16 As shown, the semiconductor pattern 19 includes a first semiconductor portion 19a covering the first electrode 7, the side wall of the first via k1 and a portion of the second electrode 9, and a second semiconductor portion 19b located on a portion of the second electrode 9 and the interlayer dielectric layer 8; wherein the first semiconductor portion 19a is used as the active layer 10, and the second semiconductor portion 19b is used to form a pixel electrode after conductorization treatment in a subsequent process.

[0133] Specifically, the dividing line between the first semiconductor portion 19 a and the second semiconductor portion 19 b is where the dotted line L is located.

[0134] S1305: sequentially forming a gate insulating material layer and a gate metal layer covering the interlayer dielectric layer and the semiconductor pattern, patterning the gate metal layer using the fifth mask (mask5) process to form a gate, and patterning the gate insulating material layer through a self-alignment process to form a gate insulating layer.

[0135] like Fig.17 As shown, the patterns of the gate insulating layer 11 and the gate 12 formed in the display area A are consistent. In the process of patterning the gate metal layer, a second wiring 16 arranged in the same layer as the gate 12 can also be formed; the second wiring 16 is located in the non-display area B, and the gate insulating layer 11 is also provided below the second wiring 16. It can be understood that the patterns of the gate insulating layer 11 below the second wiring 16 are also consistent with those of the second wiring 16.

[0136] Specifically, the first semiconductor portion 19a is covered by the gate 12, while the second semiconductor portion 19b is not covered by the gate 12. It can be understood that the boundary between the first semiconductor portion 19a and the second semiconductor portion 19b corresponds to the edge of the gate 12.

[0137] S1306: Conducting the second semiconductor portion using the gate electrode as a mask to form a pixel electrode.

[0138] like Fig.18 As shown, the second semiconductor portion 19 b is subjected to a conductorization process using the gate electrode 12 as a mask to form a pixel electrode 5 ′ at least located in the pixel region 3 .

[0139] It can be understood that in order to ensure that the formed pixel electrode 5' has good overlap with the second electrode 9, the gate 12 cannot cover the edge portion of the second electrode 9 close to the second semiconductor portion 19b. Therefore, the second semiconductor portion 19b also covers the edge of the second electrode 9, so that the pixel electrode 5' formed by conductorization also covers the edge of the second electrode 9.

[0140] Specifically, the second semiconductor portion 19b of the semiconductor material is transformed into a conductive semiconductor material after being subjected to a conductive treatment, thereby forming the pixel electrode 5'. The conductive method has been described in detail above and will not be repeated here.

[0141] S1307: forming a passivation material layer covering the interlayer dielectric layer, the second electrode, the gate insulating layer and the gate, and patterning the passivation material layer using a sixth mask process (mask6) to form a passivation layer.

[0142] like Fig.19As shown, the passivation layer 13 at least covers the gate electrode 12 and the pixel electrode 5 ′. After the passivation material layer is patterned, a third via hole k3 is formed, and the third via hole k3 exposes the first wiring 15 and the second wiring 16 .

[0143] Specifically, when the display panel is a VA type liquid crystal display panel, the following step S407 is not required, that is, it is not required to form a common electrode located in the pixel area 3 on the passivation layer 13; when the display panel is an FFS type liquid crystal display panel, the following step S1308 is required. Since the embodiment of the present application is described by taking the FFS type liquid crystal display panel as an example, the following step S1308 is also required.

[0144] S1308: forming a common electrode material layer covering the passivation layer, and patterning the common electrode material layer using a seventh mask process (mask7) to form a common electrode.

[0145] like Fig.11 As shown, the common electrode 14 is located in the pixel area 3 .

[0146] In a specific embodiment, part of the common electrode 14 is located in the third via hole k3 in the non-display area B, and is used to connect the first wiring 15 and the second wiring 16 to achieve switching between wirings of different layers.

[0147] It should be noted that the present application does not limit the specific position of the common electrode 14 , that is, for different types of display products, the position of the common electrode 14 can be adjusted according to driving requirements.

[0148] It can be understood that the substrate 6, the first electrode 7, the interlayer dielectric layer 8, the second electrode 9, the active layer 10, the gate insulating layer 11 and the gate 12 located in the device area 2 constitute a thin film transistor 4 with a vertical channel structure, and the FFS type display panel 1' provided in the embodiment of the present application only needs seven mask (7mask) processes to be completed, which can effectively reduce the production cost of the display panel 1'.

[0149] In the display panel 1' provided in the embodiment of the present application, the first electrode 7, the second electrode 9, the active layer 10 and the gate 12 of the thin film transistor 4 in the device area 2 are distributed in a direction perpendicular to the substrate 6, and the channel is formed on the side wall of the first via hole k1 of the interlayer dielectric layer 8. The ultra-short channel at the nanometer or submicron level can be achieved by controlling the thickness of the interlayer dielectric layer 8, thereby achieving a high aperture ratio and a high charging rate; and, since the pixel electrode 5' in the pixel area 3 is arranged in the same layer as the active layer 10, the pixel electrode 5' and the active layer 10 can be formed in the same mask process, which can save a mask process for making the pixel electrode 5', thereby saving the production cost of the display panel 1'; at the same time, part of the pixel electrode 5' covers the second electrode 9, which can avoid increasing the overlap of the openings, thereby reducing the number of openings, and further reducing the production cost of the display panel 1'; in addition, the first via hole k1 on the interlayer dielectric layer 8 can be formed by a self-alignment process, which can be used for a mask process for the openings, thereby further reducing the production cost of the display panel 1'. Therefore, the display panel 1 ′ provided in the embodiment of the present application can achieve a high aperture ratio and a high charging rate while effectively reducing its manufacturing cost.

[0150] like Fig. 20 As shown, the embodiment of the present application further provides a display device 20, which includes a color filter substrate 21, a liquid crystal layer 22 and a display panel 1, 1' as described in any one of the above embodiments; the color filter substrate 21 is arranged opposite to the display panel 1, 1', and the liquid crystal layer 22 is located between the color filter substrate 21 and the display panel 1, 1'.

[0151] Specifically, the color filter substrate 21 may also be replaced by an opposing substrate. In this case, the color filter layer is disposed in the display panel 1, 1'.

[0152] The display panel 20 provided in the embodiment of the present application has a high aperture ratio and a high charging rate, and has a low manufacturing cost.

[0153] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0154] The above is a detailed introduction to a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solution to deviate from the scope of the technical solution of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises a display area and a non-display area which are adjacent to each other, the display area comprises a plurality of pixel units arranged in an array, and each of the pixel units comprises a device area and a pixel area which are adjacent to each other; the display panel comprises a substrate located in the display area and the non-display area, a thin film transistor located in the device area, and a pixel electrode located in the pixel area; The thin film transistor comprises: A first electrode, located on the substrate; an interlayer dielectric layer, covering the substrate and the first electrode; a first via hole is provided on the interlayer dielectric layer, and the first via hole exposes at least a portion of the first electrode; A second electrode is located on a side of the interlayer dielectric layer away from the substrate; an active layer, covering the first electrode exposed to the first via hole, a hole wall of the first via hole, and at least a portion of the second electrode; The interlayer dielectric layer extends from the device area to the pixel area, the pixel electrode is located on a side of the interlayer dielectric layer away from the substrate and is connected to the second electrode; the pixel electrode is arranged in the same layer as the second electrode or the active layer.

2. The display panel according to claim 1, characterized in that: The pixel electrode and the second electrode are arranged in the same layer; the pixel electrode and the second electrode are made of the same material and include a transparent metal oxide conductor material.

3. The display panel according to claim 2, characterized in that: The material of the pixel electrode and the second electrode includes any one of indium tin oxide and indium zinc oxide or a combination of the two materials.

4. The display panel according to claim 1, characterized in that: The pixel electrode is arranged in the same layer as the active layer; the material of the active layer is a semiconductor material, the pixel electrode is a conductive semiconductor material, and the material of the pixel electrode contains all the chemical elements contained in the material of the active layer.

5. The display panel according to claim 4, characterized in that: The material of the active layer includes a metal oxide semiconductor material; the material of the second electrode includes a metal material or a metal oxide conductor material.

6. The display panel according to claim 4, characterized in that: The thin film transistor further comprises a gate insulating layer and a gate; the gate insulating layer at least covers the active layer; the gate is located on a side of the gate insulating layer away from the substrate and is arranged in alignment with the active layer; The edge of the gate electrode close to the pixel electrode is completely overlapped with the edge of the pixel electrode close to the gate electrode.

7. The display panel according to claim 6, characterized in that: The edge of the gate insulating layer is aligned with the edge of the gate.

8. The display panel according to claim 6, characterized in that: The pixel electrode extends from the interlayer dielectric layer to cover a portion of the second electrode; an edge of the pixel electrode on the second electrode close to the gate is completely overlapped with an edge of the gate close to the pixel electrode.

9. The display panel according to claim 1, characterized in that: A second via hole is provided on the second electrode; the second via hole is aligned with and connected to the first via hole; the active layer also covers the side wall of the second via hole; the aperture of the first via hole close to the second via hole is greater than or equal to the aperture of the second via hole close to the first via hole.

10. The display panel according to claim 1, characterized in that: The display panel further includes a gate insulating layer and a gate; the gate insulating layer at least covers the active layer; and the gate is at least arranged on a side of the gate insulating layer away from a hole wall of the first via hole.

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