Low-power-consumption control circuit, chip and electronic equipment
By designing a low-power control circuit in the chip and controlling data signal transmission using gated clocks and flip-flops, the problem that combined logic power consumption in the prior art cannot be reduced is solved, and the zero flip rate when the module is not in use is achieved. Significantly reduces the dynamic power consumption of the chip.
Patent Information
- Application Number
- CN202421039430.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-13
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2034-05-13
AI Technical Summary
The prior art cannot effectively reduce the power consumption of the combined logic when the module is not working, resulting in an increase in the dynamic power consumption of the chip.
Design a low-power control circuit, through the combination of timing logic circuit and combination logic circuit, the gated clock and flip-flop are used to control the transmission of data signals, ensuring that the combined logic does not flip with the data when the module is not in use, thereby reducing dynamic work. Consumption.
The internal signal flip rate is achieved at 0% when the circuit module is not in use, which significantly reduces the dynamic power consumption of the chip.
Smart Images
Figure CN222281126U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip technology, and in particular to a low-power control circuit, chip and electronic device. Background Art
[0002] The clock is one of the important components of the chip. The use of reasonable clock management, such as more flexible clock control strategies and gated clock technology, can reduce the invalid flipping of the device so as to effectively reduce the power consumption of the chip. The gated clock technology means that in the actual working process of the chip, when a module circuit in the system completes the established task (such as image mirroring operation), the clock driving the module stops flipping through the control of the gated clock enable signal, and the corresponding timing element is no longer updated, then the combinational logic in between also stops flipping. At this time, the power consumption of the module is equivalent to the static power consumption, which can reduce the power consumption of the entire system. However, the above solution has a disadvantage: when the module is not working, it can only reduce the power consumption of the device using the clock signal, but the combinational logic in it still flips with the change of data, so the power consumption of the combinational logic is not eliminated.
[0003] In view of the above problems, those skilled in the art have been seeking solutions. Utility Model Content
[0004] The technical problem to be solved by the present application is to provide a low-power control circuit, chip and electronic device in view of the defects of the above-mentioned prior art.
[0005] In order to achieve the above objectives, this application is implemented through the following technical solutions:
[0006] The present application provides a low power consumption control circuit, comprising:
[0007] A sequential logic circuit for controlling an output data signal according to a clock signal;
[0008] A combinational logic circuit for receiving the data signal and combining and outputting it;
[0009] One end of the sequential logic circuit is electrically connected to an external data signal output device, and the other end of the sequential logic circuit is electrically connected to the combinational logic circuit;
[0010] The sequential logic circuit includes: a gated clock and at least one trigger;
[0011] The gated clock is used to control the output clock signal;
[0012] The trigger is connected to the gated clock, and is used to output the data signal when the clock signal is received, and temporarily store the data signal when the clock signal is not received.
[0013] Optionally, the trigger includes at least a clock signal input interface, a data signal input interface, and a data signal output interface;
[0014] The clock signal input interface is electrically connected to the gated clock and is used to receive the clock signal;
[0015] The data signal input interface is electrically connected to an external data signal output device and is used to receive the data signal;
[0016] The data signal output interface is electrically connected to the combinational logic circuit and is used to output the data signal to the combinational logic circuit.
[0017] Optionally, the combinational logic circuit includes at least one inverter and an AND gate circuit;
[0018] The signal input terminal of the inverter is connected to the corresponding trigger, and is used to output an inverted signal according to the data signal;
[0019] The AND gate circuit is connected to the signal output ends of the plurality of inverters, and is used for combining and outputting the plurality of inverted signals.
[0020] Optionally, the inverter includes a first switch and a second switch; control ends of the first switch and the second switch are connected and serve as signal input ends of the inverter, first path ends of the first switch and the second switch are connected and serve as signal output ends of the inverter, the second path end of the first switch is grounded, and the second path end of the second switch is connected to an external power supply.
[0021] Optionally, the AND gate circuit includes at least three groups of first switches and second switches; wherein, the control ends of two groups of the first switches and the second switches are connected as the first signal input end and the second signal input end of the AND gate circuit respectively, and the first path ends of one group of the first switches and the second switches are connected and serve as the signal output end of the AND gate circuit.
[0022] Optionally, the trigger is a D trigger, including a master D latch and a slave D latch; the master D latch and the slave D latch are connected in series, the signal input end of the master D latch is the data signal input interface of the trigger, and the signal output end of the slave D latch is the data signal output interface of the trigger.
[0023] Optionally, the low power consumption control circuit further includes a power management module; the power management module is electrically connected to the supply voltage and the load, and is used to dynamically adjust the supply voltage according to the load.
[0024] Optionally, the low power consumption control circuit further includes a timing voltage control module;
[0025] The timing voltage control module is connected to the gated clock and the power supply voltage, and is used to output a first voltage to a first timing zone of a load, and / or output a second voltage to a second timing zone of the load.
[0026] The present application also provides a chip, comprising the low-power consumption control circuit as described above.
[0027] The present application also provides an electronic device, comprising the chip as described above.
[0028] The present application provides a low-power control circuit, chip and electronic device, which can reduce the flip rate of internal signals when the circuit module is not in use, thereby reducing the dynamic power consumption of the chip.
[0029] In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following specifically cites preferred embodiments and describes them in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The present application is described in detail below with reference to the accompanying drawings and specific implementation methods;
[0031] Figure 1 It is a circuit function module diagram of the prior art provided by an embodiment of the present application.
[0032] Figure 2 It is a schematic diagram of the structure of the circuit function of the prior art provided by an embodiment of the present application.
[0033] Figure 3 It is a module schematic diagram of a low power consumption control circuit provided in one embodiment of the present application.
[0034] Figure 4 It is a structural schematic diagram of a low power consumption control circuit provided in one embodiment of the present application.
[0035] Figure 5 It is a timing diagram of a data signal of the prior art provided by an embodiment of the present application.
[0036] Figure 6 It is a timing diagram of the data signal of the present application provided by an embodiment of the present application.
[0037] Figure 7 It is a schematic diagram of the structure of an inverter provided in one embodiment of the present application.
[0038] Figure 8 It is a schematic diagram of the structure of an AND gate circuit provided in one embodiment of the present application. DETAILED DESCRIPTION
[0039] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0040] With the improvement of integrated circuit process and technological development, the operating frequency and integration of chips are constantly increasing, which also leads to a rapid increase in the power consumption of electronic devices. Power consumption has two main negative effects on circuits: first, short battery life; second, increased power consumption will cause the chip temperature to rise, which in turn affects the performance and packaging cost of the device. For industrial-grade and automotive-grade chips, the negative impact of power consumption is not very obvious. For consumer-grade chips, since they are often used in small mobile devices (such as mobile phones, digital cameras, translation pens, and phone watches, etc.), the optimization of performance and area is currently limited by the manufacturing process. How to reduce power consumption is a key issue in digital IC (Integrated Circuit) design.
[0041] Chip power consumption is divided into static power consumption and dynamic power consumption. Static power consumption is also called leakage current, which refers to the power consumption generated by leakage current when the circuit is in a waiting or inactive state. Under the 130 nm process, static power consumption is relatively small and can be ignored. Dynamic power consumption refers to the power consumption consumed during the circuit logic transformation process, which is caused by changes in current input or related connection voltage, and has nothing to do with whether the output of the circuit changes. Dynamic power consumption is divided into short-circuit power consumption and flip power consumption, which is the main component of integrated circuit power consumption. Short-circuit power consumption is internal power consumption, which refers to the power consumption caused by the instantaneous short circuit caused by the simultaneous conduction of the P tube and the N tube inside the device at a certain moment. Flip power consumption is caused by the charging and discharging of the output load capacitor of the CMOS device.
[0042] The clock signal is the signal with the highest switching rate in digital IC chips. The power consumption caused by the clock network flip can reach 30% of the chip power consumption, or even higher. And even if the input and output signals remain unchanged, the trigger that receives the clock will consume a certain amount of power. Therefore, among many low-power technologies, gated clock has the strongest inhibitory effect on flip power consumption and internal power consumption.
[0043] Based on the above, this solution provides a low-power control circuit, chip and electronic device.
[0044] Figure 1 is a circuit function module diagram of the prior art provided by an embodiment of the present application, Figure 2 is a schematic diagram of the structure of the circuit function of the prior art provided by an embodiment of the present application, such as Figure 1 The circuit function module includes a combinational logic circuit and a sequential logic circuit. The data data_in passes through the combinational logic circuit and then enters the sequential logic circuit. The gated clock (not shown) outputs a clock signal clk_gating. The sequential logic circuit controls the output of the final data signal da_out_gating according to the clock signal clk_gating. Specifically, Figure 2The combinational logic circuit includes at least two data inputs da_in1 and da_in2, which respectively pass through corresponding inverters and enter the AND gate circuit. The AND gate circuit outputs the data signal da_in3 to the trigger D interface in the sequential logic circuit; at the same time, the gated clock outputs the clock signal clk to the trigger C interface in the sequential logic circuit. When the trigger detects the rising edge of the clock signal, the data signal da_in3 is output as da_in4. In this existing solution, when the gated clock stops outputting the clock signal, the power consumption of the device using the clock signal, that is, the power consumption of the trigger, can be reduced. However, before this, the combinational logic still flips with the change of data, and there is flipping power consumption, so the power consumption of the combinational logic is not eliminated.
[0045] Figure 3 is a module schematic diagram of a low power consumption control circuit provided in an embodiment of the present application, Figure 4 This is a schematic diagram of the structure of a low power consumption control circuit provided by an embodiment of the present application. Figure 3 and Figure 4 , the present application provides a low power consumption control circuit, comprising:
[0046] A sequential logic circuit for controlling an output data signal according to a clock signal;
[0047] Combinational logic circuit for receiving data signals and combining them for output;
[0048] One end of the sequential logic circuit is electrically connected to an external data signal output device, and the other end of the sequential logic circuit is electrically connected to a combinational logic circuit;
[0049] The sequential logic circuit includes: a gated clock and at least one trigger;
[0050] The gated clock is used to control the output clock signal;
[0051] The trigger is connected to the gated clock and is used to output a data signal when a clock signal is received and temporarily store the data signal when no clock signal is received.
[0052] like Figure 3 , the application adjusts the transmission path of the data signal to: first pass through the sequential logic circuit, and then output through the combinational logic circuit. The gated clock (not shown) outputs the clock signal clk_gating, the sequential logic circuit controls the data signal data_in to output as the data signal data_gating according to the clock signal clk_gating, and the combinational logic circuit outputs the final data signal da_out_gating. Specifically, Figure 4, the combinational logic circuit includes at least two data inputs da_in1 and da_in2, which are respectively output to the corresponding trigger D interface, and each trigger has a C interface for receiving the clock signal clk; when the trigger detects the rising edge of the clock signal, the data signal da_in1 is output as da_in1_1, and the data signal da_in2 is output as da_in2_1; the data signals da_in1_1 and da_in2_1 respectively pass through the corresponding inverters and enter the AND gate circuit, and the AND gate circuit outputs the final data signal da_in3. In this scheme, after the data signal enters the circuit function module, the transmission is controlled by the trigger in the sequential logic circuit: when the trigger receives the clock signal, the data signal can be output to the combinational logic circuit; when the clock signal is not received, the data signal is temporarily stored, and the data signal cannot be output to the combinational logic circuit. The combinational logic circuit will not flip with the data change, so there is no flip power consumption, and the internal signal flip rate can be achieved at 0% when the circuit function module is not in use, thereby effectively reducing the dynamic power consumption of the chip.
[0053] Figure 5 is a timing diagram of a data signal of the prior art provided by an embodiment of the present application, Figure 6 This is a timing diagram of the data signal of the present application provided by an embodiment of the present application. Please also refer to Figure 5 and Figure 6 , where CLK is a timing diagram of a clock signal, da_in1 is a timing diagram of a first data signal, da_in2 is a timing diagram of a second data signal, and da_in1_1 is a timing diagram of a first data signal.
[0054] like Figure 5 In the timing diagram of the data signal of the prior art, the first data signal da_in1_1 and the second data signal da_in2_1 are the level changes of two groups of data signals in the combinational logic circuit. It can be seen that the frequency of level changes in the combinational logic circuit is high. That is, when the gated clock stops outputting the clock signal, the combinational logic still flips with the data change, and the flipping power consumption is high.
[0055] like Figure 6 In the timing diagram of the data signal of the present application, the first data signal da_in1_1, da_in1_2 and the second data signal da_in2_1, da_in2_2 are the level changes of two groups of data signals in the combinational logic circuit. It can be seen that the frequency of the level change in the combinational logic circuit is higher than that of Figure 5 It is significantly reduced, that is, when the gated clock stops outputting the clock signal, there is no data change in the combinational logic circuit, the flip rate of the combinational logic circuit is low, and the flip power consumption is as low as 0%.
[0056] Optionally, the trigger includes at least a clock signal input interface C, a data signal input interface D, and a data signal output interface Q;
[0057] The clock signal input interface C is electrically connected to the gated clock and is used to receive the clock signal;
[0058] The data signal input interface D is electrically connected to an external data signal output device and is used to receive a data signal;
[0059] The data signal output interface Q is electrically connected to the combinational logic circuit and is used to output the data signal to the combinational logic circuit.
[0060] Optionally, the combinational logic circuit includes at least one inverter and an AND gate circuit;
[0061] The signal input terminal of the inverter is connected to the corresponding trigger, and is used to output an inverted signal according to the data signal;
[0062] The AND gate circuit is connected to the signal output terminals of the plurality of inverters and is used for combining and outputting the plurality of inverted signals.
[0063] Figure 7 is a schematic diagram of the structure of an inverter provided in an embodiment of the present application, please refer to Figure 7 , the inverter includes a first switch Mn and a second switch Mp; the control ends of the first switch Mn and the second switch Mp are connected and used as the signal input end Vin of the inverter, the first channel ends of the first switch Mn and the second switch Mp are connected and used as the signal output end Vout of the inverter, the second channel end of the first switch Mn is grounded, and the second channel end of the second switch Mp is connected to the external power supply VDD. Among them, the first switch Mn is an NMOS tube, and the second switch Mp is a PMOS tube. When the input to the common gate Vin of the two is higher than the threshold voltage, the PMOS is turned off and the NMOS is turned on, so the output Vout is equivalent to connecting to GND and pulling low, and when the input Vin is lower than the threshold voltage, the PMOS is turned on and the NMOS is turned off, so the output Vout is equivalent to connecting to VDD and pulling high.
[0064] Figure 8 This is a schematic diagram of the structure of an AND gate circuit provided in an embodiment of the present application. Figure 8The AND gate circuit includes at least three groups of first switches and second switches: first switches NMOS-Q3, Q4, Q6, and second switches PMOS-Q1, Q2, Q5. The gates of the first switch Q3 and the second switch Q1 are connected as the first signal input terminal A of the AND gate circuit, the gates of the first switch Q4 and the second switch Q2 are connected as the second signal input terminal B of the AND gate circuit, the gates of the first switch Q6 and the second switch Q5 are connected and connected to the drains of the second switches Q1, Q2, and the first switch Q3, the drains of the first switch Q6 and the second switch Q5 are connected and serve as the signal output terminal O of the AND gate circuit, and the sources of the second switches Q1, Q2, and Q5 are all connected to the external power supply VDD. The source of the first switch Q3 is connected to the drain of the first switch Q4, and the sources of the first switch Q4 and the first switch Q6 are grounded.
[0065] The trigger is a D trigger, including a master D latch and a slave D latch; the master D latch and the slave D latch are connected in series, the signal input end of the master D latch is the data signal input interface of the trigger, and the signal output end of the slave D latch is the data signal output interface of the trigger. The D trigger is actually two D latches connected in series, the first D latch is called Master, and the second D latch is called Slave. The output of the Master is used as the input of the Slave, but the clock enable inputs of the two D latches are just opposite.
[0066] Optionally, the low power consumption control circuit further includes a power management module; the power management module is electrically connected to the supply voltage and the load, and is used to dynamically adjust the supply voltage according to the load. Specifically, the load may be other functional modules of the chip, and the operating voltage may be dynamically adjusted according to the working load of the chip to achieve the purpose of power consumption optimization.
[0067] Optionally, the low-power control circuit also includes a timing voltage control module; the timing voltage control module is connected to the gated clock and the power supply voltage, and is used to output a first voltage to the first timing zone of the load, and / or output a second voltage to the second timing zone of the load. Specifically, the chip is divided into independent "voltage domains", and different power supply voltages are used according to the timing requirements of each area, thereby reducing power consumption from the perspective of lowering voltage. For example, modules with strict timing requirements are operated at standard voltage (1 V for 90 nm process); paths with less strict timing requirements can be arranged in other low-voltage areas, such as 0.8V.
[0068] The present application also provides a chip, comprising the low-power consumption control circuit as described above.
[0069] The present application also provides an electronic device, comprising the chip as described above.
[0070] Compared with the existing design scheme, the advantage of this application is that when the circuit module is not working, the signal inside the functional module can achieve a flip rate of 0%. At the same time, the new design adopts specific data input and output rules. The specific data rule means that the data is combined with logic output in each module of the chip, and then captured by the sequential logic after entering the module. It only adjusts the position of the combinational logic and the sequential logic, and has no effect on the chip area. Therefore, without changing the area, the solution proposed in this application significantly reduces the dynamic power consumption of the combinational logic inside the circuit module.
[0071] Obviously, those skilled in the art can make various changes and modifications to the utility model without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these changes and variations. The technical features of the above-described embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0072] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions or improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims
1. A low power consumption control circuit, characterized in that: include: A sequential logic circuit for controlling an output data signal according to a clock signal; A combinational logic circuit for receiving the data signal and combining and outputting it; One end of the sequential logic circuit is electrically connected to an external data signal output device, and the other end of the sequential logic circuit is electrically connected to the combinational logic circuit; The sequential logic circuit includes: a gated clock and at least one trigger; The gated clock is used to control the output clock signal; The trigger is connected to the gated clock, and is used to output the data signal when the clock signal is received, and temporarily store the data signal when the clock signal is not received.
2. The circuit according to claim 1, characterized in that The trigger at least includes a clock signal input interface, a data signal input interface, and a data signal output interface; The clock signal input interface is electrically connected to the gated clock and is used to receive the clock signal; The data signal input interface is electrically connected to an external data signal output device and is used to receive the data signal; The data signal output interface is electrically connected to the combinational logic circuit and is used to output the data signal to the combinational logic circuit.
3. The circuit according to claim 2, characterized in that The combinational logic circuit includes at least one inverter and an AND gate circuit; The signal input terminal of the inverter is connected to the corresponding trigger, and is used to output an inverted signal according to the data signal; The AND gate circuit is connected to the signal output ends of the plurality of inverters, and is used for combining and outputting the plurality of inverted signals.
4. The circuit according to claim 3, characterized in that The inverter includes a first switch and a second switch; control ends of the first switch and the second switch are connected and serve as signal input ends of the inverter, first path ends of the first switch and the second switch are connected and serve as signal output ends of the inverter, the second path end of the first switch is grounded, and the second path end of the second switch is connected to an external power supply.
5. The circuit according to claim 4, characterized in that The AND gate circuit includes at least three groups of first switches and second switches; wherein the control ends of two groups of the first switches and the second switches are connected as the first signal input end and the second signal input end of the AND gate circuit respectively, and the first path ends of one group of the first switches and the second switches are connected and serve as the signal output end of the AND gate circuit.
6. The circuit according to claim 2, characterized in that The trigger is a D trigger, including a master D latch and a slave D latch; the master D latch and the slave D latch are connected in series, the signal input end of the master D latch is the data signal input interface of the trigger, and the signal output end of the slave D latch is the data signal output interface of the trigger.
7. The circuit according to claim 1, characterized in that The low power consumption control circuit further comprises a power management module; the power management module is electrically connected to the supply voltage and the load, and is used for dynamically adjusting the supply voltage according to the load.
8. The circuit according to claim 7, characterized in that The low power consumption control circuit also includes a timing voltage control module; The timing voltage control module is connected to the gated clock and the power supply voltage, and is used to output a first voltage to a first timing zone of a load, and / or output a second voltage to a second timing zone of the load.
9. A chip, characterized in that: The invention comprises a low power consumption control circuit as claimed in any one of claims 1 to 8.
10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.