Storage device with low latency characteristics

By selecting a combination of transistors and floating-gate transistors, along with a cache and main controller, the problem of data errors in high-density NAND flash memory storage is solved, resulting in a low-latency, high-reliability storage device suitable for real-time and high-reliability scenarios.

CN224355000UActive Publication Date: 2026-06-12JUXIN INTEGRATED CIRCUIT CHIP (HEFEI) CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
JUXIN INTEGRATED CIRCUIT CHIP (HEFEI) CO LTD
Filing Date
2025-05-27
Publication Date
2026-06-12

AI Technical Summary

⚠Technical Problem

NAND flash memory is susceptible to external interference in high-density storage, which can lead to data errors. Furthermore, error correction code algorithms increase the complexity of controller design and power consumption, affecting read and write efficiency and making it difficult to meet the low latency and low power consumption requirements of mobile devices.

⚗Method used

It adopts a combination structure of selection transistor and floating gate transistor. The floating electrode state reduces interference between memory cells. Combined with the cache and main controller, it realizes direct access and low-latency operation, and avoids the use of error correction code.

🎯Benefits of technology

It achieves high-density, high-reliability storage, reduces power consumption and latency, is suitable for real-time and high-reliability scenarios, and improves the performance and reliability of storage devices.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model provides a storage device with low delay characteristic, include: a plurality of selection transistor, a plurality of floating gate transistor, a plurality of floating gate transistor respectively with bit line and word line electric nature connection, wherein a plurality of floating gate transistor respectively with corresponding selection transistor electric nature connection, and with the form of storage unit integrated in same flash memory chip, and floating gate transistor includes control grid, source electrode and drain electrode, wherein control grid and word line electric nature connection, any electrode in source electrode or drain electrode is in floating state, and another electrode electric nature connection is in bit line, and main controller is electrically connected with host computer and flash memory chip, and according to the instruction random access any storage unit of host computer. The utility model can provide high density and high reliability storage space under the premise of not using error correction related technology.
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