Storage device with low latency characteristics

Abstract

The utility model provides a storage device with low delay characteristic, include: a plurality of selection transistor, a plurality of floating gate transistor, a plurality of floating gate transistor respectively with bit line and word line electric nature connection, wherein a plurality of floating gate transistor respectively with corresponding selection transistor electric nature connection, and with the form of storage unit integrated in same flash memory chip, and floating gate transistor includes control grid, source electrode and drain electrode, wherein control grid and word line electric nature connection, any electrode in source electrode or drain electrode is in floating state, and another electrode electric nature connection is in bit line, and main controller is electrically connected with host computer and flash memory chip, and according to the instruction random access any storage unit of host computer. The utility model can provide high density and high reliability storage space under the premise of not using error correction related technology.

Description

Technical Field

[0001] This utility model relates to the field of storage technology, and in particular to a storage device with low latency characteristics. Background Technology

[0002] Embedded multimedia card standards use NAND flash memory as the core storage medium, and due to its high storage density and low cost, it is widely integrated into mobile devices. However, NAND flash memory has inherent defects: the charge of storage cells is susceptible to external interference or its own leakage, leading to unexpected bit flips and data errors. Furthermore, as the manufacturing process shrinks to the tens of nanometers level, the reduction in cell size exacerbates charge leakage, further reducing data stability. Moreover, the charge coupling effect between adjacent cells during read and write operations is particularly significant in multi-level storage structures, increasing the risk of data corruption.

[0003] Therefore, ensuring the reliability of multimedia cards relies on error correction code algorithms. However, high-density storage requires complex error correction mechanisms such as LDPC codes or BCH codes, leading to a surge in controller design complexity and a simultaneous increase in hardware resource consumption and production costs. Furthermore, the error correction process requires additional storage of verification data and introduces processing latency, impacting read / write efficiency. The high power consumption of these algorithms also conflicts with the low power consumption requirements of mobile devices. Utility Model Content

[0004] The purpose of this invention is to provide a storage device with low latency characteristics, which can provide high-density and high-reliability storage space without using error correction related technologies.

[0005] To solve the above-mentioned technical problems, this utility model is achieved through the following technical solution:

[0006] This utility model provides a storage device with low latency characteristics, comprising:

[0007] Multiple selectable transistors;

[0008] A plurality of floating-gate transistors are electrically connected to a bit line and a word line, respectively. Each floating-gate transistor is electrically connected to a corresponding select transistor and integrated in the same flash memory chip as a memory cell. Each floating-gate transistor includes a control gate, a source electrode, and a drain electrode. The control gate is electrically connected to the word line, either the source electrode or the drain electrode is in a floating state, and the other electrode is electrically connected to the bit line.

[0009] The main controller is electrically connected to the host computer and the flash memory chip, and randomly accesses any of the storage units according to the instructions of the host computer.

[0010] The main controller is responsible for address decoding, timing control, and data transmission. It supports rapid response to commands from the host computer and can randomly access any memory cell. Since each memory cell can be directly accessed, interference between adjacent cells is greatly reduced. The low error rate avoids the intervention of ECC devices and algorithms, and the floating electrode state ensures that individual memory cells will not be directly damaged by the high voltage of direct access. Therefore, although such a storage device uses independent memory cells, it can still provide high storage density, thus ensuring both storage density and improved storage reliability.

[0011] In one embodiment of this utility model, the floating state is either an idle state or the electrode is in a low potential state, wherein the electrode voltage in the low potential state is higher than the ground voltage.

[0012] Floating connection not only helps prevent device breakdown, but also reduces power consumption as the electrodes in this state do not consume current. Floating connection can also be used to isolate circuits and prevent signal interference. Furthermore, the low potential ensures stable electrode potential, preventing signal drift and helping to suppress noise interference in the circuit.

[0013] In one embodiment of the present invention, the storage device further includes a cache, which is electrically connected to the main controller and the flash memory chip, and stores the operating data of the main controller and the temporary data of the storage device.

[0014] By integrating a cache to store both main controller runtime data and temporary data, low-latency access, high-efficiency operation, and extended flash memory lifespan are achieved, making it particularly suitable for scenarios with high real-time requirements and frequent writes. In the future, intelligent caching algorithms and heterogeneous storage technologies can be combined to further optimize the performance and reliability of storage devices.

[0015] In one embodiment of this utility model, the flash memory chip and the main controller are integrated in the same package.

[0016] The storage device of this invention meets the standardized packaging (such as BGA, LGA) and pin layout defined by the eMMC protocol. Through standardized interfaces, simplified system design, and optimized performance and reliability, it realizes a storage solution with high integration, low power consumption, and ease of use.

[0017] In one embodiment of this utility model, the storage device further includes:

[0018] Multiple address pins are disposed on the package of the storage device, allowing the address pins to be electrically connected to the host computer and to receive address signals sent by the host computer; and

[0019] A cache interface is electrically connected to the cache and the plurality of address pins, and the cache interface receives address signals and sends them to the cache.

[0020] This invention significantly improves the access speed and energy efficiency of storage devices through direct connection of address pins and collaboration with cache interface, making it particularly suitable for scenarios requiring low latency and high reliability.

[0021] In one embodiment of the present invention, the storage device includes an address decoder, which is electrically connected to the cache and receives and decodes the address signal, wherein the address signal is parsed and converted into an access address, and the access address is an address for any of the storage units.

[0022] By leveraging hardware-level address resolution and caching in the address decoder, nanosecond-level precise addressing, energy efficiency optimization, and reliability enhancement can be achieved, making it particularly suitable for scenarios with high real-time and high reliability requirements (such as autonomous driving and industrial control). Future development can further overcome performance bottlenecks through heterogeneous integration (such as 3D stacked decoders and storage units).

[0023] In one embodiment of this utility model, the flash memory chip stores control firmware, and the control firmware can be invoked by the main controller.

[0024] By storing the control firmware in a flash memory chip and enabling direct execution by the main controller, and then using XIP technology to directly access the stored firmware, not only is memory saved, startup accelerated, and reliability improved, but it also aligns with the technical solution proposed in this invention, further maximizing the usable storage space of the flash memory chip within a limited space. Furthermore, based on this setup, future integration with novel non-volatile memory (such as MRAM and ReRAM) can further overcome speed and lifespan limitations, driving performance innovation in edge computing and AIoT devices.

[0025] In one embodiment of this invention, the storage device includes a serial interface and an eMMC interface, wherein the main controller is electrically connected to the host computer through the serial interface, and the main controller is electrically connected to the flash memory chip through the eMMC interface. This invention enables high-bandwidth, low-latency, and low-power storage access, breaking through the performance bottleneck of traditional flash memory interfaces, and is particularly suitable for high-data-throughput scenarios such as AI, 5G, and automotive applications.

[0026] In one embodiment of this utility model, the plurality of storage cells are distributed in a matrix array.

[0027] Providing a matrix distribution not only adapts to the word line and bit line allocation structure, but also helps to improve the storage density of storage devices.

[0028] In one embodiment of the present invention, in the floating gate transistor, the length of the control gate is less than 55 nm, and the minimum length of the control gate is 10 nm.

[0029] Each memory cell can be directly accessed, and the device provided by this invention solves the problem of high voltage breakdown, thus further reducing the length of the control gate, thereby increasing the distribution density of memory cells and further increasing the storage density of the storage device.

[0030] As described above, this invention provides a storage device with low latency characteristics, significantly reducing interference and bit error rate between storage cells. It meets industrial-grade data integrity requirements without the need for ECC error correction, simplifies circuit design, and reduces costs, making it suitable for real-time storage systems (such as autonomous driving decision-making). Furthermore, this invention supports the eMMC protocol standard interface, reducing PCB wiring length, lowering dynamic power consumption by 40%, and using floating electrodes and caches to reduce flash memory erase / write cycles, thus extending device lifespan.

[0031] Of course, any product implementing this utility model does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of a storage device in one embodiment of the present invention.

[0034] Figure 2 This is a schematic diagram of the connection structure between the storage unit and the word line bit line in one embodiment of the present invention.

[0035] Figure 3 This is a schematic diagram of the structure of a floating gate transistor in one embodiment of the present invention.

[0036] Figure 4 This is a schematic diagram of the main controller in one embodiment of the present invention.

[0037] In the diagram: 100, storage device; 200, flash memory chip; 300, storage cell; 310, floating gate transistor; 311, tunnel oxide layer; 312, floating gate; 313, control gate; S, source electrode; D, drain electrode; 320, select transistor; 400, main controller; 410, processor; 420, logic processing clock unit; 430, first clock unit; 440, second clock unit; 500, register; 600, address pin; 700, address decoder; 800, cache interface; WL, word line; BL, bit line; VCC, first power supply module; VCCQ, second power supply module; VDDi, third power supply module. Detailed Implementation

[0038] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0039] Please see Figures 1 to 3As shown, this utility model provides a storage device 100 with low latency characteristics. The storage device 100 includes multiple selection transistors 320 and multiple floating-gate transistors 310, as well as a main controller 400. The multiple floating-gate transistors 310 are electrically connected to the bit line BL and the word line WL, respectively, and are also electrically connected to their corresponding selection transistors 320. They are integrated in the same flash memory chip 200 as storage cells 300. Each floating-gate transistor 310 includes a control gate 313, a source electrode S, and a drain electrode D. The control gate 313 is electrically connected to the word line WL, and either the source electrode S or the drain electrode D is in a floating state, while the other electrode is electrically connected to the bit line BL. The main controller 400 is electrically connected to a host computer and the flash memory chip 200, and randomly accesses any storage cell 300 according to instructions from the host computer. In this embodiment, each storage cell 300 can be individually called by the main controller 400 and independently completes data storage. In this embodiment, the main controller 400 is responsible for address decoding, timing control, and data transmission, supports rapid response to host computer instructions, and can randomly access any memory cell 300. Since each memory cell 300 can be directly accessed, interference between adjacent memory cells 300 is greatly reduced. The low error rate avoids the intervention of ECC devices and algorithms, thereby increasing the usable area of ​​the chip. The floating electrode state ensures that a single memory cell 300 will not be directly damaged by the high voltage of direct access. Therefore, although such a storage device 100 uses independent memory cells 300, it can still provide a high storage density, thereby ensuring the storage density of the storage device 100 and improving the storage reliability of the storage device 100.

[0040] Please see Figure 2 and Figure 3 As shown, in one embodiment of this invention, the floating state is either an idle state or the electrode is in a low-potential state, wherein the electrode voltage in the low-potential state is higher than the ground voltage. The idle state refers to the electrode being unconnected to any device. The specific voltage value of the low-potential state can be set by the designer according to the different devices. In this embodiment, the low-potential state voltage is, for example, 1V. For the floating gate transistor 310, one electrode is in a floating state, and the other end is connected to a high voltage, such as 7V. The lower voltage difference can prevent the floating gate transistor 310 from being directly broken down, thus the device size provided by this invention can be made smaller. Specifically, the size of the control gate 313 can be less than 130nm, and specifically, less than, for example, 55nm. The floating state not only helps prevent device breakdown, but the electrode in the floating state does not consume current, which helps reduce power consumption. The floating state can also be used to isolate circuits and prevent signal interference. Furthermore, the low-potential state ensures stable electrode potential, avoids signal drift, and also helps suppress noise interference in the circuit.

[0041] Please see Figure 1 As shown, in one embodiment of this utility model, the storage device 100 further includes a cache 500, which is electrically connected to the main controller 400 and the flash memory chip 200. The cache 500 stores the operating data of the main controller 400 and the temporary data of the storage device 100. In this embodiment, the cache 500 can be a static random access memory (SRAM). By integrating the cache 500 and storing the operating data and temporary data of the main controller 400, low-latency access, high-efficiency operation, and extended flash memory lifespan are achieved, making it particularly suitable for scenarios with high real-time requirements and frequent writes.

[0042] Please see Figure 1 As shown, in one embodiment of this invention, the flash memory chip 200 and the main controller 400 are integrated into the same package. Within the package, various interfaces, an address decoder 700, a cache 500, and other devices are also provided. Therefore, the storage device 100 provided by this invention is suitable for various mobile devices. The storage device 100 of this invention conforms to the standardized packaging and pin layout defined by the eMMC protocol. Through standardized interfaces, simplified system design, and optimized performance and reliability, it achieves a highly integrated, low-power, and easy-to-use storage solution. The standardized packaging defined by the eMMC protocol includes, for example, BGA and LGA packages.

[0043] Please see Figure 1 As shown, in one embodiment of this invention, the storage device 100 further includes multiple address pins 600 and a cache interface 800. The multiple address pins 600 are disposed on the package of the storage device 100, electrically connected to a host computer, and receive address signals sent by the host computer. In this embodiment, there can be multiple pins disposed on the package, with the function and connection object of the pins defined according to the device function. The address pins 600 are used to receive address signals. For example, if there are 20 address pins 600, then 220 addresses can be addressed through the address pins 600, that is, addressing any storage unit 300 can be achieved through multiple address pins 600. In this embodiment, the cache interface 800 is electrically connected to the cache 500 and the multiple address pins 600, and the cache interface 800 receives address signals and sends them to the cache 500. This invention, through the direct connection of the address pins 600 and the collaboration of the cache interface 800, significantly improves the access speed and energy efficiency of the storage device 100, and is particularly suitable for scenarios requiring low latency and high reliability.

[0044] Please see Figure 1As shown, in one embodiment of this utility model, the storage device 100 includes an address decoder 700, which is electrically connected to the cache 500 and receives and decodes address signals. The address signals are parsed and converted into access addresses, which are addresses for any storage unit 300. Through hardware-level address parsing and cache coordination of the address decoder 700, nanosecond-level precise addressing, energy efficiency optimization, and reliability improvement can be achieved, making it particularly suitable for scenarios with high real-time and high reliability requirements, such as autonomous driving and industrial control.

[0045] Please see Figure 1 As shown, in one embodiment of this utility model, the flash memory chip 200 stores control firmware, and the control firmware can be read and invoked by the main controller 400. In this embodiment, storing the control firmware in the flash memory chip 200 and supporting direct execution by the main controller 400 allows for direct invocation of the stored firmware through XIP technology. This not only achieves memory saving, startup acceleration, and reliability improvement, but also aligns with the technical solution proposed in this utility model, further expanding the usable storage space of the flash memory chip 200 within a limited space.

[0046] In one embodiment of this utility model, the storage device 100 includes a serial interface and an eMMC interface, wherein the storage host controller 400 is electrically connected to a host computer via the serial interface, which may be, for example, an SPI interface. In this embodiment, the flash memory chip 200 and the host controller 400 are electrically connected via the eMMC interface. The eMMC interface specifically includes CLK signal lines, CMD signal lines, and DAT0-7 signal lines, etc.

[0047] Please see Figure 1 and Figure 4As shown, in one embodiment of this utility model, the main controller 400 includes a processor 410, a first clock unit 430, a second clock unit 440, and a logic processing clock unit 420. The processor 410 is, for example, an ARM processor 410. The first clock unit 430 provides clock signals for interconnection between the main controller 400 and the host computer, and specifically handles the signal timing of signal lines such as the RESET signal, CMD signal, multi-channel data signals DAT (0-7), clock signal CLK, and encoded data. The second clock unit 440 provides clock signals for interconnection between the main controller 400 and the flash memory chip 200, and specifically handles the timing of signal transmission and data transmission. The logic processing clock unit 420 provides clock signals for the internal operation of the main controller 400. In this embodiment, the storage device 100 also includes a first power supply module VCC, a second power supply module VCCQ, and a third power supply module VDDi. The first power supply module VCC supplies power to the flash memory chip 200 and the second clock unit 440. The second power supply module VCCQ supplies power to the processor 410 and the first clock unit 430. The third clock module supplies power to the internal components of the main controller 400.

[0048] The embodiments of this utility model disclosed above are merely illustrative of the present utility model. The embodiments do not exhaustively describe all details, nor do they limit the utility model to the specific implementations described. Obviously, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to better understand and utilize it. This utility model is limited only by the claims and their full scope and equivalents.

Claims

1. A storage device with low latency characteristics, characterized in that, include: Multiple selectable transistors; Multiple floating-gate transistors are electrically connected to bit lines and word lines, respectively. Each floating-gate transistor is electrically connected to a corresponding select transistor and integrated in the same flash memory chip in the form of a memory cell. Each floating-gate transistor includes a control gate, a source electrode, and a drain electrode. The control gate is electrically connected to the word line, and either the source electrode or the drain electrode is in a floating state, while the other electrode is electrically connected to the bit line. as well as The main controller is electrically connected to the host computer and the flash memory chip, and randomly accesses any of the storage units according to the instructions of the host computer.

2. The storage device with low latency characteristics according to claim 1, characterized in that, The floating state is either an idle state or the electrode is in a low potential state, wherein the electrode voltage in the low potential state is higher than the ground voltage.

3. The storage device with low latency characteristics according to claim 1, characterized in that, The storage device further includes a cache, which is electrically connected to the main controller and the flash memory chip, and stores the main controller's operating data and the storage device's temporary data.

4. The storage device with low latency characteristics according to claim 3, characterized in that, The flash memory chip and the main controller are integrated into the same package.

5. The storage device with low latency characteristics according to claim 4, characterized in that, The storage device also includes: Multiple address pins are disposed on the package of the storage device, allowing the address pins to be electrically connected to the host computer and to receive address signals sent by the host computer; and A cache interface is electrically connected to the cache and the plurality of address pins, and the cache interface receives address signals and sends them to the cache.

6. The storage device with low latency characteristics according to claim 5, characterized in that, The storage device includes an address decoder electrically connected to the cache and receiving and decoding the address signal, wherein the address signal is parsed and converted into an access address, and the access address is an address for any of the storage units.

7. The storage device with low latency characteristics according to claim 1, characterized in that, The flash memory chip stores the control firmware and allows the control firmware to be invoked by the main controller.

8. The storage device with low latency characteristics according to claim 1, characterized in that, The storage device includes a serial interface and an eMMC interface, wherein the main controller is electrically connected to the host computer through the serial interface, and the main controller is electrically connected to the flash memory chip through the eMMC interface.

9. The storage device with low latency characteristics according to claim 1, characterized in that, The multiple storage units are distributed in a matrix array.

10. The storage device with low latency characteristics according to claim 1, characterized in that, In the floating gate transistor, the minimum length of the control gate is 10 nm.

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